Merge commit 'd52cfbba89817e2c062fc02ffc4ad1594a365445'

* commit 'd52cfbba89817e2c062fc02ffc4ad1594a365445':
  soc: rockchip: system_monitor: Add support to adjust volt before online first cpu
  cpufreq: dt: Fix crash when cpu offline at low temperature
  cpufreq: rockchip: Implement rockchip_cpufreq_online/offline()
  net: wireless: rockchip_wlan: Add missing BH locking around __napi_schdule()
  ASoC: rockchip: asrc: Fix asrc get parent clock error
  clk: rockchip: rk3506: Remove CLK_IS_CRITICAL flag for v1pll
  clk: rockchip: rk3506: Make clk_ddrc critical
  arm64: dts: rockchip: rk3576-vehicle-evb-v20: enable saiX
  drm/bridge: synopsys: dw-hdmi-qp: Check that necessary hdmi clock is on when hdmi bind
  ARM: dts: rockchip: rv1106: Remove otp arb and pmc clock
  arm64: dts: rockchip: rk3562: Remove otp arb clock
  arm64: dts: rockchip: rk3588s: Remove otp arb clock
  clk: rockchip: rv1106: Remove clk_pmc_otp and clk_otpc_arb
  clk: rockchip: rk3562: remove clk_otpc_arb
  clk: rockchip: rk3588: Removd clk_otpc_arb
  usb: dwc2: fix dwc2 resume failed when device is connected
  phy: rockchip: mipi-dcphy: limit the maximum addr according to DC-PHY register map
  media: rockchip: isp: fix isp39 unite stats frame id

Change-Id: I6af023446010a6df94e79222124d9157040d20b5

arch/arm/boot/dts/rv1106.dtsi

@@ -753,9 +753,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
-			 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>,
-			 <&cru CLK_OTPC_ARB>, <&cru CLK_PMC_OTP>;
-		clock-names = "usr", "sbpi", "apb", "phy", "arb", "pmc";
+			 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>;
+		clock-names = "usr", "sbpi", "apb", "phy";
 		resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>,
 			 <&cru SRST_P_OTPC_NS>, <&cru SRST_P_OTP_MASK>,
 			 <&cru SRST_OTPC_ARB>, <&cru SRST_PMC_OTP>;

arch/arm64/boot/dts/rockchip/rk3562.dtsi

@@ -2753,9 +2753,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
-			 <&cru PCLK_OTPC_NS>, <&cru CLK_OTPC_ARB>,
-			 <&cru PCLK_OTPPHY>;
-		clock-names = "usr", "sbpi", "apb", "arb", "phy";
+			 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>;
+		clock-names = "usr", "sbpi", "apb", "phy";
 		resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>,
 			 <&cru SRST_P_OTPC_NS>, <&cru SRST_OTPC_ARB>,
 			 <&cru SRST_P_OTPPHY>;

arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20-audio.dtsi

@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/ {
+
+	dummy_codec0: dummy-codec@0 {
+		status = "okay";
+		compatible = "rockchip,dummy-codec";
+		#sound-dai-cells = <0>;
+	};
+
+	dummy_codec1: dummy-codec@1 {
+		status = "okay";
+		compatible = "rockchip,dummy-codec";
+		#sound-dai-cells = <0>;
+	};
+
+	bt_codec: bt-codec {
+		compatible = "delta,dfbmcs320";
+		#sound-dai-cells = <1>;
+		status = "okay";
+	};
+
+	sound0 {
+		status = "okay";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "rockchip,tdm";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,cpu {
+			sound-dai = <&sai1>;
+			dai-tdm-slot-num = <8>;
+			dai-tdm-slot-width = <32>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&dummy_codec0>;
+		};
+	};
+
+	sound1 {
+		status = "okay";
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "rockchip,low-latency";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,bitclock-master = <&dummy_clk1>;
+		simple-audio-card,frame-master = <&dummy_clk1>;
+		simple-audio-card,cpu {
+			sound-dai = <&sai4>;
+			dai-tdm-slot-num = <2>;
+			dai-tdm-slot-width = <32>;
+		};
+		dummy_clk1: simple-audio-card,codec {
+			sound-dai = <&dummy_codec1>;
+		};
+	};
+
+	sound2 {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "dsp_a";
+		simple-audio-card,bitclock-inversion;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "rockchip,bt";
+		simple-audio-card,cpu {
+			sound-dai = <&sai2>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&bt_codec 1>;
+		};
+	};
+};
+
+&sai1 {
+	status = "okay";
+	rockchip,tdm-tx-lanes = <3>;
+	rockchip,tdm-rx-lanes = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sai1m0_lrck
+			&sai1m0_sclk
+			&sai1m0_sdi0
+			&sai1m0_sdi1
+			&sai1m0_sdo0
+			&sai1m0_sdo1
+			&sai1m0_sdo2>;
+};
+
+&sai2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&sai2m0_lrck
+			&sai2m0_sclk
+			&sai2m0_sdi
+			&sai2m0_sdo>;
+};
+
+&sai4 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&sai4m2_lrck
+			&sai4m2_sclk
+			&sai4m2_sdi
+			&sai4m2_sdo>;
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0m0_csn0 &spi0m0_pins>;
+	spi-dev@0 {
+		compatible = "rockchip,spidev";
+		reg = <0x0>;
+		spi-max-frequency = <50000000>;
+		spi-lsb-first;
+	};
+};

arch/arm64/boot/dts/rockchip/rk3576-vehicle-evb-v20.dtsi

@@ -5,6 +5,7 @@
  */
 
 #include "rk3576-vehicle.dtsi"
+#include "rk3576-vehicle-evb-v20-audio.dtsi"
 #include "rk3576-rk806.dtsi"
 
 / {
@@ -119,28 +120,6 @@
 		off-on-delay-us = <16000>;
 		vin-supply = <&vcc5v0_buck>;
 	};
-
-	dummy_codec: dummy-codec {
-		status = "okay";
-		compatible = "rockchip,dummy-codec";
-		#sound-dai-cells = <0>;
-	};
-
-	vehicle_adsp_sound: vehicle-adsp-sound {
-		status = "okay";
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "rockchip,tdm";
-		simple-audio-card,format = "i2s";
-		simple-audio-card,mclk-fs = <256>;
-		simple-audio-card,cpu {
-			sound-dai = <&sai1>;
-			dai-tdm-slot-num = <8>;
-			dai-tdm-slot-width = <32>;
-		};
-		simple-audio-card,codec {
-			sound-dai = <&dummy_codec>;
-		};
-	};
 };
 
 &combphy0_ps {
@@ -384,36 +363,10 @@
 	connect = <&vp0_out_hdmi>;
 };
 
-&sai1 {
-	status = "okay";
-	rockchip,tdm-tx-lanes = <3>;
-	rockchip,tdm-rx-lanes = <2>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sai1m0_lrck
-		     &sai1m0_sclk
-		     &sai1m0_sdi0
-		     &sai1m0_sdi1
-		     &sai1m0_sdo0
-		     &sai1m0_sdo1
-		     &sai1m0_sdo2>;
-};
-
 &sdmmc {
 	status = "okay";
 };
 
-&spi0 {
-	status = "okay";
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi0m0_csn0 &spi0m0_pins>;
-	spi-dev@0 {
-		compatible = "rockchip,spidev";
-		reg = <0x0>;
-		spi-max-frequency = <50000000>;
-		spi-lsb-first;
-	};
-};
-
 &ufs {
 	vcc-supply = <&vcc_ufs_s0>;
 	vccq-supply = <&vcc1v2_ufs_vccq_s0>;

arch/arm64/boot/dts/rockchip/rk3588s.dtsi

@@ -6609,8 +6609,8 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
-			 <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>;
-		clock-names = "otpc", "apb", "arb", "phy";
+			 <&cru CLK_OTP_PHY_G>;
+		clock-names = "otpc", "apb", "phy";
 		resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
 			 <&cru SRST_OTPC_ARB>;
 		reset-names = "otpc", "apb", "arb";

drivers/clk/rockchip/clk-rk3506.c

@@ -159,7 +159,7 @@ static struct rockchip_pll_clock rk3506_pll_clks[] __initdata = {
 		     CLK_IS_CRITICAL, RK3506_PLL_CON(8),
 		     RK3506_MODE_CON, 2, 0, 0, rk3506_pll_rates),
 	[v1pll] = PLL(pll_rk3328, PLL_V1PLL, "v1pll", mux_pll_p,
-		     CLK_IS_CRITICAL, RK3506_PLL_CON(16),
+		     0, RK3506_PLL_CON(16),
 		     RK3506_MODE_CON, 4, 1, 0, rk3506_pll_rates),
 };
 
@@ -178,7 +178,7 @@ static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
 			RK3506_CLKGATE_CON(0), 2, GFLAGS),
 	GATE(CLK_V0PLL_GATE, "clk_v0pll_gate", "v0pll", CLK_IS_CRITICAL,
 			RK3506_CLKGATE_CON(0), 3, GFLAGS),
-	GATE(CLK_V1PLL_GATE, "clk_v1pll_gate", "v1pll", CLK_IS_CRITICAL,
+	GATE(CLK_V1PLL_GATE, "clk_v1pll_gate", "v1pll", 0,
 			RK3506_CLKGATE_CON(0), 4, GFLAGS),
 	COMPOSITE_NOMUX(CLK_GPLL_DIV, "clk_gpll_div", "clk_gpll_gate", CLK_IS_CRITICAL,
 			RK3506_CLKSEL_CON(0), 6, 4, DFLAGS,
@@ -189,7 +189,7 @@ static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
 	COMPOSITE_NOMUX(CLK_V0PLL_DIV, "clk_v0pll_div", "clk_v0pll_gate", CLK_IS_CRITICAL,
 			RK3506_CLKSEL_CON(1), 0, 4, DFLAGS,
 			RK3506_CLKGATE_CON(0), 7, GFLAGS),
-	COMPOSITE_NOMUX(CLK_V1PLL_DIV, "clk_v1pll_div", "clk_v1pll_gate", CLK_IS_CRITICAL,
+	COMPOSITE_NOMUX(CLK_V1PLL_DIV, "clk_v1pll_div", "clk_v1pll_gate", 0,
 			RK3506_CLKSEL_CON(1), 4, 4, DFLAGS,
 			RK3506_CLKGATE_CON(0), 8, GFLAGS),
 	COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX0, "clk_int_voice_matrix0", "clk_v0pll_gate", 0,
@@ -394,7 +394,7 @@ static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
 			RK3506_CLKGATE_CON(10), 0, GFLAGS),
 	GATE(ACLK_DDRC_1, "aclk_ddrc_1", "clk_ddrc_src", CLK_IGNORE_UNUSED,
 			RK3506_CLKGATE_CON(10), 1, GFLAGS),
-	GATE(CLK_DDRC, "clk_ddrc", "clk_ddrc_src", CLK_IGNORE_UNUSED,
+	GATE(CLK_DDRC, "clk_ddrc", "clk_ddrc_src", CLK_IS_CRITICAL,
 			RK3506_CLKGATE_CON(10), 3, GFLAGS),
 	GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IGNORE_UNUSED,
 			RK3506_CLKGATE_CON(10), 4, GFLAGS),

drivers/clk/rockchip/clk-rk3562.c

@@ -744,8 +744,6 @@ static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = {
 	COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", CLK_IGNORE_UNUSED,
 			RK3562_PERI_CLKSEL_CON(44), 8, 8, DFLAGS,
 			RK3562_PERI_CLKGATE_CON(14), 5, GFLAGS),
-	GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
-			RK3562_PERI_CLKGATE_CON(14), 6, GFLAGS),
 	GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_peri", 0,
 			RK3562_PERI_CLKGATE_CON(14), 7, GFLAGS),
 	GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri", 0,

drivers/clk/rockchip/clk-rk3588.c

@@ -1148,8 +1148,6 @@ static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
 			RK3588_CLKGATE_CON(18), 9, GFLAGS),
 	GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,
 			RK3588_CLKGATE_CON(18), 10, GFLAGS),
-	GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
-			RK3588_CLKGATE_CON(18), 11, GFLAGS),
 	GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
 			RK3588_CLKGATE_CON(18), 13, GFLAGS),
 	GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,

drivers/clk/rockchip/clk-rv1106.c

@@ -891,8 +891,6 @@ static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
 			RV1106_VOCLKSEL_CON(2), 1, 6, DFLAGS),
 	GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
 			RV1106_VOCLKGATE_CON(2), 13, GFLAGS),
-	GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
-			RV1106_VOCLKGATE_CON(2), 11, GFLAGS),
 	GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
 			RV1106_VOCLKGATE_CON(2), 3, GFLAGS),
 	GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
@@ -902,15 +900,11 @@ static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
 			RV1106_VOCLKGATE_CON(2), 6, GFLAGS),
 	GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_vo_root", 0,
 			RV1106_VOCLKGATE_CON(2), 7, GFLAGS),
-	GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", 0,
-			RV1106_VOCLKGATE_CON(2), 9, GFLAGS),
 	COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", 0,
 			RV1106_VOCLKSEL_CON(3), 13, 3, DFLAGS,
 			RV1106_VOCLKGATE_CON(2), 10, GFLAGS),
 	GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_vo_root", 0,
 			RV1106_VOCLKGATE_CON(2), 14, GFLAGS),
-	GATE(CLK_PMC_OTP, "clk_pmc_otp", "clk_sbpi_otpc_s", 0,
-			RV1106_VOCLKGATE_CON(2), 15, GFLAGS),
 	GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
 			RV1106_VOCLKGATE_CON(0), 7, GFLAGS),
 	GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,

drivers/cpufreq/cpufreq-dt.c

@@ -160,12 +160,18 @@ out_clk_put:
 
 static int cpufreq_online(struct cpufreq_policy *policy)
 {
+#ifdef CONFIG_ARCH_ROCKCHIP
+	return rockchip_cpufreq_online(policy->cpu);
+#endif
 	/* We did light-weight tear down earlier, nothing to do here */
 	return 0;
 }
 
 static int cpufreq_offline(struct cpufreq_policy *policy)
 {
+#ifdef CONFIG_ARCH_ROCKCHIP
+	return rockchip_cpufreq_offline(policy->cpu);
+#endif
 	/*
 	 * Preserve policy->driver_data and don't free resources on light-weight
 	 * tear down.

drivers/cpufreq/rockchip-cpufreq.c

@@ -571,6 +571,42 @@ static int rockchip_cpufreq_suspend(struct cpufreq_policy *policy)
 	return ret;
 }
 
+int rockchip_cpufreq_online(int cpu)
+{
+	struct cluster_info *cluster;
+	struct rockchip_opp_info *opp_info;
+
+	cluster = rockchip_cluster_info_lookup(cpu);
+	if (!cluster)
+		return -EINVAL;
+	opp_info = &cluster->opp_info;
+
+	opp_info->is_runtime_active = true;
+	if (opp_info->data && opp_info->data->set_read_margin)
+		opp_info->data->set_read_margin(opp_info->dev, opp_info,
+						opp_info->target_rm);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(rockchip_cpufreq_online);
+
+int rockchip_cpufreq_offline(int cpu)
+{
+	struct cluster_info *cluster;
+	struct rockchip_opp_info *opp_info;
+
+	cluster = rockchip_cluster_info_lookup(cpu);
+	if (!cluster)
+		return -EINVAL;
+	opp_info = &cluster->opp_info;
+
+	opp_info->is_runtime_active = false;
+	opp_info->current_rm = UINT_MAX;
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(rockchip_cpufreq_offline);
+
 static int rockchip_cpufreq_add_monitor(struct cluster_info *cluster,
 					struct cpufreq_policy *policy)
 {

drivers/cpufreq/rockchip-cpufreq.h

@@ -6,6 +6,8 @@
 #define __ROCKCHIP_CPUFREQ_H
 
 #if IS_ENABLED(CONFIG_ARM_ROCKCHIP_CPUFREQ)
+int rockchip_cpufreq_online(int cpu);
+int rockchip_cpufreq_offline(int cpu);
 int rockchip_cpufreq_adjust_table(struct device *dev);
 int rockchip_cpufreq_opp_set_rate(struct device *dev, unsigned long target_freq);
 #else

drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c

@@ -71,6 +71,8 @@
 #define HDMI_HDCP2_AUTH		BIT(1)
 #define HDMI_HDCP14_AUTH	BIT(0)
 
+#define HDMI_CTRL_CLK_EN	0x15
+
 static const unsigned int dw_hdmi_cable[] = {
 	EXTCON_DISP_HDMI,
 	EXTCON_NONE,
@@ -4317,7 +4319,8 @@ static struct dw_hdmi_qp *dw_hdmi_qp_probe(struct platform_device *pdev,
 	hdmi_writel(hdmi, hdmi->refclk_rate, TIMER_BASE_CONFIG0);
 	hdmi->logo_plug_out = false;
 	if (hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data) == connector_status_connected &&
-	    hdmi_readl(hdmi, I2CM_INTERFACE_CONTROL0)) {
+	    hdmi_readl(hdmi, I2CM_INTERFACE_CONTROL0) &&
+	    (hdmi_readl(hdmi, CMU_STATUS) & HDMI_CTRL_CLK_EN) == HDMI_CTRL_CLK_EN) {
 		hdmi->initialized = true;
 		hdmi->disabled = false;
 	}

drivers/media/platform/rockchip/isp/isp_stats_v39.c

@@ -254,9 +254,11 @@ rkisp_stats_send_meas_v39(struct rkisp_isp_stats_vdev *stats_vdev,
 	u32 cur_frame_id = meas_work->frame_id;
 
 	if (!stats_vdev->rdbk_drop) {
-		if (cur_buf)
+		if (cur_buf) {
 			cur_stat_buf = cur_buf->vaddr[0];
-
+			cur_stat_buf->frame_id = cur_frame_id;
+			cur_stat_buf->params_id = params_vdev->cur_frame_id;
+		}
 		/* buffer done when frame of right handle */
 		if (dev->unite_div > ISP_UNITE_DIV1) {
 			if (dev->unite_index == ISP_UNITE_LEFT) {

drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/dhd_linux_lb.c

@@ -1131,6 +1131,7 @@ dhd_napi_schedule(void *info)
 	DHD_GENERAL_UNLOCK(&dhd->pub, flags);
 #endif /* OEM_ANDROID */
 
+	local_bh_disable();
 	/* add napi_struct to softnet data poll list and raise NET_RX_SOFTIRQ */
 	if (napi_schedule_prep(&dhd->rx_napi_struct)) {
 
@@ -1151,6 +1152,7 @@ dhd_napi_schedule(void *info)
 		raise_softirq(NET_RX_SOFTIRQ);
 #endif /* WAKEUP_KSOFTIRQD_POST_NAPI_SCHEDULE */
 	}
+	local_bh_enable();
 
 	/*
 	 * If the rx_napi_struct was already running, then we let it complete

drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c

@@ -217,6 +217,8 @@
 #define RX_S0D3_DESKEW_CON0		(0xF40)
 #define RX_S0D3_DESKEW_CON2		(0xF48)
 #define RX_S0D3_DESKEW_CON4		(0xF50)
+#define RX_S0D3_ADI_STAT0		(0XFEC)
+#define MIPI_DCPHY_MAX_REGISGER		RX_S0D3_ADI_STAT0
 
 struct samsung_mipi_dphy_timing {
 	unsigned int max_lane_mbps;
@@ -2363,7 +2365,7 @@ static const struct regmap_config samsung_mipi_dcphy_regmap_config = {
 	.reg_bits = 32,
 	.val_bits = 32,
 	.reg_stride = 4,
-	.max_register = 0x10000,
+	.max_register = MIPI_DCPHY_MAX_REGISGER,
 };
 
 static int samsung_mipi_dcphy_probe(struct platform_device *pdev)

drivers/soc/rockchip/rockchip_system_monitor.c

@@ -1088,19 +1088,8 @@ static void rockchip_high_temp_adjust(struct monitor_dev_info *info,
 	}
 }
 
-int rockchip_monitor_suspend_low_temp_adjust(int cpu)
+static int rockchip_monitor_low_temp_adjust(struct monitor_dev_info *info)
 {
-	struct monitor_dev_info *info = NULL, *tmp;
-
-	list_for_each_entry(tmp, &monitor_dev_list, node) {
-		if (tmp->devp->type != MONITOR_TYPE_CPU)
-			continue;
-		if (cpumask_test_cpu(cpu, &tmp->devp->allowed_cpus)) {
-			info = tmp;
-			break;
-		}
-	}
-
 	if (!info || !info->is_low_temp_enabled)
 		return 0;
 
@@ -1115,6 +1104,24 @@ int rockchip_monitor_suspend_low_temp_adjust(int cpu)
 
 	return 0;
 }
+
+int rockchip_monitor_suspend_low_temp_adjust(int cpu)
+{
+	struct monitor_dev_info *info = NULL, *tmp;
+
+	down_read(&mdev_list_sem);
+	list_for_each_entry(tmp, &monitor_dev_list, node) {
+		if (tmp->devp->type != MONITOR_TYPE_CPU)
+			continue;
+		if (cpumask_test_cpu(cpu, &tmp->devp->allowed_cpus)) {
+			info = tmp;
+			break;
+		}
+	}
+	up_read(&mdev_list_sem);
+
+	return rockchip_monitor_low_temp_adjust(info);
+}
 EXPORT_SYMBOL(rockchip_monitor_suspend_low_temp_adjust);
 
 static int
@@ -1498,6 +1505,30 @@ out:
 	return 0;
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static void rockchip_system_monitor_first_cpu_online(struct cpumask *online_cpus)
+{
+	struct monitor_dev_info *tmp;
+	struct cpumask tmp_mask;
+
+	down_read(&mdev_list_sem);
+	list_for_each_entry(tmp, &monitor_dev_list, node) {
+		if (tmp->devp->type != MONITOR_TYPE_CPU)
+			continue;
+		/* Check if all allowed cpus of the cluster are offline */
+		cpumask_and(&tmp_mask, &tmp->devp->allowed_cpus, cpu_online_mask);
+		if (!cpumask_empty(&tmp_mask))
+			continue;
+		/* Check if the online cpus contain one allowed cpu of the cluster */
+		cpumask_and(&tmp_mask, &tmp->devp->allowed_cpus, online_cpus);
+		if (cpumask_empty(&tmp_mask))
+			continue;
+		rockchip_monitor_low_temp_adjust(tmp);
+	}
+	up_read(&mdev_list_sem);
+}
+#endif
+
 static void rockchip_system_monitor_cpu_on_off(void)
 {
 #ifdef CONFIG_HOTPLUG_CPU
@@ -1528,6 +1559,7 @@ static void rockchip_system_monitor_cpu_on_off(void)
 	cpumask_xor(&online_cpus, cpu_online_mask, &online_cpus);
 	if (cpumask_empty(&online_cpus))
 		goto out;
+	rockchip_system_monitor_first_cpu_online(&online_cpus);
 	for_each_cpu(cpu, &online_cpus)
 		add_cpu(cpu);
 
@@ -1679,6 +1711,7 @@ static int rockchip_system_monitor_set_cpu_uevent_suppress(bool is_suppress)
 	struct monitor_dev_info *info;
 	struct cpufreq_policy *policy;
 
+	down_read(&mdev_list_sem);
 	list_for_each_entry(info, &monitor_dev_list, node) {
 		if (info->devp->type != MONITOR_TYPE_CPU)
 			continue;
@@ -1690,6 +1723,7 @@ static int rockchip_system_monitor_set_cpu_uevent_suppress(bool is_suppress)
 		else
 			dev_set_uevent_suppress(&policy->cdev->device, 0);
 	}
+	up_read(&mdev_list_sem);
 
 	return 0;
 }

drivers/usb/dwc2/hcd.c

@@ -4447,20 +4447,19 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd)
 	if (hsotg->lx_state != DWC2_L2)
 		goto unlock;
 
-	hprt0 = dwc2_read_hprt0(hsotg);
-
-	/*
-	 * Added port connection status checking which prevents exiting from
-	 * Partial Power Down mode from _dwc2_hcd_resume() if not in Partial
-	 * Power Down mode.
-	 */
-	if (hprt0 & HPRT0_CONNSTS) {
-		hsotg->lx_state = DWC2_L0;
-		goto unlock;
-	}
-
 	switch (hsotg->params.power_down) {
 	case DWC2_POWER_DOWN_PARAM_PARTIAL:
+		hprt0 = dwc2_read_hprt0(hsotg);
+		/*
+		 * Added port connection status checking which prevents exiting from
+		 * Partial Power Down mode from _dwc2_hcd_resume() if not in Partial
+		 * Power Down mode.
+		 */
+		if (hprt0 & HPRT0_CONNSTS) {
+			hsotg->lx_state = DWC2_L0;
+			goto unlock;
+		}
+
 		ret = dwc2_exit_partial_power_down(hsotg, 0, true);
 		if (ret)
 			dev_err(hsotg->dev,

sound/soc/rockchip/rockchip_asrc.c

@@ -1269,7 +1269,7 @@ static struct clk *rockchip_asrc_get_clk_parent(struct clk *clk, char *clk_names
 
 	name_len = strlen(name);
 	if ((name_len > 1) && (name[name_len - 1] == '0') &&
-	    (name[name_len - 2] < '0' && name[name_len - 2] > '9')) {
+	    (name[name_len - 2] < '0' || name[name_len - 2] > '9')) {
 		name_temp = kstrdup(name, GFP_KERNEL);
 		if (!name_temp)
 			return ERR_PTR(-ENOMEM);