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arm64: dts: rockchip: rk3588: add cacheinfo

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little cpu:
console:/ # ls /sys/devices/system/cpu/cpu0/cache/
index0  index1  index2  index3  uevent
console:/ # ls /sys/devices/system/cpu/cpu0/cache/index0/
coherency_line_size  shared_cpu_list  type
level                shared_cpu_map   uevent
number_of_sets       size             ways_of_associativity
console:/ # cat /sys/devices/system/cpu/cpu0/cache/index*/{level,size,type}
1
1
2
3
32K
32K
128K
3072K
Data
Instruction
Unified
Unified

big cpu:
console:/ # cat /sys/devices/system/cpu/cpu4/cache/index*/{level,size,type}
1
1
2
3
64K
64K
512K
3072K
Data
Instruction
Unified
Unified

Change-Id: I59158db95b4f8345805db05e4cce2e97dc73e724
Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
2022-01-10 20:14:35 +08:00
committed by Tao Huang
parent 8e6b342cd5
commit da7abc05ea
1 changed files with 127 additions and 0 deletions
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127
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -323,6 +323,13 @@
clocks = <&scmi_clk SCMI_CLK_CPUL>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l0>;
};
cpu_l1: cpu@100 {
@@ -334,6 +341,13 @@
clocks = <&scmi_clk SCMI_CLK_CPUL>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l1>;
};
cpu_l2: cpu@200 {
@@ -345,6 +359,13 @@
clocks = <&scmi_clk SCMI_CLK_CPUL>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l2>;
};
cpu_l3: cpu@300 {
@@ -356,6 +377,13 @@
clocks = <&scmi_clk SCMI_CLK_CPUL>;
operating-points-v2 = <&cluster0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
d-cache-size = <32768>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
next-level-cache = <&l2_cache_l3>;
};
cpu_b0: cpu@400 {
@@ -367,6 +395,13 @@
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_b0>;
};
cpu_b1: cpu@500 {
@@ -378,6 +413,13 @@
clocks = <&scmi_clk SCMI_CLK_CPUB01>;
operating-points-v2 = <&cluster1_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_b1>;
};
cpu_b2: cpu@600 {
@@ -389,6 +431,13 @@
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
operating-points-v2 = <&cluster2_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_b2>;
};
cpu_b3: cpu@700 {
@@ -400,6 +449,13 @@
clocks = <&scmi_clk SCMI_CLK_CPUB23>;
operating-points-v2 = <&cluster2_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <65536>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <65536>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2_cache_b3>;
};
idle-states {
@@ -413,6 +469,77 @@
min-residency-us = <1000>;
};
};
l2_cache_l0: l2-cache-l0 {
compatible = "cache";
cache-size = <131072>;
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_cache>;
};
l2_cache_l1: l2-cache-l1 {
compatible = "cache";
cache-size = <131072>;
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_cache>;
};
l2_cache_l2: l2-cache-l2 {
compatible = "cache";
cache-size = <131072>;
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_cache>;
};
l2_cache_l3: l2-cache-l3 {
compatible = "cache";
cache-size = <131072>;
cache-line-size = <64>;
cache-sets = <512>;
next-level-cache = <&l3_cache>;
};
l2_cache_b0: l2-cache-b0 {
compatible = "cache";
cache-size = <524288>;
cache-line-size = <64>;
cache-sets = <1024>;
next-level-cache = <&l3_cache>;
};
l2_cache_b1: l2-cache-b1 {
compatible = "cache";
cache-size = <524288>;
cache-line-size = <64>;
cache-sets = <1024>;
next-level-cache = <&l3_cache>;
};
l2_cache_b2: l2-cache-b2 {
compatible = "cache";
cache-size = <524288>;
cache-line-size = <64>;
cache-sets = <1024>;
next-level-cache = <&l3_cache>;
};
l2_cache_b3: l2-cache-b3 {
compatible = "cache";
cache-size = <524288>;
cache-line-size = <64>;
cache-sets = <1024>;
next-level-cache = <&l3_cache>;
};
l3_cache: l3-cache {
compatible = "cache";
cache-size = <3145728>;
cache-line-size = <64>;
cache-sets = <4096>;
};
};
cluster0_opp_table: cluster0-opp-table {