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ASoC: codecs: remove unused codecs

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Change-Id: I8ed1e51666c767c8698d6d0a8f647ee64cfa5a02
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This commit is contained in:
Sugar Zhang
2019-11-19 14:45:04 +08:00
committed by Tao Huang
parent 5a7879bb74
commit daf07e4866
41 changed files with 0 additions and 35140 deletions
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467
sound/soc/codecs/ak4396.c
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@@ -1,467 +0,0 @@
/*
* AK4396 ALSA SoC (ASoC) driver
*
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <linux/spi/spi.h>
#include <sound/asoundef.h>
#include <linux/delay.h>
/* AK4396 registers addresses */
#define AK4396_REG_CONTROL1 0x00
#define AK4396_REG_CONTROL2 0x01
#define AK4396_REG_CONTROL3 0x02
#define AK4396_REG_LCH_ATT 0x03
#define AK4396_REG_RCH_ATT 0x04
#define AK4396_NUM_REGS 5
#define AK4396_REG_MASK 0x1f
#define AK4396_WRITE 0x20 /*C1 C0 R/W A4 A3 A2 A1 A0 8bit==0010 0000 */
/* Bit masks for AK4396 registers */
#define AK4396_CONTROL1_RSTN (1 << 0)
#define AK4396_CONTROL1_DIF0 (1 << 1)
#define AK4396_CONTROL1_DIF1 (1 << 2)
#define AK4396_CONTROL1_DIF2 (1 << 3)
#define DRV_NAME "AK4396"
struct ak4396_private {
enum snd_soc_control_type control_type;
void *control_data;
unsigned int sysclk;
};
#if 0
static const u16 ak4396_reg[AK4396_NUM_REGS] = {
0x87, 0x02, 0x00, 0xff, 0xff
}; //CONFIG_LINF
#else
static const u16 ak4396_reg[AK4396_NUM_REGS] = {
0x05, 0x02, 0x00, 0xff, 0xff
}; //CONFIG_LINF
#endif
static void on_off_ext_amp(int i)
{
#ifdef SPK_CTL
//gpio_direction_output(SPK_CTL, GPIO_LOW);
gpio_set_value(SPK_CTL, i);
printk("*** %s() SPEAKER set as %d\n", __FUNCTION__, i);
#endif
#ifdef EAR_CON_PIN
//gpio_direction_output(EAR_CON_PIN, GPIO_LOW);
gpio_set_value(EAR_CON_PIN, i);
printk("*** %s() HEADPHONE set as %d\n", __FUNCTION__, i);
mdelay(50);
#endif
}
static int ak4396_fill_cache(struct snd_soc_codec *codec)
{
int i;
u8 *reg_cache = codec->reg_cache;
struct spi_device *spi = codec->control_data;
for (i = 0; i < codec->driver->reg_cache_size; i++) {
int ret = spi_w8r8(spi, i);
if (ret < 0) {
dev_err(&spi->dev, "SPI write failure\n");
return ret;
}
reg_cache[i] = ret;
}
return 0;
}
/* read the reg_cache */
static unsigned int ak4396_read_reg_cache(struct snd_soc_codec *codec,
unsigned int reg)
{
u8 *reg_cache = codec->reg_cache;
if (reg >= codec->driver->reg_cache_size)
return -EINVAL;
// printk("read reg_cache[%x]====%d\n", reg, reg_cache[reg]);
return reg_cache[reg];
}
static int ak4396_spi_write(struct snd_soc_codec *codec, unsigned int reg,
unsigned int value)
{
u8 *cache = codec->reg_cache;
struct spi_device *spi = codec->control_data;
if (reg >= codec->driver->reg_cache_size)
return -EINVAL;
/* only write to the hardware if value has changed */
//if (cache[reg] != value)
//{
u8 tmp[2] = { (reg & AK4396_REG_MASK) | AK4396_WRITE, value};
//printk("tmp[0]===%d\n", tmp[0]);
//printk("tmp[1]===%d\n", tmp[1]);
if (spi_write(spi, tmp, sizeof(tmp))) {
dev_err(&spi->dev, "SPI write failed\n");
return -EIO;
}
cache[reg] = value;
//}
return 0;
}
/* write the register space */
static ak4396_write(struct snd_soc_codec *codec)
{
int ret, val, i;
val = 0;
int addr[5] = {0x00, 0x01, 0x02, 0x03, 0x04};
int dat[5] = {0x87, 0x02, 0x00, 0xff, 0xff};
// while(1){
val |= AK4396_CONTROL1_RSTN;
ak4396_spi_write(codec, AK4396_REG_CONTROL1, val);
for(i=0; i<5; i++)
{
ret = ak4396_spi_write(codec, addr[i], dat[i]);
if (ret < 0)
printk("ak4396_spi_write failed!\n");
printk("write %d time(s)\n", i);
}
// }
}
/*
* Note that this should be called from init rather than from hw_params.
*/
static int ak4396_set_dai_sysclk(struct snd_soc_dai *codec_dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct ak4396_private *ak4396 = snd_soc_codec_get_drvdata(codec);
printk("Enter::%s----%d\n",__FUNCTION__,__LINE__);
printk("freq======%d\n", freq);
ak4396->sysclk = freq;
return 0;
}
static int ak4396_set_dai_fmt(struct snd_soc_dai *codec_dai,
unsigned int format)
{
struct snd_soc_codec *codec = codec_dai->codec;
int val = 0;
printk("%s----%d, format[%02x]\n",__FUNCTION__,__LINE__,format);
val = ak4396_read_reg_cache(codec, AK4396_REG_CONTROL1);
if (val < 0)
return val;
val &= ~(AK4396_CONTROL1_DIF0 | AK4396_CONTROL1_DIF1 | AK4396_CONTROL1_DIF2);
// printk("ak4396 val=%d\n", val);
/* set DAI format */
switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_RIGHT_J:
val |= AK4396_CONTROL1_DIF2 ;
printk("SND_SOC_DAIFMT_RIGHT_J: \n");
break;
case SND_SOC_DAIFMT_LEFT_J:
val |= AK4396_CONTROL1_DIF1 ;
printk("SND_SOC_DAIFMT_LEFT_J: \n");
break;
case SND_SOC_DAIFMT_I2S:
val |= AK4396_CONTROL1_DIF0 | AK4396_CONTROL1_DIF1 ;
//val |= 0x87;
printk("SND_SOC_DAIFMT_I2S is ok!\n");
break;
default:
dev_err(codec->dev, "invalid dai format\n");
return -EINVAL;
}
/* This device can only be slave */
if ((format & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
{
printk("%s failed!----%d\n",__FUNCTION__,__LINE__);
return -EINVAL;
}
//val |= AK4396_CONTROL1_RSTN;
printk("AK4396 CONTROL1 val ==== %d\n", val);
ak4396_spi_write(codec, AK4396_REG_CONTROL1, val);
return 0;
}
static int ak4396_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_codec *codec = rtd->codec;
int val = 0;
switch (params_rate(params)) {
case 176400:
val |= IEC958_AES3_CON_FS_176400;
printk("params_rate::=176400!\n");
break;
case 192000:
val |= IEC958_AES3_CON_FS_192000;
printk("params_rate::=192000!\n");
break;
case 88200:
val |= IEC958_AES3_CON_FS_88200;
printk("params_rate::=88200!\n");
break;
case 96000:
val |= IEC958_AES3_CON_FS_96000;
printk("params_rate::=96000!\n");
break;
case 44100:
val |= IEC958_AES3_CON_FS_44100;
printk("params_rate::=44100!\n");
break;
case 48000:
val |= IEC958_AES3_CON_FS_48000;
break;
case 32000:
val |= IEC958_AES3_CON_FS_32000;
break;
default:
dev_err(codec->dev, "unsupported sampling rate\n");
return -EINVAL;
}
val = 0;
val = ak4396_read_reg_cache(codec, AK4396_REG_CONTROL1);
//reset RSTN bit;
val &= 0xFE;
printk("val ==== %d\n", val);
ak4396_spi_write(codec, AK4396_REG_CONTROL1, val);
val |= 0x01;
printk("val ==== %d\n", val);
ak4396_spi_write(codec, AK4396_REG_CONTROL1, val);
//printk("val === %d\n", val);
//ak4396_spi_write(codec, AK4396_REG_CONTROL2, val);
return 0;
}
static struct snd_soc_dai_ops ak4396_dai_ops = {
.hw_params = ak4396_hw_params,
.set_fmt = ak4396_set_dai_fmt,
.set_sysclk = ak4396_set_dai_sysclk,
};
static struct snd_soc_dai_driver ak4396_dai = {
.name = "AK4396 HiFi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE |
SNDRV_PCM_FMTBIT_S24_3LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S32_LE
},
.ops = &ak4396_dai_ops,
};
struct snd_soc_codec *codec_temp;
static int ak4396_probe(struct snd_soc_codec *codec)
{
struct ak4396_private *ak4396 = snd_soc_codec_get_drvdata(codec);
int ret;
printk("ak4396_probe begin!\n");
codec->control_data = ak4396->control_data;
codec_temp = codec;
#if 0
/* read all regs and fill the cache */
ret = ak4396_fill_cache(codec);
if (ret < 0) {
dev_err(codec->dev, "failed to fill register cache\n");
return ret;
}
#endif
/* write to ak4396_reg */
// ak4396_write(codec);
printk("ak4396_probe is ok!\n");
dev_info(codec->dev, "SPI device initialized\n");
return 0;
}
static int ak4396_remove(struct snd_soc_codec *codec)
{
int val, ret;
val = ak4396_read_reg_cache(codec, AK4396_REG_CONTROL1);
if (val < 0)
return val;
/* set non-reset bits */
val &= ~AK4396_CONTROL1_RSTN;
ret = ak4396_spi_write(codec, AK4396_REG_CONTROL1, val);
return ret;
}
static int ak4396_suspend(struct snd_soc_codec *codec)
{
return 0;
}
static int ak4396_resume(struct snd_soc_codec *codec)
{
//ak4396_write(codec);
return 0;
}
static struct snd_soc_codec_driver soc_codec_device_ak4396 = {
.probe = ak4396_probe,
.remove = ak4396_remove,
.suspend = ak4396_suspend,
.resume = ak4396_resume,
.reg_cache_size = AK4396_NUM_REGS,
.reg_word_size = sizeof(u16),
.reg_cache_default = ak4396_reg,
};
static struct class *cls = NULL;
static ssize_t store_ak4396_reg(struct class *dev,
struct class_attribute *attr, const char *buf, size_t count)
{
int reg, value, ret;
// char buf[10] = "123 11";
char *start = buf;
printk("%s, the first dat is reg, the second dat is data, data type is dex\n", __FUNCTION__);
while (*start == ' ')
start++;
reg = simple_strtoull(start, &start, 16);
while (*start == ' ')
start++;
value = simple_strtoull(start, &start, 16);
ret = ak4396_spi_write(codec_temp, reg, value);
if (ret < 0)
printk("ak4396_spi_write failed!\n");
printk("reg = %d, value =%d\n", reg, value);
// return 0;
}
static struct class_attribute attr[] = {
__ATTR(write_reg, 0644, NULL, store_ak4396_reg),
__ATTR_NULL,
};
static int ak4396_spi_probe(struct spi_device *spi)
{
struct ak4396_private *ak4396;
int ret;
printk("ak4396_spi_probe begin!\n");
#if 0 //defined(CONFIG_ARCH_RK3188)
iomux_set(SPI1_CS0);
iomux_set(SPI1_CLK);
iomux_set(SPI1_TXD);
printk("iomux_set is OK!!!\n");
#endif
spi->bits_per_word = 8;
spi->mode = SPI_MODE_0;
ret = spi_setup(spi);
if (ret < 0)
return ret;
ak4396 = kzalloc(sizeof(struct ak4396_private), GFP_KERNEL);
if (ak4396 == NULL)
return -ENOMEM;
ak4396->control_data = spi;
ak4396->control_type = SND_SOC_SPI;
spi_set_drvdata(spi, ak4396);
cls = class_create(THIS_MODULE, DRV_NAME);
if (IS_ERR(cls))
{
printk("class_create failed!\n");
}
ret = class_create_file(cls, attr);
if (ret < 0)
{
printk("class_create_file failed!\n");
}
ret = snd_soc_register_codec(&spi->dev,
&soc_codec_device_ak4396, &ak4396_dai, 1);
if (ret < 0)
kfree(ak4396);
printk("ak4396_spi_probe successful!\n");
return ret;
}
static int ak4396_spi_remove(struct spi_device *spi)
{
snd_soc_unregister_codec(&spi->dev);
kfree(spi_get_drvdata(spi));
return 0;
}
static struct spi_driver ak4396_spi_driver = {
.driver = {
.name = DRV_NAME,
.owner = THIS_MODULE,
},
.probe = ak4396_spi_probe,
.remove = ak4396_spi_remove,
};
static int __init ak4396_init(void)
{
printk("%s\n", __FUNCTION__);
return spi_register_driver(&ak4396_spi_driver);
}
module_init(ak4396_init);
static void __exit ak4396_exit(void)
{
spi_unregister_driver(&ak4396_spi_driver);
}
module_exit(ak4396_exit);
MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
MODULE_DESCRIPTION("Asahi Kasei AK4396 ALSA SoC driver");
MODULE_LICENSE("GPL");

415
sound/soc/codecs/cx2070x-i2c.h
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@@ -1,415 +0,0 @@
/*
* Cx2070x ASoc codec driver.
*
* Copyright: (C) 2010/2011 Conexant Systems
*
* Based on sound/soc/codecs/tlv320aic2x.c by Vladimir Barinov
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* The software is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along with
* this software. If not, see <http//www.gnu.org/licenses/>
*
* All copies of the software must include all unaltered copyright notices,
* disclaimers of warranty, all notices that refer to the General Public License
* and the absence of any warranty.
*
* History
* Added support for CX2070x codec [www.conexant.com]
*/
// force to enable TX/RX on 2nd PCM interface.
#ifndef _PASS1_COMPLETE_
# ifdef CONFIG_SND_DIGICOLOR_SOC_CHANNEL_VER_3_13F
# endif
# ifdef CONFIG_SND_DIGICOLOR_SOC_CHANNEL_VER_4_30F
# endif
#endif
__REG(PLAYBACK_REGISTER, 0xffff, 0xffff, 0x00, 0, DM, B)
__REG(CAPTURE_REGISTER, 0xffff, 0xffff, 0x00, 0, DM, B)
__REG(MICBIAS_REGISTER, 0xffff, 0xffff, 0x00, 0, DM, B)
/////////////////////////////////////////////////////////////////////////
// General codec operations registers
/////////////////////////////////////////////////////////////////////////
// id addr data bias type
__REG(ABORT_CODE, 0x1000, 0x1000, 0x00, 0, RO,B)
__REG(FIRMWARE_VERSION, 0x1001, 0x1001, 0x00, 0, RO,W)
__REG(PATCH_VERSION, 0x1003, 0x1003, 0x00, 0, RO,W)
__REG(CHIP_VERSION, 0x1005, 0x1005, 0x00, 0, RO,B)
__REG(RELEASE_TYPE, 0x1006, 0x1006, 0x00, 0, RO,B)
__REG(USB_LOCAL_VOLUME, 0x004E, 0x004E, 0x42, 0, RW,B)
__REG(ROM_PATCH_VER_HB, 0x1584, 0xFFFF, 0x00, 0, RO,B)
__REG(ROM_PATCH_VER_MB, 0x1585, 0xFFFF, 0x00, 0, RO,B)
__REG(ROM_PATCH_VER_LB, 0x1586, 0xFFFF, 0x00, 0, RO,B)
__REG(DAC1_GAIN_LEFT, 0x100D, 0x100D, 0x00, 0x00, RW,B)
__REG(DAC2_GAIN_RIGHT, 0x100E, 0x100E, 0x00, 0x00, RW,B)
__REG(DSP_MAX_VOLUME, 0x100F, 0x100F, 0x00, 0, RW,B)
__REG(CLASS_D_GAIN, 0x1011, 0x1010, b_00000000, 0, RW,B)
#ifndef _PASS1_COMPLETE_
#define CLASS_D_GAIN_2W8 b_00000000 // 2.8W
#define CLASS_D_GAIN_2W6 b_00000001 // 2.6W
#define CLASS_D_GAIN_2W5 b_00000010 // 2.5W
#define CLASS_D_GAIN_2W4 b_00000011 // 2.4W
#define CLASS_D_GAIN_2W3 b_00000100 // 2.3W
#define CLASS_D_GAIN_2W2 b_00000101 // 2.2W
#define CLASS_D_GAIN_2W1 b_00000110 // 2.1W
#define CLASS_D_GAIN_2W0 b_00000111 // 2.0W
#define CLASS_D_GAIN_1W3 b_00001000 // 1.3W
#define CLASS_D_GAIN_1W25 b_00001001 // 1.25W
#define CLASS_D_GAIN_1W2 b_00001010 // 1.2W
#define CLASS_D_GAIN_1W15 b_00001011 // 1.15W
#define CLASS_D_GAIN_1W1 b_00001100 // 1.1W
#define CLASS_D_GAIN_1W05 b_00001101 // 1.05W
#define CLASS_D_GAIN_1W0 b_00001110 // 1.0W
#define CLASS_D_GAIN_0W9 b_00001111 // 0.9W
#endif
__REG(DAC3_GAIN_SUB, 0x1012, 0x1011, 0x00, 0x4A, RW,B)
__REG(ADC1_GAIN_LEFT, 0x1013, 0x1012, 0x00, 0x4A, RW,B)
__REG(ADC1_GAIN_RIGHT, 0x1014, 0x1013, 0x00, 0x4A, RW,B)
__REG(ADC2_GAIN_LEFT, 0x1015, 0x1014, 0x00, 0x00, RW,B)
__REG(ADC2_GAIN_RIGHT, 0x1016, 0x1015, 0x00, 0x00, RW,B)
__REG(DSP_MAX_MIC_GAIN, 0x1017, 0x1016, 0x00, 0, RW,B)
__REG(VOLUME_MUTE, 0x1018, 0x1017, 0, 0, WI,B)
#ifndef _PASS1_COMPLETE_
#define LEFT_AUX_MUTE b_01000000
#define RIGH_AUX_MUTE b_00100000
#define LEFT_MIC_MUTE b_00010000
#define RIGH_MIC_MUTE b_00001000
#define SUB_SPEAKER_MUTE b_00000100
#define LEFT_SPEAKER_MUTE b_00000010
#define RIGH_SPEAKER_MUTE b_00000001
#define VOLUME_MUTE_ALL b_01111111
#endif
//since the playback path is determined in register value,we have to enable one port.
__REG(OUTPUT_CONTROL, 0x1019, 0x1018, b_10000000, 0, WC,B) //class -d is selected by default.
#ifndef _PASS1_COMPLETE_
#define OUT_CTRL_AUTO b_10000000 // Automatic FW Control base on Jack Sense and DAC enables, 1= Auto, 0= Manual
#define OUT_CTRL_SUB_DIFF b_01000000 // Sub Differential control, 1=Differential, 0=Single Ended
#define OUT_CTRL_LO_DIFF b_00100000 // Line Out Differential control, 1=Differential, 0=Single Ended
#define OUT_CTRL_CLASSD_OUT b_00010000 // ClassD Output, 1=PWM, 0=Speakers
#define OUT_CTRL_CLASSD_MONO b_00001000 // ClassD Mono, 1=Mono, 0=Stereo
#define OUT_CTRL_CLASSD_EN b_00000100 // If OutCTL[7]=0, 1=Enable ClassD Speakers, 0=Disable ClassD Speakers
#define OUT_CTRL_LO_EN b_00000010 // If OutCTL[7]=0, 1=Enable Line Out, 0=Disable Line Out
#define OUT_CTRL_HP_EN b_00000001 // If OutCTL[7]=0, 1=Enable Headphone, 0=Disable Headphone
#endif
__REG(INPUT_CONTROL, 0x101A, 0x1019, b_10000000, 0, WI,B)
#ifndef _PASS1_COMPLETE_
#define IN_CTRL_AUTO b_10000000 // Automatic FW Control base on Jack Sense and ADC enables, 1=Auto, 0=Manual
#define IN_CTRL_L1_DIFF b_00001000 // Line In 1 Differential control, 1=Differential, 0=Single Ended
#define IN_CTRL_L3_EN b_00000100 // If LineCTL[7]=0, 1=Enable Line In 3, 0=Disable Line In 3
#define IN_CTRL_L2_EN b_00000010 // If LineCTL[7]=0, 1=Enable Line In 2, 0=Disable Line In 2
#define IN_CTRL_L1_EN b_00000001 // If LineCTL[7]=0, 1=Enable Line In 1, 0=Disable Line In 1
#endif
__REG(LINE1_GAIN, 0x101B, 0x101A, b_00000000, 0, RW,B)
#ifndef _PASS1_COMPLETE_
#define LINE1_MUTE b_10000000 // 1=mute, 0=unmute
#define LINE1_GAIN_MASK b_00011111 // range 0x00-0x1F (-35.5dB to +12dB)
#endif
__REG(LINE2_GAIN, 0x101C, 0x101B, b_00000000, 0, RW,B)
#ifndef _PASS1_COMPLETE_
#define LINE2_MUTE b_10000000 // 1=mute, 0=unmute
#define LINE2_GAIN_MASK b_00011111 // range 0x00-0x1F (-35.5dB to +12dB)
#endif
__REG(LINE3_GAIN, 0x101D, 0x101C, b_00000000, 0, RW,B)
#ifndef _PASS1_COMPLETE_
#define LINE3_MUTE b_10000000 // 1=mute, 0=unmute
#define LINE3_GAIN_MASK b_00011111 // range 0x00-0x1F (-35.5dB to +12dB)
#endif
__REG(MIC_CONTROL, 0x101E, 0x101D, b_00000110, 0, WC,B)
#ifndef _PASS1_COMPLETE_
#define MICROPHONE_POWER_ALWAYS b_00010000 // 1 = leave microphone and bias always on to avoid pops (burns power), 0 = microphone powered up as needed, mute for 400ms to remove pops
#define MICROPHONE_BIAS SELECT b_00001000 // 1= 80%, 0= 50%
#define MICROPHONE_BOOST_MASK b_00000111 // 2:0 MicCTL [2:0] Microphone Boost in 6dB Steps, 0= 0dB, 7= +42dB
#endif
#if defined(CONFIG_SND_DIGICOLOR_SOC_CHANNEL_VER_3_13E)
// adc
__REG(STREAM1_MIX, 0xffff, 0x101E, b_00000000, 0, WI,B)
#ifndef _PASS1_COMPLETE_
#define STREAM1_MUTE b_10000000 // 1=mute, 0=unmute
#define STREAM1_GAIN_MASK b_00011111 // range 0x00-0x4A (0dB to -74dB)
#endif
// i2s
__REG(STREAM3_MIX, 0xffff, 0x101F, b_00000000, 0, WI,B)
#ifndef _PASS1_COMPLETE_
#define STREAM3_MUTE b_10000000 // 1=mute, 0=unmute
#define STREAM3_GAIN_MASK b_00011111 // range 0x00-0x4A (0dB to -74dB)
#endif
// usb?
__REG(STREAM4_MIX, 0xffff, 0x1020, b_00000000, 0, WI,B)
#ifndef _PASS1_COMPLETE_
#define STREAM4_MUTE b_10000000 // 1=mute, 0=unmute
#define STREAM4_GAIN_MASK b_00011111 // range 0x00-0x4A (0dB to -74dB)
#endif
#endif
#if defined(CONFIG_SND_DIGICOLOR_SOC_CHANNEL_VER_4_30F)
__REG(MIX0_INPUT0, 0x101F, 0xffff, b_00000000, 0, WI,B) // stream1 out
__REG(MIX0_INPUT1, 0x1020, 0xffff, b_00000000, 0, WI,B) // stream3 out
__REG(MIX0_INPUT2, 0x1021, 0xffff, b_00000000, 0, WI,B) // stream4 out
__REG(MIX0_INPUT3, 0x1022, 0xffff, b_10000000, 0, WI,B) // none
__REG(MIX1_INPUT0, 0x1023, 0xffff, b_10000000, 0, WI,B) // none
__REG(MIX1_INPUT1, 0x1024, 0xffff, b_10000000, 0, WI,B) // none
__REG(MIX1_INPUT2, 0x1025, 0xffff, b_10000000, 0, WI,B) // none
__REG(MIX1_INPUT3, 0x1026, 0xffff, b_10000000, 0, WI,B) // nonw
__REG(MIX0_SOURCE0, 0x1184, 0xffff, b_00000000, 0, WI,B) // stream1 out
__REG(MIX0_SOURCE1, 0x1185, 0xffff, b_00000011, 0, WI,B) // stream3 out
__REG(MIX0_SOURCE2, 0x1186, 0xffff, b_00000100, 0, WI,B) // stream4 out
__REG(MIX0_SOURCE3, 0x1187, 0xffff, b_00000000, 0, WI,B) // none
__REG(MIX1_SOURCE0, 0x1188, 0xffff, b_00000001, 0, WI,B) // none
__REG(MIX1_SOURCE1, 0x1189, 0xffff, b_00000000, 0, WI,B) // none
__REG(MIX1_SOURCE2, 0x118a, 0xffff, b_00000000, 0, WI,B) // none
__REG(MIX1_SOURCE3, 0x118b, 0xffff, b_00000000, 0, WI,B) // none
__REG(VOICE_IN_SOURCE, 0x118c, 0xffff, b_00000010, 0, WI,B) // stream2
//__REG(VOICE_IN_SOURCE, 0x118c, 0xffff, 0x04, 0, WI,B) // stream2
#endif
/////////////////////////////////////////////////////////////////////////
// Hardware registers
/////////////////////////////////////////////////////////////////////////
// id addr data bias type
// __REG(CLOCK_DIVIDER, 0x0F50, 0x0F50, b_00001111, 0, WI,B) // Port1 external clock enabled
__REG(CLOCK_DIVIDER, 0x0F50, 0x0F50, 0xFF, 0, WI,B) // Port1 slave, Port2 Master 2.048 MHz
#ifndef _PASS1_COMPLETE_
#define PORT2_DIV_SEL_6_144MHz b_00000000 // 0x0 = 6.144 MHz
#define PORT2_DIV_SEL_4_096MHz b_00010000 // 0x1 = 4.096 MHz
#define PORT2_DIV_SEL_3_072MHz b_00100000 // 0x2 = 3.072 MHz
#define PORT2_DIV_SEL_2_048MHz b_00110000 // 0x3 = 2.048 MHz
#define PORT2_DIV_SEL_1_536MHz b_01000000 // 0x4 = 1.536 MHz
#define PORT2_DIV_SEL_1_024MHz b_01010000 // 0x5 = 1.024 MHz
#define PORT2_DIV_SEL_768kHz b_01100000 // 0x6 = 768kHz
#define PORT2_DIV_SEL_512kHz b_01110000 // 0x7 = 512 kHz
#define PORT2_DIV_SEL_384kHz b_10000000 // 0x8 = 384 kHz
#define PORT2_DIV_SEL_256kHz b_10010000 // 0x9 = 256 kHz
#define PORT2_DIV_SEL_5_644MHz b_10100000 // 0xa = 5.644 MHz
#define PORT2_DIV_SEL_2_822MHz b_10110000 // 0xb = 2.822 MHz
#define PORT2_DIV_SEL_1_411MHz b_11000000 // 0xc = 1.411 MHz
#define PORT2_DIV_SEL_705kHz b_11010000 // 0xd = 705 kHz
#define PORT2_DIV_SEL_352kHz b_11100000 // 0xe = 352 kHz
#define PORT2_DIV_SEL_EXT b_11110000 // 0xf = external clock enabled
#define PORT1_DIV_SEL_6_144MHz b_00000000 // 0x0 = 6.144 MHz
#define PORT1_DIV_SEL_4_096MHz b_00000001 // 0x1 = 4.096 MHz
#define PORT1_DIV_SEL_3_072MHz b_00000010 // 0x2 = 3.072 MHz
#define PORT1_DIV_SEL_2_048MHz b_00000011 // 0x3 = 2.048 MHz
#define PORT1_DIV_SEL_1_536MHz b_00000100 // 0x4 = 1.536 MHz
#define PORT1_DIV_SEL_1_024MHz b_00000101 // 0x5 = 1.024 MHz
#define PORT1_DIV_SEL_768kHz b_00000110 // 0x6 = 768kHz
#define PORT1_DIV_SEL_512kHz b_00000111 // 0x7 = 512 kHz
#define PORT1_DIV_SEL_384kHz b_00001000 // 0x8 = 384 kHz
#define PORT1_DIV_SEL_256kHz b_00001001 // 0x9 = 256 kHz
#define PORT1_DIV_SEL_5_644MHz b_00001010 // 0xa = 5.644 MHz
#define PORT1_DIV_SEL_2_822MHz b_00001011 // 0xb = 2.822 MHz
#define PORT1_DIV_SEL_1_411MHz b_00001100 // 0xc = 1.411 MHz
#define PORT1_DIV_SEL_705kHz b_00001101 // 0xd = 705 kHz
#define PORT1_DIV_SEL_352kHz b_00001110 // 0xe = 352 kHz
#define PORT1_DIV_SEL_EXT b_00001111 // 0xf = external clock enabled
#endif
__REG(PORT1_CONTROL, 0x0F51, 0x0F51, b_10110000, 0, WI,B)
#ifndef _PASS1_COMPLETE_
#define PORT1_DELAY b_10000000 // 1=Data delayed 1 bit (I2S standard), 0=no delay (sony mode)
#define PORT1_JUSTR_LSBF b_01000000 // [1/0]=Right/Left Justify (I2S) or LSB/MSB First (PCM)
#define PORT1_RX_EN b_00100000 // 1=RX Clock Enable, 0=RX Clock Disabled
#define PORT1_TX_EN b_00010000 // 1=TX Clock Enable, 0=TX Clock Disabled
//#define PORT1_ b_00001000 //
#define PORT1_BITCLK_POL b_00000100 // 0=Normal clock, 1=Inverted clock
#define PORT1_WS_POL b_00000010 // 0=Rising Edge Active for Word Strobe, 1=Falling Edge Active for Word Strobe
#define PORT1_PCM_MODE b_00000001 // 0=I2S mode, 1=PCM Mode
#endif
__REG(PORT1_TX_CLOCKS_PER_FRAME_PHASE,0x0F52, 0x0F52, b_00000011, 0, WI,B) // clocks/frame=(N+1)*8
__REG(PORT1_RX_CLOCKS_PER_FRAME_PHASE,0x0F53, 0x0F53, b_00000011, 0, WI,B) // clocks/frame=(N+1)*8
__REG(PORT1_TX_SYNC_WIDTH, 0x0F54, 0x0F54, b_00001111, 0, WI,B) // clocks=(N+1)
__REG(PORT1_RX_SYNC_WIDTH, 0x0F55, 0x0F55, b_00001111, 0, WI,B) // clocks=(N+1)
__REG(PORT1_CONTROL_2, 0x0F56, 0x0F56, b_00000101, 0, WI,B)
#ifndef _PASS1_COMPLETE_
#define PORT1_CTRL_TX_PT b_00100000 // Tx passthrough mode, 0=off, 1=on
#define PORT1_CTRL_RX_PT b_00010000 // Rx passthrough mode, 0=off, 1=on
#define PORT1_CTRL_RX_SIZE_8 b_00000000 // RX Sample Size, 00=8 bits
#define PORT1_CTRL_RX_SIZE_16 b_00000100 // RX Sample Size, 01=16 bit
#define PORT1_CTRL_RX_SIZE_24T b_00001000 // RX Sample Size, 10=24 bit truncated to 16 bits
#define PORT1_CTRL_RX_SIZE_24 b_00001100 // RX Sample Size, 11=24 bit
#define PORT1_CTRL_TX_SIZE_8 b_00000000 // TX Sample Size, 00=8 bits
#define PORT1_CTRL_TX_SIZE_16 b_00000001 // TX Sample Size, 01=16 bit
#define PORT1_CTRL_TX_SIZE_24T b_00000010 // TX Sample Size, 10=24 bit truncated to 16 bits
#define PORT1_CTRL_TX_SIZE_24 b_00000011 // TX Sample Size, 11=24 bit
#endif
/////////////////////////////////////////////////////////////////////////
// Codec registers, most need NEWC to be set
/////////////////////////////////////////////////////////////////////////
// id addr data bias type
__REG(STREAM2_RATE, 0x116b, 0xffff, 0xa2, 0, WI,B) // Mic
#ifndef _PASS1_COMPLETE_
#define STREAM2_STREAM_MONO_LEFT 0x00 //
#define STREAM2_STREAM_MONO_RIGHT 0x40 //
#define STREAM2_STREAM_STEREO 0x80 //
#define STREAM2_SAMPLE_A_LAW 0x00 // 8-bit A law
#define STREAM2_SAMPLE_U_LAW 0x10 // 8-bit µ law
#define STREAM2_SAMPLE_16_LIN 0x20 // 16 bit linear
#define STREAM2_SAMPLE_24_LIN 0x30 // 24 bit linear
#define STREAM2_RATE_8000 0x00 // 8000 samples/sec
#define STREAM2_RATE_11025 0x01 // 11025 samples/sec
#define STREAM2_RATE_16000 0x02 // 16000 samples/sec
#define STREAM2_RATE_22050 0x03 // 22050 samples/sec
#define STREAM2_RATE_24000 0x04 // 24000 samples/sec
#define STREAM2_RATE_32000 0x05 // 32000 samples/sec
#define STREAM2_RATE_44100 0x06 // 44100 samples/sec
#define STREAM2_RATE_48000 0x07 // 48000 samples/sec
#define STREAM2_RATE_88200 0x08 // 88200 samples/sec
#define STREAM2_RATE_96000 0x09 // 96000 samples/sec
#endif
__REG(STREAM5_RATE, 0x1171, 0x112D, 0x26, 0, WI,B) // Mic -> I2S (5 wire)
#ifndef _PASS1_COMPLETE_
#define STREAM5_SAMPLE_A_LAW 0x00 // 8-bit A law
#define STREAM5_SAMPLE_U_LAW 0x10 // 8-bit µ law
#define STREAM5_SAMPLE_16_LIN 0x20 // 16 bit linear
#define STREAM5_SAMPLE_24_LIN 0x30 // 24 bit linear
#define STREAM5_RATE_8000 0x00 // 8000 samples/sec
#define STREAM5_RATE_11025 0x01 // 11025 samples/sec
#define STREAM5_RATE_16000 0x02 // 16000 samples/sec
#define STREAM5_RATE_22050 0x03 // 22050 samples/sec
#define STREAM5_RATE_24000 0x04 // 24000 samples/sec
#define STREAM5_RATE_32000 0x05 // 32000 samples/sec
#define STREAM5_RATE_44100 0x06 // 44100 samples/sec
#define STREAM5_RATE_48000 0x07 // 48000 samples/sec
#define STREAM5_RATE_88200 0x08 // 88200 samples/sec
#define STREAM5_RATE_96000 0x09 // 96000 samples/sec
#endif
__REG(STREAM3_RATE, 0x116D, 0x112F, 0xA6, 0, WI,B) // 44.1kHz, 16 bit linear
#ifndef _PASS1_COMPLETE_
#define STREAM3_STREAM_MONO_LEFT 0x00 //
#define STREAM3_STREAM_MONO_RIGHT 0x40 //
#define STREAM3_STREAM_STEREO 0x80 //
#define STREAM3_SAMPLE_A_LAW 0x00 // 8-bit A law
#define STREAM3_SAMPLE_U_LAW 0x10 // 8-bit µ law
#define STREAM3_SAMPLE_16_LIN 0x20 // 16 bit linear
#define STREAM3_SAMPLE_24_LIN 0x30 // 24 bit linear
#define STREAM3_RATE_8000 0x00 // 8000 samples/sec
#define STREAM3_RATE_11025 0x01 // 11025 samples/sec
#define STREAM3_RATE_16000 0x02 // 16000 samples/sec
#define STREAM3_RATE_22050 0x03 // 22050 samples/sec
#define STREAM3_RATE_24000 0x04 // 24000 samples/sec
#define STREAM3_RATE_32000 0x05 // 32000 samples/sec
#define STREAM3_RATE_44100 0x06 // 44100 samples/sec
#define STREAM3_RATE_48000 0x07 // 48000 samples/sec
#define STREAM3_RATE_88200 0x08 // 88200 samples/sec
#define STREAM3_RATE_96000 0x09 // 96000 samples/sec
#endif
__REG(STREAM_3_ROUTING, 0x116E, 0x1130, 0x02, 0, WI,B)
#ifndef _PASS1_COMPLETE_
#define STREAM3_ROUTE_SRC_D1 0x00 // Source = Digital Port1
#define STREAM3_ROUTE_SRC_D2 0x10 // Source = Digital Port2
#define STREAM3_ROUTE_DST_D1 0x00 // Destination = Digital Port1
#define STREAM3_ROUTE_DST_D2 0x01 // Destination = Digital Port2
#define STREAM3_ROUTE_DST_DAC 0x02 // Destination = DAC
#define STREAM3_ROUTE_DST_SUB 0x03 // Destination = DAC (sub)
#define STREAM3_ROUTE_DST_SPDIF 0x04 // Destination = SPDIF
#define STREAM3_ROUTE_DST_USB 0x05 // Destination = USB
#endif
__REG(EQ_GAIN, 0x10D7, 0x10D1, 0x1000, 0, WI,W)
__REG(EQS_GAIN, 0x10D9, 0x10D3, 0x1000, 0, WI,W)
// __REG(SPDIF_CODE, 0x1178, 0x1134, 0x00, 0, WI,B)
// __REG(SPDIF_CONTROL, 0x1179, 0x1135, 0x00, 0, WI,B)
__REG(DSP_PROCESSING_ENABLE_1, 0x117A, 0x1136, 0x00, 0, WC,B)
#ifndef _PASS1_COMPLETE_
#define RIGHT_MIKE b_01000000
#define IN_NOISE_REDUCTION b_00100000
#define MIC_AGC b_00010000
#define BEAM_FORMING b_00001000
#define NOICE_REDUCTION b_00000100
#define LEC b_00000010
#define AEC b_00000001
#endif
__REG(DSP_PROCESSING_ENABLE_2, 0x117B, 0x1137, 0x00, 0, WC,B)
#ifndef _PASS1_COMPLETE_
#define DSP_MONO_OUTPUT b_00100000 // 0=Stereo, 1=Mono (L+R)=L (L+R)=R
#define LOUDNESS_ADAPTER b_00010000 // 1=Enable, 0=Disable
#define STAGE_ENHANCER b_00001000 // 1=Enable 3D processing, 0=Disable
#define DYNAMIC_RANGE_COMPRESSION b_00000100 // 1=Enable, 0=Disable
#define SUBWOOFER_CROSSOVER b_00000010 // 1=Enable, 0=Disable
#define EQUALIZER_10_BAND b_00000001 // 1=Enable, 0=Disable
#endif
#if defined(CONFIG_SND_DIGICOLOR_SOC_CHANNEL_VER_4_30F)
__REG(DSP_INIT_H, 0x117C, 0xffff, 0x00, 0, WI,B) // special
__REG(DSP_INIT, 0x117D, 0xffff, 0x00, 0, WC,B) // special
__REG(DSP_POWER, 0x117E, 0xffff, 0xE0, 0, WC,B) // special
#ifndef _PASS1_COMPLETE_
#define DSP_INIT_NEWC b_00000001
#define DSP_INIT_STREAM_OFF b_00000001
#define DSP_INIT_STREAM_3 b_10001001 // enable stream 3 and 7
#define DSP_INIT_STREAM_5 b_00100101 // enable stream 2 and 5
#define DSP_INIT_STREAM_5_3 b_10101101 // enable streams 2,3,5,7
#define DSP_NO_SOURCE b_00000000
#define DSP_ENABLE_STREAM_3 b_00001000
#define DSP_ENABLE_STREAM_4 b_00010000
#define DSP_ENABLE_STREAM_3_4 b_00011000
#endif
#else
__REG(DSP_INIT, 0xffff, 0x1138, 0x00, 0, WI,B) // special
#ifndef _PASS1_COMPLETE_000000000000000000000000
#define DSP_INIT_NEWC b_00000001
#define DSP_INIT_STREAM_OFF b_00000001
#define DSP_INIT_STREAM_3 b_00001001
#define DSP_INIT_STREAM_5 b_00100001
#define DSP_INIT_STREAM_5_3 b_00101001
#endif
#endif
#ifdef CX20709_TRISTATE_EEPROM
__REG(PAD, 0x0004, 0x0004, 0x00, 0, WO,B)
__REG(PBD, 0x0005, 0x0005, 0x00, 0, W0,B)
#endif
// temp code.
// added rerouting render stream to second I2S output ( 16 Kbps/ 16BITS)
__REG(STREAM4_RATE, 0x116F, 0xffff, 0xA7, 0, WI,B) // dsp -> PCM-2 8Kbps output
__REG(STREAM4_ROUTING, 0x1170, 0xffff, 0x12, 0, WI,B)
__REG(STREAM6_RATE, 0x1172, 0xffff, 0x27, 0, WI,B) // dsp -> PCM-2 8Kbps output
__REG(STREAM7_RATE, 0x1173, 0xffff, 0x07, 0, WC,B) // dsp -> I2S-2 (5 wire)
__REG(STREAMOP_ROUTING, 0x1176, 0xffff, 0x60, 0, WC,B) // AEC narrow band. 48 KHz
__REG(STREAM6_ROUTING, 0x1182, 0xffff, 0x06, 0, WI,B)
__REG(STREAM7_SOURCE, 0x117F, 0xffff, 0x05, 0, WI,B) // dsp -> I2S-2 (5 wire)
__REG(STREAM8_SOURCE, 0x1180, 0xffff, 0x05, 0, WC,B)
__REG(STREAM8_RATE, 0x1175, 0xffff, 0x07, 0, WC,B)
__REG(PORT2_CONTROL, 0x0F5E, 0x0F5E, 0XB0, 0, WI,B) // Delay 1 bit, RX/TX en, mode =i2s
__REG(PORT2_CLOCK_PER_FRAME, 0x0F5F, 0x0F5F, 0X07, 0, WI,B) // 64-bits per frame.
__REG(PORT2_SYNC_WIDTH, 0x0F60, 0x0F60, 0X0f, 0, WI,B) // clocks=(N+1)
__REG(PORT2_SAMPLE_WIDTH, 0x0F61, 0x0F61, 0X01, 0, WI,B) // 16 bits.
__REG(PORT2_RX_STREAM1, 0x0F62, 0x0F62, 0X20, 0, WI,B) // RX 1 <- Slot 0
__REG(PORT2_RX_STREAM2, 0x0F63, 0x0F63, 0X24, 0, WI,B) // RX 2 <- Slot 4
__REG(PORT2_TX_STREAM1, 0x0F65, 0x0F65, 0X20, 0, WI,B) // TX 1 -> Slot 0
__REG(PORT2_TX_STREAM2, 0x0F66, 0x0F66, 0X24, 0, WI,B) // TX 2 -> Slot 4
#ifndef _PASS1_COMPLETE_
#define _PASS1_COMPLETE_
#endif

2290
sound/soc/codecs/cx2070x.c
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File diff suppressed because it is too large Load Diff

90
sound/soc/codecs/cx2070x.h
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@@ -1,90 +0,0 @@
/*
* ALSA SoC CX2070X Channel codec driver
*
* Copyright: (C) 2009/2010 Conexant Systems
*
* Based on sound/soc/codecs/tlv320aic2x.c by Vladimir Barinov
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _CX2070X_H
#define _CX2070X_H
#define CONFIG_SND_DIGICOLOR_SOC_CHANNEL_VER_4_30F 1
#ifdef CONFIG_SND_SOC_CNXT_FW_UPDATE
#define CONFIG_SND_CX2070X_LOAD_FW 1
#endif
//#define CONFIG_SND_CX2070X_USE_FW_H 1
//#define CONFIG_CNXT_USING_SPI_BUS 1
#ifdef CONFIG_SND_SOC_CNXT_JACKSENSE
#define CONFIG_SND_CX2070X_GPIO_JACKSENSE 1
#endif
//#define CONFIG_SND_CX2070X_GPIO_RESET 1
#define CONFIG_SND_CXLIFEGUARD 1
//#define CONFIG_CXNT_SOFTWOARE_SIMULATION 1
#define DBG_MONITOR_REG 1
//#define GPIO_HP_JACKSENSE 178 //Tegra 250
//.#define JACK_SENSE_GPIO_PIN 178 // Tegra
//#define CODEC_RESET_GPIO_PIN 184 // Tegra
#define JACK_SENSE_GPIO_PIN 151 //s5pc110 GPH2_5
#define CODEC_RESET_GPIO_PIN 157 //s5pc110 reset pin.
#define FOR_MID 0
#if (defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) ) && !defined(CONFIG_CNXT_USING_SPI_BUS)
#define USING_I2C 1
#endif
#if defined(CONFIG_SPI_MASTER) && defined(CONFIG_CNXT_USING_SPI_BUS)
#define USING_SPI 1
#endif
enum Cx_INPUT_SEL{
Cx_INPUT_SEL_BY_GPIO = 0,
Cx_INPUT_SEL_MIC,
Cx_INPUT_SEL_LINE,
Cx_INPUT_SEL_DPORT2,
};
enum Cx_OUTPUT_SEL{
Cx_OUTPUT_SEL_BY_GPIO = 0,
Cx_OUTPUT_SEL_SPK,
Cx_OUTPUT_SEL_LINE,
Cx_OUTPUT_SEL_HP,
Cx_OUTPUT_SEL_DPORT2,
};
enum {
OFF,
RCV,
SPK_PATH,
HP_PATH,
HP_NO_MIC,
BT,
SPK_HP,
RING_SPK,
RING_HP,
RING_HP_NO_MIC,
RING_SPK_HP,
};
enum {
MIC_OFF,
Main_Mic,
Hands_Free_Mic,
BT_Sco_Mic,
};
#define CX2070X_I2C_DRIVER_NAME "cx2070x-i2c"
#define CX2070X_SPI_DRIVER_NAME "cx2070x-spi"
#define CX2070X_FIRMWARE_FILENAME "cnxt/cx2070x.fw"
#define AUDDRV_VERSION(major0,major1, minor, build ) ((major0)<<24|(major1)<<16| (minor)<<8 |(build))
#endif

266
sound/soc/codecs/cxdebug.c
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@@ -1,266 +0,0 @@
/*
* ALSA SoC CX20709 Channel codec driver
*
* Copyright: (C) 2009/2010 Conexant Systems
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*
*
*************************************************************************
* Modified Date: 12/01/11
* File Version: 2.26.35.11
*************************************************************************
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/module.h> /* Specifically, a module */
#include <linux/fs.h>
#include <asm/uaccess.h> /* for get_user and put_user */
//#include <sound/core.h>
//#include <sound/pcm.h>
//#include <sound/pcm_params.h>
#include <sound/soc.h>
//#include <sound/soc-dapm.h>
#include <linux/gpio.h>
#include <linux/slab.h>
//#define DEBUG 1
#include "cxdebug.h"
#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
#include <linux/i2c.h>
#endif
#if defined(CONFIG_SPI_MASTER)
#include <linux/spi/spi.h>
#endif
/*
*
* Is the device open right now? Used to prevent
* concurent access into the same device
*/
static int Device_Open = 0;
extern int CX_AUDDRV_VERSION;
struct snd_soc_codec *g_codec = NULL;
/*
* This is called whenever a process attempts to open the device file
*/
static int cxdbg_dev_open(struct inode *inode, struct file *file)
{
#ifdef DEBUG
printk(KERN_INFO "cxdbg_dev: device_open(%p)\n", file);
#endif
/*
* We don't want to talk to two processes at the same time
*/
if (Device_Open)
return -EBUSY;
Device_Open++;
/*
* Initialize the message
*/
// try_module_get(THIS_MODULE);
return 0;
}
/*
* This is called whenever a process attempts to open the device file
*/
static int cxdbg_dev_release(struct inode *inode, struct file *file)
{
#ifdef DEBUG
printk(KERN_INFO "cxdbg_dev: device_release(%p)\n", file);
#endif
Device_Open--;
/*
* Initialize the message
*/
return 0;
}
static int codec_reg_write(struct CXDBG_IODATA *reg)
{
int errno = 0;
BUG_ON(!g_codec);
BUG_ON(!g_codec->hw_write);
if(g_codec&& g_codec->hw_write)
{
if( g_codec->hw_write(g_codec,(char*)reg->data,reg->len)
!=reg->len)
{
errno =-EIO;
printk(KERN_ERR "cxdbg_dev: codec_reg_write failed\n");
}
}
else
{
errno = -EBUSY;
printk(KERN_ERR "cxdbg_dev: codec_reg_write failed, device is not ready.\n");
}
return errno;
}
static unsigned int codec_reg_read(struct CXDBG_IODATA *reg)
{
int errno = 0;
unsigned int regaddr;
unsigned int data;
BUG_ON(!g_codec);
BUG_ON(!g_codec->hw_read);
if (reg-> len == 2)
{
regaddr = (((unsigned int)reg->data[0])<<8) + reg->data[1];
}
else if (reg->len == 1)
{
regaddr = (unsigned int)reg->data[0];
}
else
{
printk(KERN_ERR "cxdbg_dev: codec_reg_read failed, invalid parameter.\n");
return -EINVAL;
}
memset(reg,0,sizeof(*reg));
if(g_codec && g_codec->hw_read)
{
data = g_codec->hw_read(g_codec,regaddr);
reg->data[0] = data & 0xFF;
reg->len = 1;
}
else
{
errno = -EBUSY;
printk(KERN_ERR "cxdbg_dev: codec_reg_read failed, device is not ready.\n");
}
return errno;
return 0;
}
long cxdbg_dev_ioctl(struct file * file, unsigned int cmd, unsigned long arg)
{
struct CXDBG_IODATA *reg=NULL ;
int __user *ip = (int __user*) arg;
long err = -1;
#ifdef DEBUG
printk(KERN_INFO "cxdbg_dev: ioctl, cmd=0x%02x, arg=0x%02lx\n", cmd, arg);
#endif
/*
* Switch according to the ioctl called
*/
switch (cmd) {
case CXDBG_IOCTL_REG_SET:
reg = (struct CXDBG_IODATA*) kmalloc(sizeof(*reg),GFP_KERNEL);
err = copy_from_user((char*) reg, (char*)arg,sizeof(*reg));
if(err==0)
{
codec_reg_write(reg);
}
break;
case CXDBG_IOCTL_REG_GET:
reg = (struct CXDBG_IODATA*) kmalloc(sizeof(*reg),GFP_KERNEL);
err =copy_from_user((char*) reg, (char*)arg,sizeof(*reg));
if( err == 0)
{
codec_reg_read(reg);
err = copy_to_user((char*) arg, (char*)reg,sizeof(*reg));
}
break;
case CXDBG_IOCTL_PDRIVER_VERSION:
err = put_user(CX_AUDDRV_VERSION,ip);
break;
default:
err = -EINVAL;
}
if(reg)
{
kfree(reg);
}
return err;
}
#if defined(_MSC_VER)
static const struct file_operations cxdbg_dev_fops =
{
/*.owner = */THIS_MODULE,
/*.llseek*/NULL,
/*.read = */NULL,
/*.write*/ NULL,
/*.aio_read*/ NULL,
/*.aio_write*/NULL,
/*readdir*/NULL,
/*.poll*/NULL,
/*ioctl*/ NULL /*i2cdev_ioctl*/,
/*.unlocked_ioctl*/cxdbg_dev_ioctl,
/*.compat_ioctl*/NULL,
/*.mmap*/NULL,
/*.open*/cxdbg_dev_open,
/*.flush*/NULL,
/*.release*/NULL,
/*.fsync*/NULL,
/*.aio_fsync*/NULL,
/*.fasync*/NULL,
/*.lock*/NULL,
/*.sendpage*/NULL,
};
#else
static const struct file_operations cxdbg_dev_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = cxdbg_dev_ioctl,
.open = cxdbg_dev_open,
.release = cxdbg_dev_release,
};
#endif
/*
* Initialize the module - Register the character device
*/
int cxdbg_dev_init(struct snd_soc_codec *socdev)
{
int err;
printk(KERN_INFO "cxdbg_dev: entries driver\n");
g_codec = socdev;
err = register_chrdev(CXDBG_MAJOR, CXDBG_DEVICE_NAME, &cxdbg_dev_fops);
if (err)
{
printk(KERN_ERR "cxdbg_dev: Driver Initialisation failed\n");
}
return err;
}
void cxdbg_dev_exit(void)
{
unregister_chrdev(CXDBG_MAJOR,CXDBG_DEVICE_NAME);
}
MODULE_AUTHOR("Simon Ho<simon.ho@conexant.com");
MODULE_DESCRIPTION("debug driver");
MODULE_LICENSE("GPL");

46
sound/soc/codecs/cxdebug.h
View File

@@ -1,46 +0,0 @@
/*
* ALSA SoC CX20709 Channel codec driver
*
* Copyright: (C) 2009/2010 Conexant Systems
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*
*
*************************************************************************
* Modified Date: 11/02/11
* File Version: 2.26.35.11
*************************************************************************
*/
#ifndef CXDEBUG_H
#define CXDEBUG_H
#define CXDBG_MAJOR 168 /* Device major number */
/* Use 'k' as magic number */
#define CXDBG_IOC_MAGIC 'S'
#define MAX_DATA_LEN 64
struct CXDBG_IODATA{
unsigned short len;
unsigned char data[MAX_DATA_LEN];
};
#define CXDBG_IOCTL_REG_SET _IOWR(CXDBG_IOC_MAGIC, 1, struct CXDBG_IODATA)
#define CXDBG_IOCTL_REG_GET _IOWR(CXDBG_IOC_MAGIC, 2, struct CXDBG_IODATA)
#define CXDBG_IOCTL_PDRIVER_VERSION _IOR( CXDBG_IOC_MAGIC, 3, int)
#define CXDBG_DEVICE_NAME "cxdbg"
#ifdef __KERNEL__
int cxdbg_dev_init(struct snd_soc_codec * codec);
void cxdbg_dev_exit(void);
#endif
#endif //#ifndef CXDEBUG_H

978
sound/soc/codecs/cxpump.c
View File

@@ -1,978 +0,0 @@
/*
* ALSA SoC CX20709 Channel codec driver
*
* Copyright: (C) 2009/2010 Conexant Systems
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This code is to download the firmware to CX2070x device.
*
*************************************************************************
* Modified Date: 01/24/11
* File Version: 1.0.0.1
*************************************************************************
*/
#if defined(_MSC_VER)
// microsoft windows environment.
#define __BYTE_ORDER __LITTLE_ENDIAN
#define __LITTLE_ENDIAN 1234
#include <stdlib.h> // For _MAX_PATH definition
#include <stdio.h>
#include <string.h>
#define msleep(_x_)
int printk(const char *s, ...);
#define KERN_ERR "<3>"
#elif defined(__KERNEL__)
// linux kernel environment.
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#else
//
// linux user mode environment.
//
#include <stdlib.h> // For _MAX_PATH definition
#include <stdio.h>
#endif
#include "cxpump.h"
#if defined( __BIG_ENDIAN) && !defined(__BYTE_ORDER)
#define __BYTE_ORDER __BIG_ENDIAN
#elif defined( __LITTLE_ENDIAN ) && !defined(__BYTE_ORDER)
#define __BYTE_ORDER __LITTLE_ENDIAN
#endif
#ifndef __BYTE_ORDER
#error __BYTE_ORDER is undefined.
#endif
#define ENABLE_I2C_BURST_MODE
#if defined(_MSC_VER)
#pragma warning(disable:4127 4706 4101) // conditional experssion is constant
typedef enum I2C_STATE{I2C_OK,I2C_ERR,I2C_RETRY} ;
void ShowProgress(int curPos,bool bForceRedraw, I2C_STATE eState, const int MaxPos);
void InitShowProgress(const int MaxPos);
#elif defined(__KERNEL__)
//linux kernel mode
#define ShowProgress(curPos,bForceRedraw,eState, axPos)
#define InitShowProgress(MaxPos)
#else
//linux user mode
#define InitShowProgress(MaxPos)
#define ShowProgress(curPos,bForceRedraw,eState, axPos)
#endif
#ifndef NULL
#define NULL 0
#endif //#ifndef NULL
#define S_DESC "Cnxt Channel Firmware" /*Specify the string that will show on head of rom file*/
#define S_ROM_FILE_NAME "cx2070x.fw" /*Specify the file name of rom file*/
#define CHIP_ADDR 0x14 /*Specify the i2c chip address*/
#define MEMORY_UPDATE_TIMEOUT 300
#define MAX_ROM_SIZE (1024*1024)
//#define DBG_ERROR "ERROR : "
#define DBG_ERROR KERN_ERR
#define LOG( _msg_ ) printk _msg_
//#define LOG( _msg_ ) ;
typedef struct CX_CODEC_ROM_DATA
{
#ifdef USE_TYPE_DEFINE
unsigned long Type;
#endif //#ifdef USE_TYPE_DEFINE
unsigned long Length;
unsigned long Address;
unsigned char data[1];
}CX_CODEC_ROM_DATA;
#define ROM_DATA_TYPE_S37 0xAA55CC01 // S37 format.
#define ROM_DATA_TYPE_CNXT 0xAA55CC04 // Conexant SPI format.
#define ROM_DATA_SEPARATED_LINE 0x23232323 //()()()()
typedef struct CX_CODEC_ROM{
char sDesc[24];
char cOpenBracket;
char sVersion[5];
char cCloseBracket;
char cEOF;
unsigned long FileSize;
unsigned long LoaderAddr;
unsigned long LoaderLen;
unsigned long CtlAddr;
unsigned long CtlLen;
unsigned long SpxAddr;
unsigned long SpxLen;
struct CX_CODEC_ROM_DATA Data[1];
}CX_CODEC_ROM;
typedef struct CX_CODEC_APPENDED_DATA
{
unsigned char Address[2]; // The address of data.
unsigned char padding; // The actual firmware data.
unsigned char data; // The actual firmware data.
}CX_CODEC_APPENDED_DATA;
typedef struct CX_CODEC_ROM_APPENDED{
unsigned long TuningAddr;
unsigned long TuningLen;
CX_CODEC_APPENDED_DATA data[1]; // following by Jira id and time.
}CX_CODEC_ROM_APPENDED;
typedef struct CX_CODEC_ROM_APPENDED_INFO{
char sJIRAID[16];
char sTime[16];
}CX_CODEC_ROM_APPENDED_INFO;
// To convert two digital ASCII into one BYTE.
unsigned char ASCII_2_BYTE( char ah, char al) ;
#define BUF_SIZE 0x1000
#define BIBF(_x_) if(!(_x_)) break;
#define BIF(_x_) if((ErrNo=(_x_)) !=0) break;
#ifndef BIBF
#define BIBF( _x_ ) if(!(_x_)) break;
#endif
enum {
MEM_TYPE_RAM = 1 /* CTL*/,
MEM_TYPE_SPX = 2,
MEM_TYPE_EEPROM = 3,
MEM_TYPE_CPX =0x04,
MEM_TYPE_EEPROM_RESET = 0x8003, //reset after writing.
};
fun_I2cWriteThenRead g_I2cWriteThenReadPtr = NULL;
fun_I2cWrite g_I2cWritePtr = NULL;
unsigned char * g_AllocatedBuffer = NULL;
unsigned char * g_Buffer = NULL;
unsigned long g_cbMaxWriteBufSize = 0;
void * g_pContextI2cWrite = NULL;
void * g_pContextI2cWriteThenRead = NULL;
/*
* The SetupI2cWriteCallback sets the I2cWrite callback function.
*
* PARAMETERS
*
* pCallbackContext [in] - A pointer to a caller-defined structure of data items
* to be passed as the context parameter of the callback
* routine each time it is called.
*
* I2cWritePtr [in] - A pointer to a i2cwirte callback routine, which is to
* write I2C data. The callback routine must conform to
* the following prototype:
*
* int (*fun_I2cWrite)(
* void * pCallbackContext,
* unsigned char ChipAddr,
* unsigned long cbBuf,
* unsigned char* pBuf
* );
*
* The callback routine parameters are as follows:
*
* pCallbackContext [in] - A pointer to a caller-supplied
* context area as specified in the
* CallbackContext parameter of
* SetupI2cWriteCallback.
* ChipAddr [in] - The i2c chip address.
* cbBuf [in] - The size of the input buffer, in bytes.
* pBuf [in] - A pointer to the input buffer that contains
* the data required to perform the operation.
*
*
* cbMaxWriteBuf [in] - Specify the maximux transfer size for a I2c continue
* writing with 'STOP'. This is limited in I2C bus Master
* device. The size can not less then 3 since Channel
* requires 2 address bytes plus a data byte.
*
*
*
* RETURN
*
* None
*
*/
void SetupI2cWriteCallback( void * pCallbackContext,
fun_I2cWrite I2cWritePtr,
unsigned long cbMaxWriteBufSize)
{
g_pContextI2cWrite = pCallbackContext;
g_I2cWritePtr = I2cWritePtr;
g_cbMaxWriteBufSize = cbMaxWriteBufSize;
}
/*
* The SetupI2cWriteThenReadCallback sets the SetupI2cWriteThenRead callback function.
*
* PARAMETERS
*
* pCallbackContext [in] - A pointer to a caller-defined structure of data items
* to be passed as the context parameter of the callback
* routine each time it is called.
*
* I2cWriteThenReadPtr [in] - A pointer to a i2cwirte callback routine, which is to
* write I2C data. The callback routine must conform to
* the following prototype:
*
* int (*fun_I2cWriteThenRead)(
* void * pCallbackContext,
* unsigned char ChipAddr,
* unsigned long cbBuf,
* unsigned char* pBuf
* );
*
* The callback routine parameters are as follows:
*
* pCallbackContext [in] - A pointer to a caller-supplied
* context area as specified in the
* CallbackContext parameter of
* SetupI2cWriteCallback.
* ChipAddr [in] - The i2c chip address.
* cbBuf [in] - The size of the input buffer, in bytes.
* pBuf [in] - A pointer to the input buffer that contains
* the data required to perform the operation.
*
* RETURN
* None
*
*/
void SetupI2cWriteThenReadCallback( void * pCallbackContext,
fun_I2cWriteThenRead I2cWriteThenReadPtr)
{
g_pContextI2cWriteThenRead = pCallbackContext;
g_I2cWriteThenReadPtr = I2cWriteThenReadPtr;
}
void SetupMemoryBuffer(void * pAllocedMemoryBuffer)
{
g_AllocatedBuffer = (unsigned char*)pAllocedMemoryBuffer;
g_Buffer = g_AllocatedBuffer +2;
}
/*
* Convert a 4-byte number from a ByteOrder into another ByteOrder.
*/
unsigned long ByteOrderSwapULONG(unsigned long i)
{
return((i&0xff)<<24)+((i&0xff00)<<8)+((i&0xff0000)>>8)+((i>>24)&0xff);
}
/*
* Convert a 2-byte number from a ByteOrder into another ByteOrder.
*/
unsigned short ByteOrderSwapWORD(unsigned short i)
{
return ((i>>8)&0xff)+((i << 8)&0xff00);
}
/*
* Convert a 4-byte number from generic byte order into Big Endia
*/
unsigned long ToBigEndiaULONG(unsigned long i)
{
#if __BYTE_ORDER == __LITTLE_ENDIAN
return ByteOrderSwapULONG(i);
#else
return i;
#endif
}
/*
* Convert a 2-byte number from generic byte order into Big Endia
*/
unsigned short ToBigEndiaWORD(unsigned short i)
{
#if __BYTE_ORDER == __LITTLE_ENDIAN
return ByteOrderSwapWORD(i);
#else
return i;
#endif
}
/*
* Convert a 4-byte number from Big Endia into generic byte order.
*/
unsigned long FromBigEndiaULONG(unsigned long i)
{
#if __BYTE_ORDER == __LITTLE_ENDIAN
return ByteOrderSwapULONG(i);
#else
return i;
#endif
}
/*
* Convert a 2-byte number from Big Endia into generic byte order.
*/
unsigned short FromBigEndiaWORD(unsigned short i)
{
#if __BYTE_ORDER == __LITTLE_ENDIAN
return ByteOrderSwapWORD(i);
#else
return i;
#endif
}
/*
* To convert two digital ASCII into one BYTE.
*/
unsigned char ASCII_2_BYTE( char ah, char al)
{
unsigned char ret = '\0';
int i =2;
for(;i>0;i--)
{
if( 'a' <= ah && 'f' >= ah)
{
ret += ah - 'a'+10;
}
else if( 'A' <= ah && 'F' >= ah)
{
ret += ah -'A'+10;
}
else if( '0' <= ah && '9' >= ah)
{
ret += ah - '0';
}
else
{
LOG((DBG_ERROR "Invalid txt data.\n"));
// ErrNo = ERRNO_INVALID_DATA;
break;
}
ah =al;
if(i==2)
ret = (unsigned short)ret << 4;
}
return ret;
}
/*
* Read a byte from the specified register address.
*
* PARAMETERS
*
* RegAddr [in] - Specifies the register address.
*
* RETURN
*
* Returns the byte that is read from the specified register address.
*
*/
unsigned char ReadReg(unsigned short RegAddr)
{
unsigned char RegData;
if(!g_I2cWriteThenReadPtr)
{
LOG((DBG_ERROR "i2C function is not set.\n"));
return 0;
}
RegAddr = ToBigEndiaWORD(RegAddr);
g_I2cWriteThenReadPtr(g_pContextI2cWriteThenRead,CHIP_ADDR,
2,(unsigned char*) &RegAddr,1,&RegData);
return RegData;
}
/*
* Write a byte from the specified register address.
*
* PARAMETERS
*
* RegAddr [in] - Specifies the register address.
*
* RETURN
*
* Returns the byte that is read from the specified register address.
*
* REMARK
*
* The g_I2cWriteThenReadPtr must be set before calling this function.
*/
int WriteReg(unsigned short RegAddr, unsigned char RegData)
{
unsigned char WrBuf[3];
if(!g_I2cWritePtr)
{
LOG((DBG_ERROR "i2C function is not set.\n"));
return -ERRNO_I2CFUN_NOT_SET;
}
*((unsigned short*) WrBuf) = ToBigEndiaWORD(RegAddr);
WrBuf[2] = RegData;
g_I2cWritePtr(g_pContextI2cWrite,CHIP_ADDR,sizeof(WrBuf),WrBuf);
return ERRNO_NOERR;
}
/*
* Writes a number of bytes from a buffer to Channel via I2C bus.
*
* PARAMETERS
*
* NumOfBytes [in] - Specifies the number of bytes to be written
* to the memory address.
* pData [in] - Pointer to a buffer from an array of I2C data
* are to be written.
*
* RETURN
*
* If the operation completes successfully, the return value is ERRNO_NOERR.
* Otherwise, return ERRON_* error code.
*/
int ChannelI2cBulkWrite( unsigned long NumOfBytes, unsigned char *pData)
{
int ErrNo = ERRNO_NOERR;
unsigned short CurAddr;
//unsigned char *pDataEnd = pData + NumOfBytes;
unsigned char *pCurData = pData;
unsigned short *pCurAddrByte = NULL;
unsigned long BytesToProcess = 0;
unsigned short backup = 0;
const unsigned long cbAddressBytes = 2;
const unsigned long cbMaxDataLen = g_cbMaxWriteBufSize-cbAddressBytes;
if(!g_I2cWritePtr )
{
LOG((DBG_ERROR "i2C function is not set.\n"));
return -ERRNO_I2CFUN_NOT_SET;
}
//assert(NumOfBytes < 3);
CurAddr = FromBigEndiaWORD( *((unsigned short*)pData));
//skip first 2 bytes data (address).
NumOfBytes -= cbAddressBytes;
pCurData += cbAddressBytes;
for(;NumOfBytes;)
{
BytesToProcess = NumOfBytes > cbMaxDataLen? cbMaxDataLen : NumOfBytes;
NumOfBytes-= BytesToProcess;
// save the pervious 2 bytes for later use.
pCurAddrByte = (unsigned short*) (pCurData -cbAddressBytes);
backup = *pCurAddrByte;
*pCurAddrByte= ToBigEndiaWORD(CurAddr);
BIBF(g_I2cWritePtr(g_pContextI2cWrite,CHIP_ADDR, BytesToProcess + cbAddressBytes,(unsigned char*)pCurAddrByte));
//restore the data
*pCurAddrByte = backup;
pCurData += BytesToProcess;
CurAddr += (unsigned short)BytesToProcess;
}
return ErrNo;
}
/*
* Writes a number of bytes from a buffer to the specified memory address.
*
* PARAMETERS
*
* dwAddr [in] - Specifies the memory address.
* NumOfBytes [in] - Specifies the number of bytes to be written
* to the memory address.
* pData [in] - Pointer to a buffer from an struct of
* CX_CODEC_ROM_DATA is to be written.
* MemType [in] - Specifies the requested memory type, the value must be from
* the following table.
*
* MEM_TYPE_RAM = 1
* MEM_TYPE_SPX = 2
* MEM_TYPE_EEPROM = 3
*
* RETURN
*
* If the operation completes successfully, the return value is ERRNO_NOERR.
* Otherwise, return ERRON_* error code.
*/
int CxWriteMemory(unsigned long dwAddr, unsigned long NumOfBytes, unsigned char * pData, int MemType )
{
int ErrNo = ERRNO_NOERR;
unsigned char Address[4];
unsigned char WrData[8];
unsigned char offset = 0;
const unsigned long MAX_BUF_LEN = 0x100;
unsigned char cr = 0;
int bNeedToContinue = 0;
int i=0;
const unsigned long cbAddressBytes = 2;
unsigned short * pAddressByte;
unsigned char *pEndData = pData + NumOfBytes;
unsigned short RegMemMapAddr = ToBigEndiaWORD(0x300);
unsigned long BytesToProcess = 0;
while(NumOfBytes)
{
BytesToProcess = NumOfBytes <= MAX_BUF_LEN ? NumOfBytes : MAX_BUF_LEN;
NumOfBytes -= BytesToProcess;
pEndData = pData + BytesToProcess;
*((unsigned long*)&Address) = ToBigEndiaULONG(dwAddr);
// dwAddr += offset;
offset = 0;
if( !bNeedToContinue )
{
#ifdef ENABLE_I2C_BURST_MODE
//
// Update the memory target address and buffer length.
//
WrData[0] = 0x02; //update target address Low 0x02FC
WrData[1] = 0xFC;
WrData[2] = Address[3];
WrData[3] = Address[2];
WrData[4] = Address[1];
WrData[5] = (unsigned char)BytesToProcess -1 ; // X bytes - 1
BIBF(g_I2cWritePtr(g_pContextI2cWrite,CHIP_ADDR, 6 , WrData));
#else
//
// Update the memory target address and buffer length.
//
WrData[0] = 0x02; //update target address Low 0x02FC
WrData[1] = 0xFC;
WrData[2] = Address[3];
BIBF(g_I2cWritePtr(g_pContextI2cWrite,CHIP_ADDR, 3 , WrData));
WrData[0] = 0x02; //update target address Middle 0x02FD
WrData[1] = 0xFD;
WrData[2] = Address[2];
BIBF(g_I2cWritePtr(g_pContextI2cWrite,CHIP_ADDR, 3 , WrData));
WrData[0] = 0x02; //update target address High 0x02FE
WrData[1] = 0xFE;
WrData[2] = Address[1];
BIBF(g_I2cWritePtr(g_pContextI2cWrite,CHIP_ADDR, 3 , WrData));
WrData[0] = 0x02; //update Buffer Length. 0x02FF
WrData[1] = 0xFF;
WrData[2] = (unsigned char)BytesToProcess -1 ; // X bytes - 1
BIBF(g_I2cWritePtr(g_pContextI2cWrite,CHIP_ADDR, 3 , WrData));
#endif
}
//
// Update buffer.
//
#ifdef ENABLE_I2C_BURST_MODE
pAddressByte = (unsigned short*) (pData - cbAddressBytes);
memcpy(g_Buffer, pAddressByte, BytesToProcess+cbAddressBytes);
*((unsigned short*)g_Buffer) = RegMemMapAddr;
ChannelI2cBulkWrite(BytesToProcess+cbAddressBytes, (unsigned char*)g_Buffer);
pData = pEndData;
#else
for(offset=0;pData != pEndData;offset++,pData++)
{
WrData[0] = 0x03; //update Buffer [0x0300 - 0x03ff]
WrData[1] = (unsigned char) offset;
WrData[2] = *pData;
BIBF(g_I2cWritePtr(g_pContextI2cWrite,CHIP_ADDR, 3 , WrData));
}
#endif
//
// Commit the changes and start to transfer buffer to memory.
//
if( MemType == MEM_TYPE_RAM)
{
cr = 0x81;
}
else if( MemType == MEM_TYPE_EEPROM)
{
cr = 0x83;
}
else if( MemType == MEM_TYPE_SPX)
{
cr = 0x85;
if( bNeedToContinue )
{
cr |= 0x08;
}
}
WrData[0] = 0x04; // UpdateCtl [0x400]
WrData[1] = 0x00;
WrData[2] = cr; // start to transfer
BIBF(g_I2cWritePtr(g_pContextI2cWrite,CHIP_ADDR, 3 , WrData));
for(i = 0;i<MEMORY_UPDATE_TIMEOUT;i++)
{
// loop until the writing is done.
WrData[0] = ReadReg(0x0400);
if(!( WrData[0] & 0x80 ))
{
//done
break;
}
else
{
//pending
if(MemType== MEM_TYPE_EEPROM)
{
//it needs more time for updating eeprom.
msleep(5); // need more waiting
}
else
{
udelay(1);
}
continue;
}
}
if( i == MEMORY_UPDATE_TIMEOUT)
{
//writing failed.
LOG( (DBG_ERROR "memory update timeout.\n"));
ErrNo = -ERRNO_UPDATE_MEMORY_FAILED;
break;
}
if ( i >= 1)
{
printk( KERN_ERR "write pending loop =%d\n", i);
}
bNeedToContinue = 1;
}while(0);
return ErrNo ;
}
#define WAIT_UNTIL_DEVICE_READY(_x_,_msg_) \
for (timeout=0;timeout<dev_ready_time_out;timeout++) \
{ \
Ready = ReadReg(0x1000); \
if (Ready _x_) break; \
msleep(10); \
}; \
if( timeout == dev_ready_time_out) \
{ \
printk(KERN_ERR _msg_); \
ErrNo = -ERRNO_DEVICE_OUT_OF_CONTROL; \
break; \
}
unsigned int CxGetFirmwarePatchVersion(void)
{
unsigned int FwPatchVersion = 0;
int ErrNo;
if( NULL == g_I2cWriteThenReadPtr||
NULL == g_I2cWritePtr)
{
ErrNo = -ERRNO_I2CFUN_NOT_SET;
LOG( (DBG_ERROR "i2C function is not set.\n"));
return 0;
}
FwPatchVersion = ReadReg(0x1584);
FwPatchVersion <<= 8;
FwPatchVersion |= ReadReg(0x1585);
FwPatchVersion <<= 8;
FwPatchVersion |= ReadReg(0x1586);
return FwPatchVersion;
}
unsigned int CxGetFirmwareVersion(void)
{
unsigned int FwVersion = 0;
int ErrNo;
if( NULL == g_I2cWriteThenReadPtr||
NULL == g_I2cWritePtr)
{
ErrNo = -ERRNO_I2CFUN_NOT_SET;
LOG( (DBG_ERROR "i2C function is not set.\n"));
return 0;
}
FwVersion = ReadReg(0x1002);
FwVersion <<= 8;
FwVersion |= ReadReg(0x1001);
FwVersion <<= 8;
FwVersion |= ReadReg(0x1006);
return FwVersion;
}
// return number, 0= failed. 1 = successful.
int DownloadFW(const unsigned char * const pRomBin)
{
int ErrNo = ERRNO_NOERR;
struct CX_CODEC_ROM *pRom = (struct CX_CODEC_ROM *)pRomBin;
struct CX_CODEC_ROM_DATA *pRomData;
struct CX_CODEC_ROM_DATA *pRomDataEnd;
unsigned char *pData;
unsigned char *pDataEnd;
unsigned long CurAddr = 0;
unsigned long cbDataLen = 0;
unsigned char Ready;
unsigned long curProgress = 0;
unsigned long TotalLen = 0;
unsigned long i = 0;
const unsigned long dev_ready_time_out = 100;
int bIsRomVersion = 0;
const char CHAN_PATH[]="CNXT CHANNEL PATCH";
unsigned long timeout;
unsigned long fwVer;
unsigned long fwPatchVer;
do{
if(pRom == NULL ||g_Buffer == NULL)
{
ErrNo = -ERRNO_INVALID_PARAMETER;
LOG( (DBG_ERROR "Invalid parameter.\n"));
break;
}
if( NULL == g_I2cWriteThenReadPtr||
NULL == g_I2cWritePtr)
{
ErrNo = -ERRNO_I2CFUN_NOT_SET;
LOG( (DBG_ERROR "i2C function is not set.\n"));
break;
}
//check if codec is ROM version
if (0 == memcmp(CHAN_PATH,pRom->sDesc,sizeof(CHAN_PATH)-1)) {
printk(KERN_INFO "[CNXT] sDesc = %s", pRom->sDesc);
bIsRomVersion = 1;
}
if (bIsRomVersion) {
WAIT_UNTIL_DEVICE_READY(== 0X01,"cx2070x: Timed out waiting for codecto be ready!\n");
} else {
//Check if there is a FIRMWARE present. the Channel should get
// a clear reset signal before we download firmware to it.
if( (ReadReg(0x009) & 0x04) == 0) {
LOG((DBG_ERROR "cx2070x: did not get a clear reset..!"));
ErrNo = -ERRNO_DEVICE_NOT_RESET;
break;
}
}
TotalLen = FromBigEndiaULONG(pRom->LoaderLen) + FromBigEndiaULONG(pRom->CtlLen) + FromBigEndiaULONG(pRom->SpxLen);
// InitShowProgress(TotalLen);
//Download the loader.
pRomData = (struct CX_CODEC_ROM_DATA *) ( (char*)pRom + FromBigEndiaULONG(pRom->LoaderAddr));
pRomDataEnd = (struct CX_CODEC_ROM_DATA *) ((char*)pRomData +FromBigEndiaULONG(pRom->LoaderLen));
for( ;pRomData!=pRomDataEnd;)
{
#ifdef ENABLE_I2C_BURST_MODE
pData = &pRomData->data[0];
pDataEnd= pData + FromBigEndiaULONG(pRomData->Length) - sizeof(unsigned long);
memcpy(g_Buffer, pData-2, FromBigEndiaULONG(pRomData->Length) - sizeof(unsigned short));
BIF(ChannelI2cBulkWrite( FromBigEndiaULONG(pRomData->Length) - sizeof(unsigned short), g_Buffer));
curProgress += FromBigEndiaULONG(pRomData->Length) ;
ShowProgress(curProgress,false, I2C_OK,TotalLen);
pRomData = (struct CX_CODEC_ROM_DATA *)pDataEnd;
#else
CurAddr = FromBigEndiaULONG(pRomData->Address);
pData = &pRomData->data[0];
pDataEnd= pData + FromBigEndiaULONG(pRomData->Length) - sizeof(unsigned long);
for( ;pData!=pDataEnd;pData++)
{
*((unsigned short*)writeBuf) = ToBigEndiaWORD((unsigned short)CurAddr);
writeBuf[2]= *pData;
g_I2cWritePtr(g_pContextI2cWrite,CHIP_ADDR,3, writeBuf);
CurAddr++;
}
pRomData = (struct CX_CODEC_ROM_DATA *)pData;
#endif
}
//* check if the device is ready.
if (bIsRomVersion) {
WAIT_UNTIL_DEVICE_READY(== 0X01,"cx2070x: Timed out waiting for cx2070x to be ready after loader downloaded!\n");
} else {
WAIT_UNTIL_DEVICE_READY(!= 0xFF,"cx2070x: Timed out waiting for cx2070x to be ready after loader downloaded!\n");
}
//Download the CTL
pRomData = (struct CX_CODEC_ROM_DATA *) ( (char*)pRom + FromBigEndiaULONG(pRom->CtlAddr ));
pRomDataEnd = (struct CX_CODEC_ROM_DATA *) ((char*)pRomData +FromBigEndiaULONG(pRom->CtlLen));
for( ;pRomData!=pRomDataEnd;)
{
CurAddr = FromBigEndiaULONG(pRomData->Address);
pData = &pRomData->data[0];
cbDataLen = FromBigEndiaULONG(pRomData->Length) ;
BIF(CxWriteMemory(CurAddr,cbDataLen -sizeof(unsigned long)/*subtracts the address bytes*/ , pData, MEM_TYPE_RAM ));
// The next RoMData position = current romData position + cbDataLen + sizeof( data len bytes)
pRomData = (struct CX_CODEC_ROM_DATA *)((char*) pRomData + cbDataLen + sizeof(unsigned long));
curProgress += cbDataLen ;
ShowProgress(curProgress,false, I2C_OK,TotalLen);
}
pRomData = (struct CX_CODEC_ROM_DATA *) ( (char*)pRom + FromBigEndiaULONG(pRom->SpxAddr ));
pRomDataEnd = (struct CX_CODEC_ROM_DATA *) ((char*)pRomData +FromBigEndiaULONG(pRom->SpxLen));
for( ;pRomData!=pRomDataEnd;)
{
CurAddr = FromBigEndiaULONG(pRomData->Address);
pData = &pRomData->data[0];
cbDataLen = FromBigEndiaULONG(pRomData->Length) ;
BIF(CxWriteMemory(CurAddr,cbDataLen -sizeof(unsigned long)/*subtracts the address bytes*/ , pData, MEM_TYPE_SPX ));
// The next RoMData position = current romData position + cbDataLen + sizeof( data len bytes)
pRomData = (struct CX_CODEC_ROM_DATA *)((char*) pRomData + cbDataLen + sizeof(unsigned long));
curProgress += cbDataLen ;
ShowProgress(curProgress,false, I2C_OK,TotalLen);
}
if(ErrNo != 0) break;
ShowProgress(TotalLen,false, I2C_OK,TotalLen);
//
// Reset
//
if(bIsRomVersion)
{
WriteReg(0x1000,0x00);
// msleep(400); //delay 400 ms
}
else
{
WriteReg(0x400,0x40);
msleep(400); //delay 400 ms
}
WAIT_UNTIL_DEVICE_READY(== 0x01,"cx2070x: Timed out waiting for cx2070x to be ready after firmware downloaded!\n");
//check if XPS code is working or not.
WriteReg(0x117d,0x01);
for (timeout=0;timeout<dev_ready_time_out;timeout++)
{
Ready = ReadReg(0x117d);
if (Ready == 0x00) break;
msleep(1);
};
if( timeout == dev_ready_time_out)
{
LOG((DBG_ERROR "cx2070x: DSP lockup! download firmware failed!"));
ErrNo = -ERRNO_DEVICE_DSP_LOCKUP;
break;
}
fwVer = CxGetFirmwareVersion();
if(bIsRomVersion)
{
fwPatchVer = CxGetFirmwarePatchVersion();
printk(KERN_INFO "cx2070x: firmware download successfully! FW: %u,%u,%u, FW Patch: %u,%u,%u\n",
(unsigned char)(fwVer>>16),
(unsigned char)(fwVer>>8),
(unsigned char)fwVer,
(unsigned char)(fwPatchVer>>16),
(unsigned char)(fwPatchVer>>8),
(unsigned char)fwPatchVer);
}
else
{
printk(KERN_INFO "cx2070x: firmware download successfully! FW: %u,%u,%u\n",
(unsigned char)(fwVer>>16),
(unsigned char)(fwVer>>8),
(unsigned char)fwVer);
}
}while(0);
return ErrNo;
}
int ApplyDSPChanges(const unsigned char *const pRom)
{
int ErrNo = ERRNO_NOERR;
struct CX_CODEC_ROM* pNewRom ;
struct CX_CODEC_ROM_APPENDED *pRomAppended;
struct CX_CODEC_ROM_APPENDED_INFO *pInfo;
struct CX_CODEC_APPENDED_DATA *pData;
struct CX_CODEC_APPENDED_DATA *pDataEnd;
unsigned short wRegAddr;
unsigned char NewC;
#define DESC_LEN (16)
char szJira[DESC_LEN+1];
char szDate[DESC_LEN+1];
pNewRom = (struct CX_CODEC_ROM*) pRom;
// check if firmware contains DSP tuning data.
if( (FromBigEndiaULONG(pNewRom->SpxLen) + FromBigEndiaULONG(pNewRom->SpxAddr)) != FromBigEndiaULONG(pNewRom->FileSize) )
{
// has DSP Tuning data.
pRomAppended = (struct CX_CODEC_ROM_APPENDED*)((char*)pNewRom + FromBigEndiaULONG(pNewRom->SpxAddr) + FromBigEndiaULONG(pNewRom->SpxLen));
pInfo = (struct CX_CODEC_ROM_APPENDED_INFO*) ((char*)pNewRom + FromBigEndiaULONG(pRomAppended ->TuningAddr) +
FromBigEndiaULONG(pRomAppended ->TuningLen));
strncpy(szJira,pInfo->sJIRAID,DESC_LEN);
strncpy(szDate,pInfo->sTime,DESC_LEN);
szJira[DESC_LEN]=0;
szDate[DESC_LEN-1]=0; //remove the last lettle $.
printk(KERN_INFO "Applying the DSP tuning changes..Jira: %s Date: %s\n"
,szJira,szDate);
pData = pRomAppended->data;
pDataEnd = (struct CX_CODEC_APPENDED_DATA*)((char*)pData + FromBigEndiaULONG(pRomAppended->TuningLen));
for(;pData != pDataEnd; pData++)
{
wRegAddr = pData->Address[0];
wRegAddr <<=8;
wRegAddr |= pData->Address[1];
WriteReg(wRegAddr,pData->data);
//printk(KERN_INFO "0X%04x=0x%02x\n",wRegAddr,pData->data);
}
// re-set NewC.
NewC = ReadReg(0x117d);
WriteReg(0x117d,NewC|1);
}
return ErrNo;
}

207
sound/soc/codecs/cxpump.h
View File

@@ -1,207 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/****************************************************************************************
*****************************************************************************************
*** ***
*** Copyright (c) 2011 ***
*** ***
*** Conexant Systems, Inc. ***
*** ***
*** All Rights Reserved ***
*** ***
*** CONFIDENTIAL ***
*** ***
*** NO DISSEMINATION OR USE WITHOUT PRIOR WRITTEN PERMISSION ***
*** ***
*****************************************************************************************
**
** File Name:
** pump.c
**
** Abstract:
** This code is to download the firmware to CX20709 device via I2C bus.
**
**
** Product Name:
** Conexant Channel CX20709
**
** Remark:
**
**
**
********************************************************************************
** Revision History
** Date Description Author
** 01/21/11 Created. Simon Ho
** 01/24/11 Speed up the firmware download by sending Simon Ho
** I2C data continually without addressing
********************************************************************************
*****************************************************************************************/
#ifdef __cplusplus
extern "C"{
#endif
typedef int (*fun_I2cWriteThenRead)( void * pCallbackContext,
unsigned char ChipAddr,
unsigned long cbBuf,
unsigned char* pBuf,
unsigned long cbReadBuf,
unsigned char*pReadBuf);
typedef int (*fun_I2cWrite)( void * pCallbackContext,
unsigned char ChipAddr,
unsigned long cbBuf,
unsigned char* pBuf);
/*
* Set the I2cWrite callback function.
*
* PARAMETERS
*
* pCallbackContext [in] - A pointer to a caller-defined structure of data items
* to be passed as the context parameter of the callback
* routine each time it is called.
*
* I2cWritePtr [in] - A pointer to a i2cwirte callback routine, which is to
* write I2C data. The callback routine must conform to
* the following prototype:
*
* int (*fun_I2cWrite)(
* void * pCallbackContext,
* unsigned char ChipAddr,
* unsigned long cbBuf,
* unsigned char* pBuf
* );
*
* The callback routine parameters are as follows:
*
* pCallbackContext [in] - A pointer to a caller-supplied
* context area as specified in the
* CallbackContext parameter of
* SetupI2cWriteCallback.
* ChipAddr [in] - The i2c chip address.
* cbBuf [in] - The size of the input buffer, in bytes.
* pBuf [in] - A pointer to the input buffer that contains
* the data required to perform the operation.
*
*
* cbMaxWriteBufSize [in] - Specify the maximux transfer size for a I2c continue
* writing with 'STOP'. This is limited in I2C bus Master
* device. The size can not less then 3 since Channel
* requires 2 address bytes plus a data byte.
*
*
*
* RETURN
* None
*
*/
void SetupI2cWriteCallback( void * pCallbackContext,
fun_I2cWrite I2cWritePtr,
unsigned long cbMaxWriteBufSize);
/*
* Set the SetupI2cWriteThenRead callback function.
*
* PARAMETERS
*
* pCallbackContext [in] - A pointer to a caller-defined structure of data items
* to be passed as the context parameter of the callback
* routine each time it is called.
*
* I2cWriteThenReadPtr [in] - A pointer to a i2cwirte callback routine, which is to
* write I2C data. The callback routine must conform to
* the following prototype:
*
* int (*fun_I2cWriteThenRead)(
* void * pCallbackContext,
* unsigned char ChipAddr,
* unsigned long cbBuf,
* unsigned char* pBuf
* );
*
* The callback routine parameters are as follows:
*
* pCallbackContext [in] - A pointer to a caller-supplied
* context area as specified in the
* CallbackContext parameter of
* SetupI2cWriteCallback.
* ChipAddr [in] - The i2c chip address.
* cbBuf [in] - The size of the input buffer, in bytes.
* pBuf [in] - A pointer to the input buffer that contains
* the data required to perform the operation.
*
* RETURN
*
* If the operation completes successfully, the return value is ERRNO_NOERR.
* Otherwise, return ERRON_* error code.
*
*/
void SetupI2cWriteThenReadCallback( void * pCallbackContext,
fun_I2cWriteThenRead I2cWriteThenReadPtr);
void SetupMemoryBuffer(void * pAllocedMemoryBuffer);
/*
* Download Firmware to Channel.
*
* PARAMETERS
*
* pRomData [in] - A pointer fo the input buffer that contains rom data.
*
* RETURN
*
* If the operation completes successfully, the return value is ERRNO_NOERR.
* Otherwise, return ERRON_* error code.
*
* REMARKS
*
* You need to set up both I2cWrite and I2cWriteThenRead callback function by calling
* SetupI2cWriteCallback and SetupI2cWriteThenReadCallback before you call this function.
*/
int DownloadFW(const unsigned char *const pRomData);
/*
* Apply the extra DSP changes from FW file.
*
* PARAMETERS
*
* pRomData [in] - A pointer fo the input buffer that contains rom data.
*
* RETURN
*
* If the operation completes successfully, the return value is ERRNO_NOERR.
* Otherwise, return ERRON_* error code.
*
* REMARKS
*
* You need to set up both I2C/SPI Write and I2C/SPI WriteThenRead callback function
* by calling SetupI2cSpiWriteCallback and SetupI2cSpiWriteThenReadCallback before you call
* this function.
*/
int ApplyDSPChanges(const unsigned char *const pRom);
#ifdef __cplusplus
}
#endif
/*Error codes*/
#define ERRNO_NOERR 0
#define ERRNO_SRC_FILE_NOT_EXIST 101
#define ERRNO_WRITE_FILE_FAILED 102
#define ERRNO_INVALID_DATA 103
#define ERRNO_CHECKSUM_FAILED 104
#define ERRNO_FAILED 105
#define ERRNO_INVALID_PARAMETER 106
#define ERRNO_NOMEM 107
#define ERRNO_I2CFUN_NOT_SET 108
#define ERRNO_UPDATE_MEMORY_FAILED 109
#define ERRNO_DEVICE_NOT_RESET 110
#define ERRNO_DEVICE_OUT_OF_CONTROL 111
#define ERRNO_DEVICE_DSP_LOCKUP 112

107
sound/soc/codecs/dw-hdmi-audio.c
View File

@@ -1,107 +0,0 @@
/*
* dw-hdmi-audio.c
*
* DesignerWare ALSA SoC Codec driver for DW HDMI audio.
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.*
*
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <sound/pcm.h>
#include <sound/soc.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/pcm_params.h>
#include "../../../drivers/video/rockchip/hdmi/rockchip-hdmi.h"
static int snd_dw_hdmi_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *codec_dai)
{
return snd_config_hdmi_audio(params);
}
static const struct snd_soc_dapm_widget snd_dw_hdmi_audio_widgets[] = {
SND_SOC_DAPM_OUTPUT("TX"),
};
static const struct snd_soc_dapm_route snd_dw_hdmi_audio_routes[] = {
{ "TX", NULL, "Playback" },
};
static const struct snd_soc_dai_ops dw_hdmi_dai_ops = {
.hw_params = snd_dw_hdmi_dai_hw_params,
};
static struct snd_soc_dai_driver dw_hdmi_audio_dai = {
.name = "dw-hdmi-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &dw_hdmi_dai_ops,
};
static const struct snd_soc_codec_driver dw_hdmi_audio = {
.dapm_widgets = snd_dw_hdmi_audio_widgets,
.num_dapm_widgets = ARRAY_SIZE(snd_dw_hdmi_audio_widgets),
.dapm_routes = snd_dw_hdmi_audio_routes,
.num_dapm_routes = ARRAY_SIZE(snd_dw_hdmi_audio_routes),
};
static int dw_hdmi_audio_probe(struct platform_device *pdev)
{
int ret;
ret = snd_soc_register_codec(&pdev->dev, &dw_hdmi_audio,
&dw_hdmi_audio_dai, 1);
if (ret)
dev_err(&pdev->dev, "register codec failed (%d)\n", ret);
return ret;
}
static int dw_hdmi_audio_remove(struct platform_device *pdev)
{
snd_soc_unregister_codec(&pdev->dev);
return 0;
}
static const struct of_device_id dw_hdmi_audio_ids[] = {
{ .compatible = "dw-hdmi-audio", },
{ }
};
static struct platform_driver dw_hdmi_audio_driver = {
.driver = {
.name = "dw-hdmi-audio",
.of_match_table = of_match_ptr(dw_hdmi_audio_ids),
},
.probe = dw_hdmi_audio_probe,
.remove = dw_hdmi_audio_remove,
};
module_platform_driver(dw_hdmi_audio_driver);
MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
MODULE_DESCRIPTION("DW HDMI Audio ASoC Interface");
MODULE_LICENSE("GPL");

366
sound/soc/codecs/es8323_pcm.c
View File

@@ -1,366 +0,0 @@
/*
* es8323.c -- es8323 ALSA SoC audio driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "es8323.h"
//#define ES8323_PROC
#ifdef ES8323_PROC
#include <linux/proc_fs.h>
#include <linux/seq_file.h>
#include <linux/vmalloc.h>
#endif
#if 1
#define DBG(x...) printk(KERN_INFO x)
#else
#define DBG(x...)
#endif
enum {
OFF,
RCV,
SPK_PATH,
HP_PATH,
HP_NO_MIC,
BT,
};
static struct i2c_client *i2c_client;
int es8323_codec_state = OFF;
static int codec_write(struct i2c_client *client, unsigned int reg,
unsigned int value)
{
u8 data[2];
data[0] = reg;
data[1] = value & 0x00ff;
//printk("%s: reg=0x%x value=0x%x\n",__func__,reg,value);
if (i2c_master_send(client, data, 2) == 2)
return 0;
else
return -EIO;
}
static unsigned int codec_read(struct i2c_client *client,
unsigned int r)
{
struct i2c_msg xfer[2];
u8 reg = r;
u16 data;
int ret;
/* Write register */
xfer[0].addr = client->addr;
xfer[0].flags = 0;
xfer[0].len = 1;
xfer[0].buf = &reg;
xfer[0].scl_rate = 100 * 1000;
/* Read data */
xfer[1].addr = client->addr;
xfer[1].flags = I2C_M_RD;
xfer[1].len = 2;
xfer[1].buf = (u8 *)&data;
xfer[1].scl_rate = 100 * 1000;
ret = i2c_transfer(client->adapter, xfer, 2);
if (ret != 2) {
dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
return 0;
}
//printk("%s: reg=0x%x value=0x%x\n",__func__,reg,(data >> 8) | ((data & 0xff) << 8));
return (data >> 8) | ((data & 0xff) << 8);
}
static int es8323_reg_init(struct i2c_client *client, bool main_mic)
{
if (es8323_codec_state != OFF) {
if (main_mic) {
codec_write(client, 0x0b,0x82); //ADC INPUT=LIN2/RIN2 //82
} else {
codec_write(client, 0x0b,0x02); //ADC INPUT=LIN1/RIN1 //02
}
DBG("es8323_reg_init() change to %s\n",
main_mic ? "main mic" : "headset mic");
return 0;
}
codec_write(client, 0x35, 0xa0);
codec_write(client, 0x36, 0xc8); //for 1.8V VDD
codec_write(client, 0x08, 0x20); //slave 0x00, master 0x80, bclk invert(bit5)
codec_write(client, 0x02, 0xf3);
codec_write(client, 0x2b, 0x80); //use ADC LRCK, slave 0x80, master 0xc0
codec_write(client, 0x00, 0x36); //DACMCLK is the chip master clock source
codec_write(client, 0x01, 0x72); //all normal
codec_write(client, 0x03, 0x00); //all normal
codec_write(client, 0x04, 0x3c); //L/R DAC power up, L/R out1 enable
codec_write(client, 0x05, 0x00); //normal
codec_write(client, 0x06, 0x00); //normal
codec_write(client, 0x07, 0x7c);
codec_write(client, 0x09, 0x88); //MIC GAIN=24dB
codec_write(client, 0x0a, 0xf0); //L-R diff
if (main_mic) {
codec_write(client, 0x0b,0x82); //ADC INPUT=LIN2/RIN2 //82
} else {
codec_write(client, 0x0b,0x02); //ADC INPUT=LIN1/RIN1 //02
}
codec_write(client, 0x0c, 0x23); //ADC PCM(bit0-1), 18bit(bit2-4), 2nd(bit5)
codec_write(client, 0x0d, 0x02);
codec_write(client, 0x0f, 0xf0); //unmute ADC
codec_write(client, 0x10, 0x00);
codec_write(client, 0x11, 0x00);
codec_write(client, 0x12, 0x2a); //ALC off
codec_write(client, 0x13, 0xC0); //ALC
codec_write(client, 0x14, 0x05); //ALC
codec_write(client, 0x15, 0x06); //ALC
codec_write(client, 0x16, 0x50); //ALC
codec_write(client, 0x17, 0x06); //DAC PCM(bit1-2), 16bit(bit3-5), 2nd(bit6), lr swap(bit 7)
codec_write(client, 0x18, 0x02); // MCLK/256
codec_write(client, 0x19, 0x22);
codec_write(client, 0x1a, 0x00); //lout digital
codec_write(client, 0x1b, 0x00); //rout digital
codec_write(client, 0x26, 0x00);
codec_write(client, 0x27, 0xb8); //LD2LO to left mixer
codec_write(client, 0x28, 0x38);
codec_write(client, 0x29, 0x38);
codec_write(client, 0x2a, 0xb8); //RD2RO to right mixer
codec_write(client, 0x30, 0x1e);
codec_write(client, 0x31, 0x1e);
codec_write(client, 0x02, 0x00);
DBG("es8323_reg_init() set codec route with %s\n",
main_mic ? "main mic" : "headset mic");
return 0;
}
static int es8323_reset(struct i2c_client *client)
{
es8323_codec_state = OFF;
codec_write(client, ES8323_CONTROL1, 0x80);
return codec_write(client, ES8323_CONTROL1, 0x00);
}
int set_es8323(int cmd)
{
DBG("%s : set voice_call_path = %d\n", __func__,
cmd);
if (i2c_client == NULL) {
printk("%s : i2c_client is NULL!\n", __func__);
return -EINVAL;
}
switch (cmd) {
case OFF:
es8323_reset(i2c_client);
break;
case HP_PATH:
es8323_reg_init(i2c_client, 0);
break;
case RCV:
case SPK_PATH:
case HP_NO_MIC:
es8323_reg_init(i2c_client, 1);
break;
case BT:
break;
default:
return -EINVAL;
}
es8323_codec_state = cmd;
return 0;
}
EXPORT_SYMBOL(set_es8323);
static const struct i2c_device_id es8323_i2c_id[] = {
{ "es8323-pcm", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, es8323_i2c_id);
#ifdef ES8323_PROC
static int es8323_proc_init(void);
#endif
static int es8323_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
DBG("%s\n", __func__);
#ifdef ES8323_PROC
es8323_proc_init();
#endif
i2c_client = i2c;
es8323_reset(i2c);
return 0;
}
static int es8323_i2c_remove(struct i2c_client *i2c)
{
return 0;
}
struct i2c_driver es8323_i2c_driver = {
.driver = {
.name = "es8323-pcm",
.owner = THIS_MODULE,
},
.probe = es8323_i2c_probe,
.remove = es8323_i2c_remove,
.id_table = es8323_i2c_id,
};
static int __init es8323_modinit(void)
{
return i2c_add_driver(&es8323_i2c_driver);
}
late_initcall(es8323_modinit);
static void __exit es8323_modexit(void)
{
i2c_del_driver(&es8323_i2c_driver);
}
module_exit(es8323_modexit);
MODULE_DESCRIPTION("ASoC ES8323 driver");
MODULE_AUTHOR("Jear");
MODULE_LICENSE("GPL");
#ifdef ES8323_PROC
static ssize_t es8323_proc_write(struct file *file, const char __user *buffer,
unsigned long len, void *data)
{
char *cookie_pot;
char *p;
int reg;
int value;
cookie_pot = (char *)vmalloc( len );
if (!cookie_pot)
{
return -ENOMEM;
}
else
{
if (copy_from_user( cookie_pot, buffer, len ))
return -EFAULT;
}
switch(cookie_pot[0])
{
case 'r':
case 'R':
printk("Read reg debug\n");
if(cookie_pot[1] ==':')
{
strsep(&cookie_pot,":");
while((p=strsep(&cookie_pot,",")))
{
reg = simple_strtol(p,NULL,16);
value = codec_read(i2c_client,reg);
printk("codec_read:0x%04x = 0x%04x\n",reg,value);
}
printk("\n");
}
else
{
printk("Error Read reg debug.\n");
printk("For example: echo r:22,23,24,25>es8323_ts\n");
}
break;
case 'w':
case 'W':
printk("Write reg debug\n");
if(cookie_pot[1] ==':')
{
strsep(&cookie_pot,":");
while((p=strsep(&cookie_pot,"=")))
{
reg = simple_strtol(p,NULL,16);
p=strsep(&cookie_pot,",");
value = simple_strtol(p,NULL,16);
codec_write(i2c_client,reg,value);
printk("codec_write:0x%04x = 0x%04x\n",reg,value);
}
printk("\n");
}
else
{
printk("Error Write reg debug.\n");
printk("For example: w:22=0,23=0,24=0,25=0>es8323_ts\n");
}
break;
case 'a':
printk("Dump reg \n");
for(reg = 0; reg < 0x6e; reg+=2)
{
value = codec_read(i2c_client,reg);
printk("codec_read:0x%04x = 0x%04x\n",reg,value);
}
break;
default:
printk("Help for es8323_ts .\n-->The Cmd list: \n");
printk("-->'d&&D' Open or Off the debug\n");
printk("-->'r&&R' Read reg debug,Example: echo 'r:22,23,24,25'>es8323_ts\n");
printk("-->'w&&W' Write reg debug,Example: echo 'w:22=0,23=0,24=0,25=0'>es8323_ts\n");
break;
}
return len;
}
static const struct file_operations es8323_proc_fops = {
.owner = THIS_MODULE,
};
static int es8323_proc_init(void)
{
struct proc_dir_entry *es8323_proc_entry;
es8323_proc_entry = create_proc_entry("driver/es8323_pcm_ts", 0777, NULL);
if(es8323_proc_entry != NULL)
{
es8323_proc_entry->write_proc = es8323_proc_write;
return 0;
}
else
{
printk("create proc error !\n");
return -1;
}
}
#endif

93
sound/soc/codecs/gva_codec.c
View File

@@ -1,93 +0,0 @@
/*
* Driver for virtual codec
*
* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
* Author: Li Dongqiang <David.li@rock-chips.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <sound/soc.h>
static const struct snd_soc_dapm_widget gva_codec_widgets[] = {
SND_SOC_DAPM_INPUT("RX"),
SND_SOC_DAPM_OUTPUT("TX"),
};
static const struct snd_soc_dapm_route gva_codec_routes[] = {
{ "Capture", NULL, "RX" },
{ "TX", NULL, "Playback" },
};
#define gva_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static struct snd_soc_dai_driver gva_codec_dai = {
.name = "gva_codec",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = gva_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = gva_FORMATS,
},
};
static struct snd_soc_codec_driver soc_codec_dev_gva_codec = {
.dapm_widgets = gva_codec_widgets,
.num_dapm_widgets = ARRAY_SIZE(gva_codec_widgets),
.dapm_routes = gva_codec_routes,
.num_dapm_routes = ARRAY_SIZE(gva_codec_routes),
};
static int gva_codec_probe(struct platform_device *pdev)
{
return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_gva_codec,
&gva_codec_dai, 1);
}
static int gva_codec_remove(struct platform_device *pdev)
{
snd_soc_unregister_codec(&pdev->dev);
return 0;
}
static const struct of_device_id gva_codec_of_match[] = {
{ .compatible = "rockchip,gva-codec", },
{},
};
MODULE_DEVICE_TABLE(of, gva_codec_of_match);
static struct platform_driver gva_codec_driver = {
.driver = {
.name = "gva_codec",
.of_match_table = of_match_ptr(gva_codec_of_match),
},
.probe = gva_codec_probe,
.remove = gva_codec_remove,
};
module_platform_driver(gva_codec_driver);
MODULE_AUTHOR("Li Dongqiang <David.li@rock-chips.com>");
MODULE_DESCRIPTION("ASoC gva virtual driver");
MODULE_LICENSE("GPL");

8
sound/soc/codecs/pickle.h
View File

@@ -1,8 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef PICKLE_H_
#define PICKLE_H_
void *pickle_pjt(cfw_project *p, int *n);
cfw_project *unpickle_pjt(void *p, int n);
#endif

671
sound/soc/codecs/rk2928_codec.c
View File

@@ -1,671 +0,0 @@
/*
* rk2928_codec.c ALSA SoC RK2928 codec driver
*
* Copyright 2012 Rockchip
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <linux/wakelock.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <mach/cru.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <linux/clk.h>
#include "rk2928_codec.h"
#define HP_OUT 0
#define HP_IN 1
static struct rk2928_codec_data {
struct device *dev;
struct snd_soc_codec *codec;
int regbase;
int regbase_phy;
int regsize_phy;
struct clk *pclk;
int mute;
int hdmi_enable;
int spkctl;
int hp_ctl;
int call_enable;
int headset_status;
struct rk2928_codec_pdata *pdata;
bool stop_phone_depop;
struct delayed_work h_delayed_work;
struct mutex mutex_lock;
} rk2928_data;
static int DAC_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = w->codec;
struct rk2928_codec_data *priv = snd_soc_codec_get_drvdata(codec);
DBG("%s::%d event = %d\n",__FUNCTION__,__LINE__,event);
switch (event) {
case SND_SOC_DAPM_PRE_PMD:
#ifdef CONFIG_MODEM_SOUND
if(rk2928_data.call_enable)
return 0;
#endif
//before widget power down
if(rk2928_data.spkctl != INVALID_GPIO) {
gpio_direction_output(rk2928_data.spkctl, GPIO_LOW);
}
if(rk2928_data.hp_ctl != 0 && rk2928_data.headset_status == HP_IN) {
// gpio_direction_output(rk2928_data.hp_ctl, GPIO_LOW);
}
break;
case SND_SOC_DAPM_POST_PMU:
//after widget power up
if(rk2928_data.spkctl != INVALID_GPIO && rk2928_data.headset_status == HP_OUT) {
gpio_direction_output(rk2928_data.spkctl, GPIO_HIGH);
msleep(200);
}
if(rk2928_data.hp_ctl != 0 ) {//&& rk2928_data.headset_status == HP_IN
gpio_direction_output(rk2928_data.hp_ctl, GPIO_HIGH);
}
break;
}
return 0;
}
static const struct snd_soc_dapm_widget rk2928_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("DACL", "HIFI Playback", CODEC_REG_POWER, 5, 1,DAC_event, SND_SOC_DAPM_PRE_PMD|SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_DAC_E("DACR", "HIFI Playback", CODEC_REG_POWER, 4, 1,DAC_event, SND_SOC_DAPM_PRE_PMD|SND_SOC_DAPM_POST_PMU),
SND_SOC_DAPM_PGA("DACL Amp", CODEC_REG_DAC_GAIN, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("DACR Amp", CODEC_REG_DAC_GAIN, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPKL"),
SND_SOC_DAPM_OUTPUT("SPKR"),
SND_SOC_DAPM_ADC("ADCL", "HIFI Capture", CODEC_REG_POWER, 3, 1),
SND_SOC_DAPM_INPUT("MICL"),
SND_SOC_DAPM_ADC("ADCR", "HIFI Capture", CODEC_REG_POWER, 2, 1),
SND_SOC_DAPM_INPUT("MICR"),
};
static const struct snd_soc_dapm_route rk2928_audio_map[] = {
{"SPKL", "DACL Amp", "DACL"},
{"SPKR", "DACR Amp", "DACR"},
{"ADCL", NULL, "MICL"},
{"ADCR", NULL, "MICR"},
};
static const struct snd_soc_dapm_widget rk2926_dapm_widgets[] = {
SND_SOC_DAPM_DAC("DACL", "HIFI Playback", CODEC_REG_POWER, 5, 1),
SND_SOC_DAPM_DAC("DACR", "HIFI Playback", CODEC_REG_POWER, 4, 1),
SND_SOC_DAPM_PGA("DACL Amp", CODEC_REG_DAC_GAIN, 2, 0, NULL, 0),
SND_SOC_DAPM_PGA("DACR Amp", CODEC_REG_DAC_GAIN, 0, 0, NULL, 0),
SND_SOC_DAPM_OUTPUT("SPKL"),
SND_SOC_DAPM_OUTPUT("SPKR"),
SND_SOC_DAPM_ADC("ADCR", "HIFI Capture", CODEC_REG_POWER, 2, 1),
SND_SOC_DAPM_INPUT("MICR"),
};
static const struct snd_soc_dapm_route rk2926_audio_map[] = {
{"SPKL", "DACL Amp", "DACL"},
{"SPKR", "DACR Amp", "DACR"},
{"ADCR", NULL, "MICR"},
};
static unsigned int rk2928_read(struct snd_soc_codec *codec, unsigned int reg)
{
return readl(rk2928_data.regbase + reg*4);
}
static int rk2928_write(struct snd_soc_codec *codec, unsigned int reg, unsigned int value)
{
#ifdef CONFIG_MODEM_SOUND
if(rk2928_data.call_enable)
return 0;
#endif
DBG("%s reg 0x%02x value 0x%02x", __FUNCTION__, reg, value);
if(reg == 0xc)
value &= ~0x31;
writel(value, rk2928_data.regbase + reg*4);
if( (reg == CODEC_REG_POWER) && ( (value & m_PD_DAC) == 0)) {
msleep(100);
}
return 0;
}
static int rk2928_write_incall(struct snd_soc_codec *codec, unsigned int reg, unsigned int value)
{
DBG("%s reg 0x%02x value 0x%02x", __FUNCTION__, reg, value);
if(reg == 0xc)
value &= ~0x31;
writel(value, rk2928_data.regbase + reg*4);
if( (reg == CODEC_REG_POWER) && ( (value & m_PD_DAC) == 0)) {
msleep(100);
}
return 0;
}
static int rk2928_write_mask(struct snd_soc_codec *codec, unsigned int reg,
unsigned int mask, unsigned int value)
{
unsigned int regvalue = rk2928_read(codec, reg);
DBG("%s reg 0x%02x mask 0x%02x value 0x%02x", __FUNCTION__, reg, mask, value);
regvalue &= ~mask;
regvalue |= mask & value;
return rk2928_write(codec, reg, regvalue);
}
static void call_delay_work(struct work_struct *work)
{
struct snd_soc_codec *codec = rk2928_data.codec;
if(codec == NULL)
return;
printk("%s speaker is disabled\n", __FUNCTION__);
rk2928_write_incall(NULL, CODEC_REG_DAC_MUTE, v_MUTE_DAC(0));
rk2928_write_incall(codec, CODEC_REG_POWER, 0x0c);
rk2928_write_incall(codec, CODEC_REG_ADC_SOURCE, 0x03);
rk2928_write_incall(codec, CODEC_REG_ADC_PGA_GAIN, 0x33);//spk 0x33
rk2928_data.call_enable = 1;
mutex_unlock(&rk2928_data.mutex_lock);
}
#ifdef CONFIG_MODEM_SOUND
void call_set_spk(int on)
{
struct snd_soc_codec *codec = rk2928_data.codec;
if(codec == NULL)
return;
mutex_lock(&rk2928_data.mutex_lock);
switch(on)
{
case 0:
printk("%s speaker is enabled\n", __FUNCTION__);
rk2928_data.call_enable = 0;
// rk2928_write(NULL, CODEC_REG_DAC_MUTE, v_MUTE_DAC(0));
rk2928_write(codec, CODEC_REG_ADC_SOURCE, 0x00);
printk("rk2928 codec stop phone need depop\n");
rk2928_data.stop_phone_depop = true;
break;
case 1:
rk2928_write_incall(NULL, CODEC_REG_DAC_MUTE, v_MUTE_DAC(1));
schedule_delayed_work(&rk2928_data.h_delayed_work, msecs_to_jiffies(1000));
return;
case 2:
printk("%s speaker is disabled\n", __FUNCTION__);
rk2928_write(NULL, CODEC_REG_DAC_MUTE, v_MUTE_DAC(0));
rk2928_write(codec, CODEC_REG_POWER, 0x0c);
rk2928_write(codec, CODEC_REG_ADC_SOURCE, 0x03);
rk2928_write(codec, CODEC_REG_ADC_PGA_GAIN, 0x11);//headset
rk2928_data.call_enable = 1;
break;
case 3:
printk("%s speaker is disabled\n", __FUNCTION__);
rk2928_write(NULL, CODEC_REG_DAC_MUTE, v_MUTE_DAC(0));
rk2928_write(codec, CODEC_REG_POWER, 0x0c);
rk2928_write(codec, CODEC_REG_ADC_SOURCE, 0x03);
rk2928_write(codec, CODEC_REG_ADC_PGA_GAIN, 0x33);//spk 0x33
rk2928_data.call_enable = 1;
break;
}
mutex_unlock(&rk2928_data.mutex_lock);
return;
}
#endif
#ifdef CONFIG_RK_HEADSET_DET
//for headset
void rk2928_codec_set_spk(bool on)
{
struct snd_soc_codec *codec = rk2928_data.codec;
if(codec == NULL)
return;
if(on)
rk2928_data.headset_status = HP_IN;
else
rk2928_data.headset_status = HP_OUT;
if(rk2928_data.call_enable)
return;
printk("%s: headset %s %s PA bias_level=%d\n",__FUNCTION__,on?"in":"out",on?"disable":"enable",codec->dapm.bias_level);
if(on) {
if(rk2928_data.spkctl != INVALID_GPIO)
{
gpio_direction_output(rk2928_data.spkctl, GPIO_LOW);
}
}
else {
if(codec->dapm.bias_level == SND_SOC_BIAS_STANDBY
|| codec->dapm.bias_level == SND_SOC_BIAS_OFF){
return;
}
if(rk2928_data.spkctl != INVALID_GPIO)
{
gpio_direction_output(rk2928_data.spkctl, GPIO_HIGH);
}
}
}
#endif
static int rk2928_audio_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
// struct snd_soc_pcm_runtime *rtd = substream->private_data;
// struct snd_soc_codec *codec = rtd->codec;
// struct rk2928_codec_data *priv = snd_soc_codec_get_drvdata(codec);
DBG("%s", __FUNCTION__);
return 0;
}
static int rk2928_audio_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *dai)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_codec *codec = rtd->codec;
struct rk2928_codec_data *priv = snd_soc_codec_get_drvdata(codec);
int err = 0;
int data, pd_adc;
DBG("%s cmd 0x%x", __FUNCTION__, cmd);
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
// rk2928_write(codec, CODEC_REG_DAC_GAIN, v_GAIN_DAC(DAC_GAIN_3DB_P));
if(!rk2928_data.hdmi_enable) {
data = rk2928_read(codec, CODEC_REG_POWER);
if(soc_is_rk2928g()){
if( (data & m_PD_ADC) == 0) {
data &= ~m_PD_ADC;
data |= v_PD_ADC(1);
pd_adc = 1;
}
else
pd_adc = 0;
}
else{
if( (data & m_PD_ADC_R) == 0) {
data &= ~m_PD_ADC_R;
data |= v_PD_ADC_R(1);
pd_adc = 1;
}
else
pd_adc = 0;
}
if(pd_adc == 1) {
DBG("%s reg 0x%02x value 0x%02x", __FUNCTION__, CODEC_REG_POWER, data);
writel(data, rk2928_data.regbase + CODEC_REG_POWER*4);
udelay(100);
}
rk2928_write(codec, CODEC_REG_ADC_SOURCE, 0x03);
udelay(100);
rk2928_write(codec, CODEC_REG_ADC_SOURCE, 0x00);
udelay(100);
rk2928_write(codec, CODEC_REG_ADC_SOURCE, 0x03);
udelay(100);
rk2928_write(codec, CODEC_REG_ADC_SOURCE, 0x00);
udelay(100);
rk2928_write(codec, CODEC_REG_ADC_SOURCE, 0x03);
udelay(100);
rk2928_write(codec, CODEC_REG_ADC_SOURCE, 0x00);
if(pd_adc == 1) {
udelay(100);
data = rk2928_read(codec, CODEC_REG_POWER);
if( soc_is_rk2928g() ) {
data &= ~m_PD_ADC;
data |= v_PD_ADC(0);
}
else {
data &= ~m_PD_ADC_R;
data |= v_PD_ADC_R(0);
}
DBG("%s reg 0x%02x value 0x%02x", __FUNCTION__, CODEC_REG_POWER, data);
writel(data, rk2928_data.regbase + CODEC_REG_POWER*4);
}
rk2928_write(codec, CODEC_REG_DAC_MUTE, v_MUTE_DAC(0));
if(rk2928_data.spkctl != INVALID_GPIO && rk2928_data.headset_status == HP_OUT && rk2928_data.stop_phone_depop ) {
mdelay(100);
gpio_direction_output(rk2928_data.spkctl, GPIO_HIGH);
rk2928_data.stop_phone_depop = false;
}
}
rk2928_data.mute = 0;
// if(rk2928_data.spkctl != INVALID_GPIO && rk2928_data.headset_status == HP_OUT) {
// gpio_direction_output(rk2928_data.spkctl, GPIO_HIGH);
// }
}
else {
rk2928_write(codec, CODEC_REG_ADC_PGA_GAIN, 0xFF);
rk2928_write(codec, 0x08, 0xff);
rk2928_write(codec, 0x09, 0x07);
}
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
#ifdef CONFIG_MODEM_SOUND
if(rk2928_data.call_enable)
return err;
#endif
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
//if(rk2928_data.spkctl != INVALID_GPIO) {
//gpio_direction_output(rk2928_data.spkctl, GPIO_LOW);
//}
rk2928_write(codec, CODEC_REG_DAC_MUTE, v_MUTE_DAC(1));
rk2928_data.mute = 1;
}
break;
default:
err = -EINVAL;
}
return err;
}
static int rk2928_audio_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
// struct snd_soc_pcm_runtime *rtd = substream->private_data;
// struct snd_soc_codec *codec = rtd->codec;
DBG("%s", __FUNCTION__);
return 0;
}
static int rk2928_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
DBG("%s level %d\n", __FUNCTION__, level);
if(codec == NULL)
return -1;
switch(level)
{
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
rk2928_write_mask(codec, CODEC_REG_POWER, m_PD_MIC_BIAS | m_PD_CODEC, v_PD_MIC_BIAS(0) | v_PD_CODEC(0));
break;
case SND_SOC_BIAS_STANDBY:
case SND_SOC_BIAS_OFF:
printk("rk2928 codec standby\n");
#ifdef CONFIG_MODEM_SOUND
if(rk2928_data.call_enable)
break;
#endif
// if(rk2928_data.spkctl != INVALID_GPIO) {
// gpio_direction_output(rk2928_data.spkctl, GPIO_LOW);
// }
rk2928_write(codec, CODEC_REG_POWER, v_PWR_OFF);
break;
default:
return -1;
}
codec->dapm.bias_level = level;
return 0;
}
static void rk2929_codec_reset(void)
{
// Reset Codec
cru_set_soft_reset(SOFT_RST_ACODEC, true);
udelay(1000);
cru_set_soft_reset(SOFT_RST_ACODEC, false);
}
static int rk2928_probe(struct snd_soc_codec *codec)
{
struct platform_device *pdev = to_platform_device(codec->dev);
struct snd_soc_dapm_context *dapm = &codec->dapm;
struct resource *res, *mem;
struct rk2928_codec_pdata *pdata;
int ret;
DBG("%s", __FUNCTION__);
snd_soc_codec_set_drvdata(codec, &rk2928_data);
rk2928_data.dev = &pdev->dev;
rk2928_data.pdata = pdev->dev.platform_data;
pdata = rk2928_data.pdata;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "Unable to get register resource\n");
ret = -ENXIO;
goto err0;
}
rk2928_data.regbase_phy = res->start;
rk2928_data.regsize_phy = (res->end - res->start) + 1;
mem = request_mem_region(res->start, (res->end - res->start) + 1, pdev->name);
if (!mem)
{
dev_err(&pdev->dev, "failed to request mem region for rk2928 codec\n");
ret = -ENOENT;
goto err0;
}
rk2928_data.regbase = (int)ioremap(res->start, (res->end - res->start) + 1);
if (!rk2928_data.regbase) {
dev_err(&pdev->dev, "cannot ioremap acodec registers\n");
ret = -ENXIO;
goto err1;
}
rk2928_data.pclk = clk_get(NULL,"pclk_acodec");
if(IS_ERR(rk2928_data.pclk))
{
dev_err(rk2928_data.dev, "Unable to get acodec hclk\n");
ret = -ENXIO;
goto err1;
}
clk_enable(rk2928_data.pclk);
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
if(!res) {
rk2928_data.spkctl = INVALID_GPIO;
}
else {
rk2928_data.spkctl = res->start;
}
if(rk2928_data.spkctl != INVALID_GPIO) {
ret = gpio_request(rk2928_data.spkctl, NULL);
if (ret != 0) {
gpio_free(rk2928_data.spkctl);
}
else
gpio_direction_output(rk2928_data.spkctl, GPIO_LOW);
}
//------------------------------------------------------------------
if (pdata->hpctl) {
ret = pdata->hpctl_io_init();
if (ret)
goto err1;
rk2928_data.hp_ctl = pdata->hpctl;
gpio_direction_output(rk2928_data.hp_ctl, GPIO_LOW);
}
//Reset Codec
rk2929_codec_reset();
// Select SDI input from internal audio codec
writel(0x04000400, RK2928_GRF_BASE + GRF_SOC_CON0);
// Mute and Power off codec
rk2928_write(codec, CODEC_REG_DAC_MUTE, v_MUTE_DAC(1));
rk2928_set_bias_level(codec, SND_SOC_BIAS_OFF);
if(soc_is_rk2928g()){
snd_soc_dapm_new_controls(dapm, rk2928_dapm_widgets,
ARRAY_SIZE(rk2928_dapm_widgets));
snd_soc_dapm_add_routes(dapm, rk2928_audio_map, ARRAY_SIZE(rk2928_audio_map));
}else{
snd_soc_dapm_new_controls(dapm, rk2926_dapm_widgets,
ARRAY_SIZE(rk2926_dapm_widgets));
snd_soc_dapm_add_routes(dapm, rk2926_audio_map, ARRAY_SIZE(rk2926_audio_map));
}
INIT_DELAYED_WORK(&rk2928_data.h_delayed_work, call_delay_work);
mutex_init(&rk2928_data.mutex_lock);
rk2928_data.call_enable = 0;
rk2928_data.headset_status = HP_OUT;
rk2928_data.codec=codec;
rk2928_data.stop_phone_depop=false;
return 0;
err1:
release_mem_region(res->start,(res->end - res->start) + 1);
// clk_disable(rk2928_data.hclk);
err0:
DBG("%s failed", __FUNCTION__);
return ret;
}
static int rk2928_remove(struct snd_soc_codec *codec)
{
return 0;
}
static int rk2928_suspend(struct snd_soc_codec *codec)
{
DBG("%s", __FUNCTION__);
rk2928_set_bias_level(codec, SND_SOC_BIAS_OFF);
clk_disable(rk2928_data.pclk);
return 0;
}
static int rk2928_resume(struct snd_soc_codec *codec)
{
DBG("%s", __FUNCTION__);
clk_enable(rk2928_data.pclk);
rk2928_write(codec, CODEC_REG_POWER, v_PD_ADC(1) | v_PD_DAC(1) | v_PD_MIC_BIAS(0));
return 0;
}
static struct snd_soc_codec_driver rk2928_audio_codec_drv = {
.probe = rk2928_probe,
.remove = rk2928_remove,
.suspend = rk2928_suspend,
.resume = rk2928_resume,
.read = rk2928_read,
.write = rk2928_write,
.set_bias_level = rk2928_set_bias_level,
};
static struct snd_soc_dai_ops rk2928_audio_codec_ops = {
.hw_params = rk2928_audio_hw_params,
.trigger = rk2928_audio_trigger,
.startup = rk2928_audio_startup,
};
static struct snd_soc_dai_driver rk2928_codec_dai = {
.name = "rk2928-codec",
.playback = {
.stream_name = "HIFI Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |
SNDRV_PCM_FMTBIT_S24_LE,
},
.capture = {
.stream_name = "HIFI Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_48000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE,
},
.ops = &rk2928_audio_codec_ops,
};
static int rk2928_codec_probe(struct platform_device *pdev)
{
int r;
DBG("%s", __FUNCTION__);
/* Register ASoC codec DAI */
r = snd_soc_register_codec(&pdev->dev, &rk2928_audio_codec_drv,
&rk2928_codec_dai, 1);
if (r) {
dev_err(&pdev->dev, "can't register ASoC rk2928 audio codec\n");
return r;
}
DBG("%s success", __FUNCTION__);
return 0;
}
static int __devexit rk2928_codec_remove(struct platform_device *pdev)
{
snd_soc_unregister_codec(&pdev->dev);
return 0;
}
static void rk2928_codec_shutdown(struct platform_device *pdev)
{
printk("%s .....\n", __FUNCTION__);
if(rk2928_data.spkctl != INVALID_GPIO)
gpio_direction_output(rk2928_data.spkctl, GPIO_LOW);
if(rk2928_data.hp_ctl != 0 )
gpio_direction_output(rk2928_data.hp_ctl, GPIO_LOW);
}
static struct platform_driver rk2928_codec_driver = {
.probe = rk2928_codec_probe,
.remove = __devexit_p(rk2928_codec_remove),
.driver = {
.name = "rk2928-codec",
.owner = THIS_MODULE,
},
.shutdown = rk2928_codec_shutdown,
};
static int __init rk2928_codec_init(void)
{
return platform_driver_register(&rk2928_codec_driver);
}
module_init(rk2928_codec_init);
static void __exit rk2928_codec_exit(void)
{
#ifdef CODEC_I2C_MODE
i2c_del_driver(&rk2928_codec_driver);
#else
platform_driver_unregister(&rk2928_codec_driver);
#endif
}
module_exit(rk2928_codec_exit);
MODULE_DESCRIPTION("ASoC RK2928 codec driver");
MODULE_LICENSE("GPL");

89
sound/soc/codecs/rk2928_codec.h
View File

@@ -1,89 +0,0 @@
/*
* rk2928.h ALSA SoC RK2928 codec driver
*
* Copyright 2012 Rockchip
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RK2928_CODEC_H__
#define __RK2928_CODEC_H__
#define CODEC_REG_ADC_DIGITAL_GIAN_L 0x08
#define CODEC_REG_ADC_DIGITAL_GIAN_H 0x09
#define CODEC_REG_ADC_PGA_GAIN 0x0b
#define m_MIC_GAIN_CHANNEL_L (0x0F << 4)
#define m_MIC_GAIN_CHANNEL_R (0x0F)
#define v_MIC_GAIN_CHANNEL_L(n) ((n) << 4)
#define v_MIC_GAIN_CHANNEL_R(n) (n)
#define CODEC_REG_POWER 0x0c
#define m_PD_CODEC (0x01)
#define m_PD_MIC_BIAS (0x01 << 1)
#define m_PD_ADC_R (0x01 << 2)
#define m_PD_ADC_L (0x01 << 3)
#define m_PD_ADC (0x03 << 2)
#define m_PD_DAC (0x03 << 4)
#define v_PD_CODEC(n) (n)
#define v_PD_MIC_BIAS(n) (n << 1)
#define v_PD_ADC_R(n) (n << 2)
#define v_PD_ADC_L(n) (n << 3)
#define v_PD_DAC_R(n) (n << 4)
#define v_PD_DAC_L(n) (n << 5)
#define v_PD_ADC(n) (v_PD_ADC_L(n) | v_PD_ADC_R(n))
#define v_PD_DAC(n) (v_PD_DAC_L(n) | v_PD_DAC_R(n))
#define v_PWR_OFF v_PD_DAC_L(1) | v_PD_DAC_R(1) | v_PD_ADC_L(1) | v_PD_ADC_R(1) | v_PD_MIC_BIAS(0) | v_PD_CODEC(1) //²»¹Ø±Õmic_bias for phone_pad
#define CODEC_REG_VCM_BIAS 0x0d
#define v_MIC_BIAS(n) (n)
enum {
VCM_RESISTOR_100K = 0,
VCM_RESISTOR_25K
};
#define v_VCM_25K_100K(n) (n << 2)
#define CODEC_REG_DAC_MUTE 0x0e
#define v_MUTE_DAC_L(n) (n << 1)
#define v_MUTE_DAC_R(n) (n)
#define v_MUTE_DAC(n) v_MUTE_DAC_L(n) | v_MUTE_DAC_R(n)
#define CODEC_REG_ADC_SOURCE 0x0f
enum {
ADC_SRC_MIC = 0,
ADC_SRC_LINE_IN
};
#define v_SRC_ADC_L(n) (n << 1)
#define v_SRC_ADC_R(n) (n)
#define CODEC_REG_DAC_GAIN 0x10
#define m_GAIN_DAC_L (0x03 << 2)
#define m_GAIN_DAC_R (0x03)
enum {
DAC_GAIN_0DB = 0,
DAC_GAIN_3DB_P = 0x2, //3db
DAC_GAIN_3DB_N //-3db
};
#define v_GAIN_DAC_L(n) (n << 2)
#define v_GAIN_DAC_R(n) (n)
#define v_GAIN_DAC(n) (v_GAIN_DAC_L(n) | v_GAIN_DAC_R(n))
//#ifndef DEBUG
//#define DEBUG
//#endif
#ifdef DEBUG
#define DBG(format, ...) \
printk(KERN_INFO "RK2928 CODEC: " format "\n", ## __VA_ARGS__)
#else
#define DBG(format, ...)
#endif
struct rk2928_codec_pdata {
int hpctl;
int (*hpctl_io_init)(void);
};
#endif /* __RK2928_CODEC_H__ */

2169
sound/soc/codecs/rk3026_codec.c
View File

File diff suppressed because it is too large Load Diff

565
sound/soc/codecs/rk3026_codec.h
View File

@@ -1,565 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* rk3026.h -- RK3026 CODEC ALSA SoC audio driver
*
* Copyright 2013 Rockship
* Author: chenjq <chenjq@rock-chips.com>
*
*/
#ifndef __RK3026_CODEC_H__
#define __RK3026_CODEC_H__
/* codec register */
#define RK3026_CODEC_BASE (0x0)
#define RK3026_RESET (RK3026_CODEC_BASE + 0x00)
#define RK3026_ADC_INT_CTL1 (RK3026_CODEC_BASE + 0x08)
#define RK3026_ADC_INT_CTL2 (RK3026_CODEC_BASE + 0x0c)
#define RK3026_DAC_INT_CTL1 (RK3026_CODEC_BASE + 0x10)
#define RK3026_DAC_INT_CTL2 (RK3026_CODEC_BASE + 0x14)
#define RK3026_DAC_INT_CTL3 (RK3026_CODEC_BASE + 0x18)
#define RK3026_ADC_MIC_CTL (RK3026_CODEC_BASE + 0x88)
#define RK3026_BST_CTL (RK3026_CODEC_BASE + 0x8c)
#define RK3026_ALC_MUNIN_CTL (RK3026_CODEC_BASE + 0x90)
#define RK3026_BSTL_ALCL_CTL (RK3026_CODEC_BASE + 0x94)
#define RK3026_ALCR_GAIN_CTL (RK3026_CODEC_BASE + 0x98)
#define RK3026_ADC_ENABLE (RK3026_CODEC_BASE + 0x9c)
#define RK3026_DAC_CTL (RK3026_CODEC_BASE + 0xa0)
#define RK3026_DAC_ENABLE (RK3026_CODEC_BASE + 0xa4)
#define RK3026_HPMIX_CTL (RK3026_CODEC_BASE + 0xa8)
#define RK3026_HPMIX_S_SELECT (RK3026_CODEC_BASE + 0xac)
#define RK3026_HPOUT_CTL (RK3026_CODEC_BASE + 0xB0)
#define RK3026_HPOUTL_GAIN (RK3026_CODEC_BASE + 0xB4)
#define RK3026_HPOUTR_GAIN (RK3026_CODEC_BASE + 0xB8)
#define RK3026_SELECT_CURRENT (RK3026_CODEC_BASE + 0xBC)
#define RK3026_PGAL_AGC_CTL1 (RK3026_CODEC_BASE + 0x100)
#define RK3026_PGAL_AGC_CTL2 (RK3026_CODEC_BASE + 0x104)
#define RK3026_PGAL_AGC_CTL3 (RK3026_CODEC_BASE + 0x108)
#define RK3026_PGAL_AGC_CTL4 (RK3026_CODEC_BASE + 0x10c)
#define RK3026_PGAL_ASR_CTL (RK3026_CODEC_BASE + 0x110)
#define RK3026_PGAL_AGC_MAX_H (RK3026_CODEC_BASE + 0x114)
#define RK3026_PGAL_AGC_MAX_L (RK3026_CODEC_BASE + 0x118)
#define RK3026_PGAL_AGC_MIN_H (RK3026_CODEC_BASE + 0x11c)
#define RK3026_PGAL_AGC_MIN_L (RK3026_CODEC_BASE + 0x120)
#define RK3026_PGAL_AGC_CTL5 (RK3026_CODEC_BASE + 0x124)
#define RK3026_PGAR_AGC_CTL1 (RK3026_CODEC_BASE + 0x140)
#define RK3026_PGAR_AGC_CTL2 (RK3026_CODEC_BASE + 0x144)
#define RK3026_PGAR_AGC_CTL3 (RK3026_CODEC_BASE + 0x148)
#define RK3026_PGAR_AGC_CTL4 (RK3026_CODEC_BASE + 0x14c)
#define RK3026_PGAR_ASR_CTL (RK3026_CODEC_BASE + 0x150)
#define RK3026_PGAR_AGC_MAX_H (RK3026_CODEC_BASE + 0x154)
#define RK3026_PGAR_AGC_MAX_L (RK3026_CODEC_BASE + 0x158)
#define RK3026_PGAR_AGC_MIN_H (RK3026_CODEC_BASE + 0x15c)
#define RK3026_PGAR_AGC_MIN_L (RK3026_CODEC_BASE + 0x160)
#define RK3026_PGAR_AGC_CTL5 (RK3026_CODEC_BASE + 0x164)
/* ADC Interface Control 1 (0x08) */
#define RK3026_ALRCK_POL_MASK (0x1 << 7)
#define RK3026_ALRCK_POL_SFT 7
#define RK3026_ALRCK_POL_EN (0x1 << 7)
#define RK3026_ALRCK_POL_DIS (0x0 << 7)
#define RK3026_ADC_VWL_MASK (0x3 << 5)
#define RK3026_ADC_VWL_SFT 5
#define RK3026_ADC_VWL_32 (0x3 << 5)
#define RK3026_ADC_VWL_24 (0x2 << 5)
#define RK3026_ADC_VWL_20 (0x1 << 5)
#define RK3026_ADC_VWL_16 (0x0 << 5)
#define RK3026_ADC_DF_MASK (0x3 << 3)
#define RK3026_ADC_DF_SFT 3
#define RK3026_ADC_DF_PCM (0x3 << 3)
#define RK3026_ADC_DF_I2S (0x2 << 3)
#define RK3026_ADC_DF_LJ (0x1 << 3)
#define RK3026_ADC_DF_RJ (0x0 << 3)
#define RK3026_ADC_SWAP_MASK (0x1 << 1)
#define RK3026_ADC_SWAP_SFT 1
#define RK3026_ADC_SWAP_EN (0x1 << 1)
#define RK3026_ADC_SWAP_DIS (0x0 << 1)
#define RK3026_ADC_TYPE_MASK 0x1
#define RK3026_ADC_TYPE_SFT 0
#define RK3026_ADC_TYPE_MONO 0x1
#define RK3026_ADC_TYPE_STEREO 0x0
/* ADC Interface Control 2 (0x0c) */
#define RK3026_I2S_MODE_MASK (0x1 << 4)
#define RK3026_I2S_MODE_SFT (4)
#define RK3026_I2S_MODE_MST (0x1 << 4)
#define RK3026_I2S_MODE_SLV (0x0 << 4)
#define RK3026_ADC_WL_MASK (0x3 << 2)
#define RK3026_ADC_WL_SFT (2)
#define RK3026_ADC_WL_32 (0x3 << 2)
#define RK3026_ADC_WL_24 (0x2 << 2)
#define RK3026_ADC_WL_20 (0x1 << 2)
#define RK3026_ADC_WL_16 (0x0 << 2)
#define RK3026_ADC_RST_MASK (0x1 << 1)
#define RK3026_ADC_RST_SFT 91)
#define RK3026_ADC_RST_DIS (0x1 << 1)
#define RK3026_ADC_RST_EN (0x0 << 1)
#define RK3026_ABCLK_POL_MASK 0x1
#define RK3026_ABCLK_POL_SFT 0
#define RK3026_ABCLK_POL_EN 0x1
#define RK3026_ABCLK_POL_DIS 0x0
/* DAC Interface Control 1 (0x10) */
#define RK3026_DLRCK_POL_MASK (0x1 << 7)
#define RK3026_DLRCK_POL_SFT 7
#define RK3026_DLRCK_POL_EN (0x1 << 7)
#define RK3026_DLRCK_POL_DIS (0x0 << 7)
#define RK3026_DAC_VWL_MASK (0x3 << 5)
#define RK3026_DAC_VWL_SFT 5
#define RK3026_DAC_VWL_32 (0x3 << 5)
#define RK3026_DAC_VWL_24 (0x2 << 5)
#define RK3026_DAC_VWL_20 (0x1 << 5)
#define RK3026_DAC_VWL_16 (0x0 << 5)
#define RK3026_DAC_DF_MASK (0x3 << 3)
#define RK3026_DAC_DF_SFT 3
#define RK3026_DAC_DF_PCM (0x3 << 3)
#define RK3026_DAC_DF_I2S (0x2 << 3)
#define RK3026_DAC_DF_LJ (0x1 << 3)
#define RK3026_DAC_DF_RJ (0x0 << 3)
#define RK3026_DAC_SWAP_MASK (0x1 << 2)
#define RK3026_DAC_SWAP_SFT 2
#define RK3026_DAC_SWAP_EN (0x1 << 2)
#define RK3026_DAC_SWAP_DIS (0x0 << 2)
/* DAC Interface Control 2 (0x14) */
#define RK3026_DAC_WL_MASK (0x3 << 2)
#define RK3026_DAC_WL_SFT 2
#define RK3026_DAC_WL_32 (0x3 << 2)
#define RK3026_DAC_WL_24 (0x2 << 2)
#define RK3026_DAC_WL_20 (0x1 << 2)
#define RK3026_DAC_WL_16 (0x0 << 2)
#define RK3026_DAC_RST_MASK (0x1 << 1)
#define RK3026_DAC_RST_SFT 1
#define RK3026_DAC_RST_DIS (0x1 << 1)
#define RK3026_DAC_RST_EN (0x0 << 1)
#define RK3026_DBCLK_POL_MASK 0x1
#define RK3026_DBCLK_POL_SFT 0
#define RK3026_DBCLK_POL_EN 0x1
#define RK3026_DBCLK_POL_DIS 0x0
/* ADC & MICBIAS (0x88) */
#define RK3026_ADC_CURRENT_ENABLE (0x1 << 7)
#define RK3026_ADC_CURRENT_DISABLE (0x0 << 7)
#define RK3026_MICBIAS_VOL_ENABLE (6)
#define RK3026_ADCL_ZERO_DET_EN_SFT (5)
#define RK3026_ADCL_ZERO_DET_EN (0x1 << 5)
#define RK3026_ADCL_ZERO_DET_DIS (0x0 << 5)
#define RK3026_ADCR_ZERO_DET_EN_SFT (4)
#define RK3026_ADCR_ZERO_DET_EN (0x1 << 4)
#define RK3026_ADCR_ZERO_DET_DIS (0x0 << 4)
#define RK3026_MICBIAS_VOL_SHT 0
#define RK3026_MICBIAS_VOL_MSK 7
#define RK3026_MICBIAS_VOL_MIN (0x0 << 0)
#define RK3026_MICBIAS_VOL_MAX (0x7 << 0)
/* BST_L BST_R CONTROL (0x8C) */
#define RK3026_BSTL_PWRD_SFT (6)
#define RK3026_BSTL_EN (0x1 << 6)
#define RK3026_BSTL_DIS (0x0 << 6)
#define RK3026_BSTL_GAIN_SHT (5)
#define RK3026_BSTL_GAIN_20 (0x1 << 5)
#define RK3026_BSTL_GAIN_0 (0x0 << 5)
#define RK3026_BSTL_MUTE_SHT (4)
#define RK3026_BSTR_PWRD_SFT (2)
#define RK3026_BSTR_EN (0x1 << 2)
#define RK3026_BSTR_DIS (0x0 << 2)
#define RK3026_BSTR_GAIN_SHT (1)
#define RK3026_BSTR_GAIN_20 (0x1 << 1)
#define RK3026_BSTR_GAIN_0 (0x0 << 1)
#define RK3026_BSTR_MUTE_SHT (0)
/* MUXINL ALCL MUXINR ALCR (0x90) */
#define RK3026_MUXINL_F_SHT (6)
#define RK3026_MUXINL_F_MSK (0x03 << 6)
#define RK3026_MUXINL_F_INL (0x02 << 6)
#define RK3026_MUXINL_F_BSTL (0x01 << 6)
#define RK3026_ALCL_PWR_SHT (5)
#define RK3026_ALCL_EN (0x1 << 5)
#define RK3026_ALCL_DIS (0x0 << 5)
#define RK3026_ALCL_MUTE_SHT (4)
#define RK3026_MUXINR_F_SHT (2)
#define RK3026_MUXINR_F_MSK (0x03 << 2)
#define RK3026_MUXINR_F_INR (0x02 << 2)
#define RK3026_MUXINR_F_BSTR (0x01 << 2)
#define RK3026_ALCR_PWR_SHT (1)
#define RK3026_ALCR_EN (0x1 << 1)
#define RK3026_ALCR_DIS (0x0 << 1)
#define RK3026_ALCR_MUTE_SHT (0)
/* BST_L MODE & ALC_L GAIN (0x94) */
#define RK3026_BSTL_MODE_SFT (5)
#define RK3026_BSTL_MODE_SINGLE (0x1 << 5)
#define RK3026_BSTL_MODE_DIFF (0x0 << 5)
#define RK3026_ALCL_GAIN_SHT (0)
#define RK3026_ALCL_GAIN_MSK (0x1f)
/* ALC_R GAIN (0x98) */
#define RK3026_ALCR_GAIN_SHT (0)
#define RK3026_ALCR_GAIN_MSK (0x1f)
/* ADC control (0x9C) */
#define RK3026_ADCL_REF_VOL_EN_SFT (3)
#define RK3026_ADCL_REF_VOL_EN (0x1 << 7)
#define RK3026_ADCL_REF_VOL_DIS (0x0 << 7)
#define RK3026_ADCL_CLK_EN_SFT (6)
#define RK3026_ADCL_CLK_EN (0x1 << 6)
#define RK3026_ADCL_CLK_DIS (0x0 << 6)
#define RK3026_ADCL_AMP_EN_SFT (5)
#define RK3026_ADCL_AMP_EN (0x1 << 5)
#define RK3026_ADCL_AMP_DIS (0x0 << 5)
#define RK3026_ADCL_RST_EN (0x1 << 4)
#define RK3026_ADCL_RST_DIS (0x0 << 4)
#define RK3026_ADCR_REF_VOL_EN_SFT (3)
#define RK3026_ADCR_REF_VOL_EN (0x1 << 3)
#define RK3026_ADCR_REF_VOL_DIS (0x0 << 3)
#define RK3026_ADCR_CLK_EN_SFT (2)
#define RK3026_ADCR_CLK_EN (0x1 << 2)
#define RK3026_ADCR_CLK_DIS (0x0 << 2)
#define RK3026_ADCR_AMP_EN_SFT (1)
#define RK3026_ADCR_AMP_EN (0x1 << 1)
#define RK3026_ADCR_AMP_DIS (0x0 << 1)
#define RK3026_ADCR_RST_EN (0x1 << 0)
#define RK3026_ADCR_RST_DIS (0x0 << 0)
/* DAC & VOUT Control (0xa0) */
#define RK3026_CURRENT_EN (0x1 << 6)
#define RK3026_CURRENT_DIS (0x0 << 6)
#define RK3026_REF_VOL_DACL_EN_SFT (5)
#define RK3026_REF_VOL_DACL_EN (0x1 << 5)
#define RK3026_REF_VOL_DACL_DIS (0x0 << 5)
#define RK3026_ZO_DET_VOUTL_SFT (4)
#define RK3026_ZO_DET_VOUTL_EN (0x1 << 4)
#define RK3026_ZO_DET_VOUTL_DIS (0x0 << 4)
#define RK3026_DET_ERAPHONE_DIS (0x0 << 3)
#define RK3026_DET_ERAPHONE_EN (0x1 << 3)
#define RK3026_REF_VOL_DACR_EN_SFT (1)
#define RK3026_REF_VOL_DACR_EN (0x1 << 1)
#define RK3026_REF_VOL_DACR_DIS (0x0 << 1)
#define RK3026_ZO_DET_VOUTR_SFT (0)
#define RK3026_ZO_DET_VOUTR_EN (0x1 << 0)
#define RK3026_ZO_DET_VOUTR_DIS (0x0 << 0)
/* DAC control (0xa4) */
#define RK3026_DACL_REF_VOL_EN_SFT (7)
#define RK3026_DACL_REF_VOL_EN (0x1 << 7)
#define RK3026_DACL_REF_VOL_DIS (0x0 << 7)
#define RK3026_DACL_CLK_EN (0x1 << 6)
#define RK3026_DACL_CLK_DIS (0x0 << 6)
#define RK3026_DACL_EN (0x1 << 5)
#define RK3026_DACL_DIS (0x0 << 5)
#define RK3026_DACL_INIT (0x0 << 4)
#define RK3026_DACL_WORK (0x1 << 4)
#define RK3026_DACR_REF_VOL_EN_SFT (3)
#define RK3026_DACR_REF_VOL_EN (0x1 << 3)
#define RK3026_DACR_REF_VOL_DIS (0x0 << 3)
#define RK3026_DACR_CLK_EN (0x1 << 2)
#define RK3026_DACR_CLK_DIS (0x0 << 2)
#define RK3026_DACR_EN (0x1 << 1)
#define RK3026_DACR_DIS (0x0 << 1)
#define RK3026_DACR_INIT (0x0 << 0)
#define RK3026_DACR_WORK (0x1 << 0)
/* HPMIXL HPMIXR Control (0xa8) */
#define RK3026_HPMIXL_SFT (6)
#define RK3026_HPMIXL_EN (0x1 << 6)
#define RK3026_HPMIXL_DIS (0x0 << 6)
#define RK3026_HPMIXL_INIT1 (0x0 << 5)
#define RK3026_HPMIXL_WORK1 (0x1 << 5)
#define RK3026_HPMIXL_INIT2 (0x0 << 4)
#define RK3026_HPMIXL_WORK2 (0x1 << 4)
#define RK3026_HPMIXR_SFT (2)
#define RK3026_HPMIXR_EN (0x1 << 2)
#define RK3026_HPMIXR_DIS (0x0 << 2)
#define RK3026_HPMIXR_INIT1 (0x0 << 1)
#define RK3026_HPMIXR_WORK1 (0x1 << 1)
#define RK3026_HPMIXR_INIT2 (0x0 << 0)
#define RK3026_HPMIXR_WORK2 (0x1 << 0)
/* HPMIXL Control (0xac) */
#define RK3026_HPMIXL_BYPASS_SFT (7)
#define RK3026_HPMIXL_SEL_ALCL_SFT (6)
#define RK3026_HPMIXL_SEL_ALCR_SFT (5)
#define RK3026_HPMIXL_SEL_DACL_SFT (4)
#define RK3026_HPMIXR_BYPASS_SFT (3)
#define RK3026_HPMIXR_SEL_ALCL_SFT (2)
#define RK3026_HPMIXR_SEL_ALCR_SFT (1)
#define RK3026_HPMIXR_SEL_DACR_SFT (0)
/* HPOUT Control (0xb0) */
#define RK3026_HPOUTL_PWR_SHT (7)
#define RK3026_HPOUTL_MSK (0x1 << 7)
#define RK3026_HPOUTL_EN (0x1 << 7)
#define RK3026_HPOUTL_DIS (0x0 << 7)
#define RK3026_HPOUTL_INIT_MSK (0x1 << 6)
#define RK3026_HPOUTL_INIT (0x0 << 6)
#define RK3026_HPOUTL_WORK (0x1 << 6)
#define RK3026_HPOUTL_MUTE_SHT (5)
#define RK3026_HPOUTL_MUTE_MSK (0x1 << 5)
#define RK3026_HPOUTL_MUTE_EN (0x0 << 5)
#define RK3026_HPOUTL_MUTE_DIS (0x1 << 5)
#define RK3026_HPOUTR_PWR_SHT (4)
#define RK3026_HPOUTR_MSK (0x1 << 4)
#define RK3026_HPOUTR_EN (0x1 << 4)
#define RK3026_HPOUTR_DIS (0x0 << 4)
#define RK3026_HPOUTR_INIT_MSK (0x1 << 3)
#define RK3026_HPOUTR_WORK (0x1 << 3)
#define RK3026_HPOUTR_INIT (0x0 << 3)
#define RK3026_HPOUTR_MUTE_SHT (2)
#define RK3026_HPOUTR_MUTE_MSK (0x1 << 2)
#define RK3026_HPOUTR_MUTE_EN (0x0 << 2)
#define RK3026_HPOUTR_MUTE_DIS (0x1 << 2)
#define RK3026_HPVREF_PWR_SHT (1)
#define RK3026_HPVREF_EN (0x1 << 1)
#define RK3026_HPVREF_DIS (0x0 << 1)
#define RK3026_HPVREF_WORK (0x1 << 0)
#define RK3026_HPVREF_INIT (0x0 << 0)
/* HPOUT GAIN (0xb4 0xb8) */
#define RK3026_HPOUT_GAIN_SFT (0)
/* SELECT CURR prechagrge/discharge (0xbc) */
#define RK3026_PRE_HPOUT (0x1 << 5)
#define RK3026_DIS_HPOUT (0x0 << 5)
#define RK3026_CUR_10UA_EN (0x0 << 4)
#define RK3026_CUR_10UA_DIS (0x1 << 4)
#define RK3026_CUR_I_EN (0x0 << 3)
#define RK3026_CUR_I_DIS (0x1 << 3)
#define RK3026_CUR_2I_EN (0x0 << 2)
#define RK3026_CUR_2I_DIS (0x1 << 2)
#define RK3026_CUR_4I_EN (0x0 << 0)
#define RK3026_CUR_4I_DIS (0x3 << 0)
/* PGA AGC control 1 (0xc0 0x100) */
#define RK3026_PGA_AGC_WAY_MASK (0x1 << 6)
#define RK3026_PGA_AGC_WAY_SFT 6
#define RK3026_PGA_AGC_WAY_JACK (0x1 << 6)
#define RK3026_PGA_AGC_WAY_NOR (0x0 << 6)
#define RK3026_PGA_AGC_BK_WAY_SFT 4
#define RK3026_PGA_AGC_BK_WAY_JACK1 (0x1 << 4)
#define RK3026_PGA_AGC_BK_WAY_NOR (0x0 << 4)
#define RK3026_PGA_AGC_BK_WAY_JACK2 (0x2 << 4)
#define RK3026_PGA_AGC_BK_WAY_JACK3 (0x3 << 4)
#define RK3026_PGA_AGC_HOLD_T_MASK 0xf
#define RK3026_PGA_AGC_HOLD_T_SFT 0
#define RK3026_PGA_AGC_HOLD_T_1024 0xa
#define RK3026_PGA_AGC_HOLD_T_512 0x9
#define RK3026_PGA_AGC_HOLD_T_256 0x8
#define RK3026_PGA_AGC_HOLD_T_128 0x7
#define RK3026_PGA_AGC_HOLD_T_64 0x6
#define RK3026_PGA_AGC_HOLD_T_32 0x5
#define RK3026_PGA_AGC_HOLD_T_16 0x4
#define RK3026_PGA_AGC_HOLD_T_8 0x3
#define RK3026_PGA_AGC_HOLD_T_4 0x2
#define RK3026_PGA_AGC_HOLD_T_2 0x1
#define RK3026_PGA_AGC_HOLD_T_0 0x0
/* PGA AGC control 2 (0xc4 0x104) */
#define RK3026_PGA_AGC_GRU_T_MASK (0xf << 4)
#define RK3026_PGA_AGC_GRU_T_SFT 4
#define RK3026_PGA_AGC_GRU_T_512 (0xa << 4)
#define RK3026_PGA_AGC_GRU_T_256 (0x9 << 4)
#define RK3026_PGA_AGC_GRU_T_128 (0x8 << 4)
#define RK3026_PGA_AGC_GRU_T_64 (0x7 << 4)
#define RK3026_PGA_AGC_GRU_T_32 (0x6 << 4)
#define RK3026_PGA_AGC_GRU_T_16 (0x5 << 4)
#define RK3026_PGA_AGC_GRU_T_8 (0x4 << 4)
#define RK3026_PGA_AGC_GRU_T_4 (0x3 << 4)
#define RK3026_PGA_AGC_GRU_T_2 (0x2 << 4)
#define RK3026_PGA_AGC_GRU_T_1 (0x1 << 4)
#define RK3026_PGA_AGC_GRU_T_0_5 (0x0 << 4)
#define RK3026_PGA_AGC_GRD_T_MASK 0xf
#define RK3026_PGA_AGC_GRD_T_SFT 0
#define RK3026_PGA_AGC_GRD_T_128_32 0xa
#define RK3026_PGA_AGC_GRD_T_64_16 0x9
#define RK3026_PGA_AGC_GRD_T_32_8 0x8
#define RK3026_PGA_AGC_GRD_T_16_4 0x7
#define RK3026_PGA_AGC_GRD_T_8_2 0x6
#define RK3026_PGA_AGC_GRD_T_4_1 0x5
#define RK3026_PGA_AGC_GRD_T_2_0_512 0x4
#define RK3026_PGA_AGC_GRD_T_1_0_256 0x3
#define RK3026_PGA_AGC_GRD_T_0_500_128 0x2
#define RK3026_PGA_AGC_GRD_T_0_250_64 0x1
#define RK3026_PGA_AGC_GRD_T_0_125_32 0x0
/* PGA AGC control 3 (0xc8 0x108) */
#define RK3026_PGA_AGC_MODE_MASK (0x1 << 7)
#define RK3026_PGA_AGC_MODE_SFT 7
#define RK3026_PGA_AGC_MODE_LIMIT (0x1 << 7)
#define RK3026_PGA_AGC_MODE_NOR (0x0 << 7)
#define RK3026_PGA_AGC_ZO_MASK (0x1 << 6)
#define RK3026_PGA_AGC_ZO_SFT 6
#define RK3026_PGA_AGC_ZO_EN (0x1 << 6)
#define RK3026_PGA_AGC_ZO_DIS (0x0 << 6)
#define RK3026_PGA_AGC_REC_MODE_MASK (0x1 << 5)
#define RK3026_PGA_AGC_REC_MODE_SFT 5
#define RK3026_PGA_AGC_REC_MODE_AC (0x1 << 5)
#define RK3026_PGA_AGC_REC_MODE_RN (0x0 << 5)
#define RK3026_PGA_AGC_FAST_D_MASK (0x1 << 4)
#define RK3026_PGA_AGC_FAST_D_SFT 4
#define RK3026_PGA_AGC_FAST_D_EN (0x1 << 4)
#define RK3026_PGA_AGC_FAST_D_DIS (0x0 << 4)
#define RK3026_PGA_AGC_NG_MASK (0x1 << 3)
#define RK3026_PGA_AGC_NG_SFT 3
#define RK3026_PGA_AGC_NG_EN (0x1 << 3)
#define RK3026_PGA_AGC_NG_DIS (0x0 << 3)
#define RK3026_PGA_AGC_NG_THR_MASK 0x7
#define RK3026_PGA_AGC_NG_THR_SFT 0
#define RK3026_PGA_AGC_NG_THR_N81DB 0x7
#define RK3026_PGA_AGC_NG_THR_N75DB 0x6
#define RK3026_PGA_AGC_NG_THR_N69DB 0x5
#define RK3026_PGA_AGC_NG_THR_N63DB 0x4
#define RK3026_PGA_AGC_NG_THR_N57DB 0x3
#define RK3026_PGA_AGC_NG_THR_N51DB 0x2
#define RK3026_PGA_AGC_NG_THR_N45DB 0x1
#define RK3026_PGA_AGC_NG_THR_N39DB 0x0
/* PGA AGC Control 4 (0xcc 0x10c) */
#define RK3026_PGA_AGC_ZO_MODE_MASK (0x1 << 5)
#define RK3026_PGA_AGC_ZO_MODE_SFT 5
#define RK3026_PGA_AGC_ZO_MODE_UWRC (0x1 << 5)
#define RK3026_PGA_AGC_ZO_MODE_UARC (0x0 << 5)
#define RK3026_PGA_AGC_VOL_MASK 0x1f
#define RK3026_PGA_AGC_VOL_SFT 0
/* PGA ASR Control (0xd0 0x110) */
#define RK3026_PGA_SLOW_CLK_MASK (0x1 << 3)
#define RK3026_PGA_SLOW_CLK_SFT 3
#define RK3026_PGA_SLOW_CLK_EN (0x1 << 3)
#define RK3026_PGA_SLOW_CLK_DIS (0x0 << 3)
#define RK3026_PGA_ASR_MASK 0x7
#define RK3026_PGA_ASR_SFT 0
#define RK3026_PGA_ASR_8KHz 0x7
#define RK3026_PGA_ASR_12KHz 0x6
#define RK3026_PGA_ASR_16KHz 0x5
#define RK3026_PGA_ASR_24KHz 0x4
#define RK3026_PGA_ASR_32KHz 0x3
#define RK3026_PGA_ASR_441KHz 0x2
#define RK3026_PGA_ASR_48KHz 0x1
#define RK3026_PGA_ASR_96KHz 0x0
/* PGA AGC Control 5 (0xe4 0x124) */
#define RK3026_PGA_AGC_MASK (0x1 << 6)
#define RK3026_PGA_AGC_SFT 6
#define RK3026_PGA_AGC_EN (0x1 << 6)
#define RK3026_PGA_AGC_DIS (0x0 << 6)
#define RK3026_PGA_AGC_MAX_G_MASK (0x7 << 3)
#define RK3026_PGA_AGC_MAX_G_SFT 3
#define RK3026_PGA_AGC_MAX_G_28_5DB (0x7 << 3)
#define RK3026_PGA_AGC_MAX_G_22_5DB (0x6 << 3)
#define RK3026_PGA_AGC_MAX_G_16_5DB (0x5 << 3)
#define RK3026_PGA_AGC_MAX_G_10_5DB (0x4 << 3)
#define RK3026_PGA_AGC_MAX_G_4_5DB (0x3 << 3)
#define RK3026_PGA_AGC_MAX_G_N1_5DB (0x2 << 3)
#define RK3026_PGA_AGC_MAX_G_N7_5DB (0x1 << 3)
#define RK3026_PGA_AGC_MAX_G_N13_5DB (0x0 << 3)
#define RK3026_PGA_AGC_MIN_G_MASK 0x7
#define RK3026_PGA_AGC_MIN_G_SFT 0
#define RK3026_PGA_AGC_MIN_G_24DB 0x7
#define RK3026_PGA_AGC_MIN_G_18DB 0x6
#define RK3026_PGA_AGC_MIN_G_12DB 0x5
#define RK3026_PGA_AGC_MIN_G_6DB 0x4
#define RK3026_PGA_AGC_MIN_G_0DB 0x3
#define RK3026_PGA_AGC_MIN_G_N6DB 0x2
#define RK3026_PGA_AGC_MIN_G_N12DB 0x1
#define RK3026_PGA_AGC_MIN_G_N18DB 0x0
enum {
RK3026_HIFI,
RK3026_VOICE,
};
enum {
RK3026_MONO = 1,
RK3026_STEREO,
};
enum {
OFF,
RCV,
SPK_PATH,
HP_PATH,
HP_NO_MIC,
BT,
SPK_HP,
RING_SPK,
RING_HP,
RING_HP_NO_MIC,
RING_SPK_HP,
};
enum {
MIC_OFF,
Main_Mic,
Hands_Free_Mic,
BT_Sco_Mic,
};
struct rk3026_reg_val_typ {
unsigned int reg;
unsigned int value;
};
struct rk3026_init_bit_typ {
unsigned int reg;
unsigned int power_bit;
unsigned int init2_bit;
unsigned int init1_bit;
unsigned int init0_bit;
};
struct rk3026_codec_pdata {
int spk_ctl_gpio;
int hp_ctl_gpio;
int delay_time;
};
#endif //__RK3026_CODEC_H__

1132
sound/soc/codecs/rk3036_codec.c
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160
sound/soc/codecs/rk3036_codec.h
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@@ -1,160 +0,0 @@
/*
*
* Copyright (C) 2014 rockchip
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _RK3036_CODEC_H
#define _RK3036_CODEC_H
/* codec register */
#define RK3036_CODEC_RESET (0x00 << 2)
#define RK3036_CODEC_REG03 (0x03 << 2)
#define RK3036_CODEC_REG04 (0x04 << 2)
#define RK3036_CODEC_REG05 (0x05 << 2)
#define RK3036_CODEC_REG22 (0x22 << 2)
#define RK3036_CODEC_REG23 (0x23 << 2)
#define RK3036_CODEC_REG24 (0x24 << 2)
#define RK3036_CODEC_REG25 (0x25 << 2)
#define RK3036_CODEC_REG26 (0x26 << 2)
#define RK3036_CODEC_REG27 (0x27 << 2)
#define RK3036_CODEC_REG28 (0x28 << 2)
/* RK3036_CODEC_RESET */
#define RK3036_CR00_DIGITAL_RESET (0 << 1)
#define RK3036_CR00_DIGITAL_WORK (1 << 1)
#define RK3036_CR00_SYSTEM_RESET (0 << 0)
#define RK3036_CR00_SYSTEM_WORK (1 << 0)
/*RK3036_CODEC_REG03*/
#define RK3036_CR03_DIRECTION_MASK (1 << 5)
#define RK3036_CR03_DIRECTION_IN (0 << 5)
#define RK3036_CR03_DIRECTION_IOUT (1 << 5)
#define RK3036_CR03_I2SMODE_MASK (1 << 4)
#define RK3036_CR03_I2SMODE_SLAVE (0 << 4)
#define RK3036_CR03_I2SMODE_MASTER (1 << 4)
/*RK3036_CODEC_REG04*/
#define RK3036_CR04_I2SLRC_MASK (1 << 7)
#define RK3036_CR04_I2SLRC_NORMAL (0 << 7)
#define RK3036_CR04_I2SLRC_REVERSAL (1 << 7)
#define RK3036_CR04_HFVALID_MASK (3 << 5)
#define RK3036_CR04_HFVALID_16BITS (0 << 5)
#define RK3036_CR04_HFVALID_20BITS (1 << 5)
#define RK3036_CR04_HFVALID_24BITS (2 << 5)
#define RK3036_CR04_HFVALID_32BITS (3 << 5)
#define RK3036_CR04_MODE_MASK (3 << 3)
#define RK3036_CR04_MODE_RIGHT (0 << 3)
#define RK3036_CR04_MODE_LEFT (1 << 3)
#define RK3036_CR04_MODE_I2S (2 << 3)
#define RK3036_CR04_MODE_PCM (3 << 3)
#define RK3036_CR04_LR_SWAP_MASK (1 << 2)
#define RK3036_CR04_LR_SWAP_DIS (0 << 2)
#define RK3036_CR04_LR_SWAP_EN (1 << 2)
/*RK3036_CODEC_REG05*/
#define RK3036_CR05_FRAMEH_MASK (3 << 2)
#define RK3036_CR05_FRAMEH_16BITS (0 << 2)
#define RK3036_CR05_FRAMEH_20BITS (1 << 2)
#define RK3036_CR05_FRAMEH_24BITS (2 << 2)
#define RK3036_CR05_FRAMEH_32BITS (3 << 2)
#define RK3036_CR05_DAC_RESET_MASK (1 << 1)
#define RK3036_CR05_DAC_RESET_EN (0 << 1)
#define RK3036_CR05_DAC_RESET_DIS (1 << 1)
#define RK3036_CR05_BCLKPOL_MASK (1 << 0)
#define RK3036_CR05_BCLKPOL_NORMAL (0 << 0)
#define RK3036_CR05_BCLKPOL_REVERSAL (1 << 0)
/*RK3036_CODEC_REG22*/
#define RK3036_CR22_DACL_PATH_REFV_MASK (1 << 5)
#define RK3036_CR22_DACL_PATH_REFV_STOP (0 << 5)
#define RK3036_CR22_DACL_PATH_REFV_WORK (1 << 5)
#define RK3036_CR22_DACR_PATH_REFV_MASK (1 << 4)
#define RK3036_CR22_DACR_PATH_REFV_STOP (0 << 4)
#define RK3036_CR22_DACR_PATH_REFV_WORK (1 << 4)
#define RK3036_CR22_DACL_CLK_STOP (0 << 3)
#define RK3036_CR22_DACL_CLK_WORK (1 << 3)
#define RK3036_CR22_DACR_CLK_STOP (0 << 2)
#define RK3036_CR22_DACR_CLK_WORK (1 << 2)
#define RK3036_CR22_DACL_STOP (0 << 1)
#define RK3036_CR22_DACL_WORK (1 << 1)
#define RK3036_CR22_DACR_STOP (0 << 0)
#define RK3036_CR22_DACR_WORK (1 << 0)
/*RK3036_CODEC_REG23*/
#define RK3036_CR23_HPOUTL_INIT (0 << 3)
#define RK3036_CR23_HPOUTL_WORK (1 << 3)
#define RK3036_CR23_HPOUTR_INIT (0 << 2)
#define RK3036_CR23_HPOUTR_WORK (1 << 2)
#define RK3036_CR23_HPOUTL_EN_STOP (0 << 1)
#define RK3036_CR23_HPOUTL_EN_WORK (1 << 1)
#define RK3036_CR23_HPOUTR_EN_STOP (0 << 0)
#define RK3036_CR23_HPOUTR_EN_WORK (1 << 0)
/*RK3036_CODEC_REG24*/
#define RK3036_CR24_DAC_SOURCE_STOP (0 << 5)
#define RK3036_CR24_DAC_SOURCE_WORK (1 << 5)
#define RK3036_CR24_DAC_PRECHARGE (0 << 4)
#define RK3036_CR24_DAC_DISCHARGE (1 << 4)
#define RK3036_CR24_DACL_REFV_STOP (0 << 3)
#define RK3036_CR24_DACL_REFV_WORK (1 << 3)
#define RK3036_CR24_DACR_REFV_STOP (0 << 2)
#define RK3036_CR24_DACR_REFV_WORK (1 << 2)
#define RK3036_CR24_VOUTL_ZEROD_STOP (0 << 1)
#define RK3036_CR24_VOUTL_ZEROD_WORK (1 << 1)
#define RK3036_CR24_VOUTR_ZEROD_STOP (0 << 0)
#define RK3036_CR24_VOUTR_ZEROD_WORK (1 << 0)
/*RK3036_CODEC_REG27*/
#define RK3036_CR27_DACL_INIT (0 << 7)
#define RK3036_CR27_DACL_WORK (1 << 7)
#define RK3036_CR27_DACR_INIT (0 << 6)
#define RK3036_CR27_DACR_WORK (1 << 6)
#define RK3036_CR27_HPOUTL_G_MUTE (0 << 5)
#define RK3036_CR27_HPOUTL_G_WORK (1 << 5)
#define RK3036_CR27_HPOUTR_G_MUTE (0 << 4)
#define RK3036_CR27_HPOUTR_G_WORK (1 << 4)
#define RK3036_CR27_HPOUTL_POP_PRECHARGE (1 << 2)
#define RK3036_CR27_HPOUTL_POP_WORK (2 << 2)
#define RK3036_CR27_HPOUTR_POP_PRECHARGE (1 << 0)
#define RK3036_CR27_HPOUTR_POP_WORK (2 << 0)
/*RK3036_CODEC_REG28*/
#define RK3036_CR28_YES_027I (0 << 5)
#define RK3036_CR28_NON_027I (1 << 5)
#define RK3036_CR28_YES_050I (0 << 4)
#define RK3036_CR28_NON_050I (1 << 4)
#define RK3036_CR28_YES_100I (0 << 3)
#define RK3036_CR28_NON_100I (1 << 3)
#define RK3036_CR28_YES_130I (0 << 2)
#define RK3036_CR28_NON_130I (1 << 2)
#define RK3036_CR28_YES_260I (0 << 1)
#define RK3036_CR28_NON_260I (1 << 1)
#define RK3036_CR28_YES_400I (0 << 0)
#define RK3036_CR28_NON_400I (1 << 0)
enum {
RK3036_HIFI,
RK3036_VOICE,
};
struct rk3036_reg_val_typ {
unsigned int reg;
unsigned int value;
};
struct rk3036_init_bit_typ {
unsigned int reg;
unsigned int power_bit;
unsigned int init2_bit;
unsigned int init1_bit;
unsigned int init0_bit;
};
#endif

2278
sound/soc/codecs/rk3190_codec.c
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591
sound/soc/codecs/rk3190_codec.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* rk3190_codec.h -- RK3190 CODEC ALSA SoC audio driver
*
* Copyright 2013 Rockship
* Author: zhangjun <showy.zhang@rock-chips.com>
*
*/
#ifndef __RK3190_CODEC_H__
#define __RK3190_CODEC_H__
/* codec register */
#define RK3190_CODEC_BASE (0x0)
#define RK3190_RESET (RK3190_CODEC_BASE + 0x00)
#define RK3190_ADC_INT_CTL1 (RK3190_CODEC_BASE + 0x08)
#define RK3190_ADC_INT_CTL2 (RK3190_CODEC_BASE + 0x0c)
#define RK3190_DAC_INT_CTL1 (RK3190_CODEC_BASE + 0x10)
#define RK3190_DAC_INT_CTL2 (RK3190_CODEC_BASE + 0x14)
//#define RK3190_DAC_INT_CTL3 (RK3190_CODEC_BASE + 0x18)
#define RK3190_BIST_CTL (RK3190_CODEC_BASE + 0x1c)
#define RK3190_SELECT_CURRENT (RK3190_CODEC_BASE + 0x88)
#define RK3190_BIAS_CTL (RK3190_CODEC_BASE + 0x8c)
#define RK3190_ADC_CTL (RK3190_CODEC_BASE + 0x90)
#define RK3190_BST_CTL (RK3190_CODEC_BASE + 0x94)
#define RK3190_ALC_MUNIN_CTL (RK3190_CODEC_BASE + 0x98)
#define RK3190_ALCL_GAIN_CTL (RK3190_CODEC_BASE + 0x9c)
#define RK3190_ALCR_GAIN_CTL (RK3190_CODEC_BASE + 0xa0)
#define RK3190_ADC_ENABLE (RK3190_CODEC_BASE + 0xa4)
#define RK3190_DAC_CTL (RK3190_CODEC_BASE + 0xa8)
#define RK3190_DAC_ENABLE (RK3190_CODEC_BASE + 0xac)
#define RK3190_HPMIX_CTL (RK3190_CODEC_BASE + 0xb0)
#define RK3190_HPMIX_S_SELECT (RK3190_CODEC_BASE + 0xb4)
#define RK3190_HPOUT_CTL (RK3190_CODEC_BASE + 0xb8)
#define RK3190_HPOUTL_GAIN (RK3190_CODEC_BASE + 0xbc)
#define RK3190_HPOUTR_GAIN (RK3190_CODEC_BASE + 0xc0)
#define RK3190_PGA_AGC_CTL1 (RK3190_CODEC_BASE + 0x100)
#define RK3190_PGA_AGC_CTL2 (RK3190_CODEC_BASE + 0x104)
#define RK3190_PGA_AGC_CTL3 (RK3190_CODEC_BASE + 0x108)
#define RK3190_PGA_AGC_CTL4 (RK3190_CODEC_BASE + 0x10c)
#define RK3190_PGA_ASR_CTL (RK3190_CODEC_BASE + 0x110)
#define RK3190_PGA_AGC_MAX_H (RK3190_CODEC_BASE + 0x114)
#define RK3190_PGA_AGC_MAX_L (RK3190_CODEC_BASE + 0x118)
#define RK3190_PGA_AGC_MIN_H (RK3190_CODEC_BASE + 0x11c)
#define RK3190_PGA_AGC_MIN_L (RK3190_CODEC_BASE + 0x120)
#define RK3190_PGA_AGC_CTL5 (RK3190_CODEC_BASE + 0x124)
#if 0
#define RK3190_PGAR_AGC_CTL1 (RK3190_CODEC_BASE + 0x140)
#define RK3190_PGAR_AGC_CTL2 (RK3190_CODEC_BASE + 0x144)
#define RK3190_PGAR_AGC_CTL3 (RK3190_CODEC_BASE + 0x148)
#define RK3190_PGAR_AGC_CTL4 (RK3190_CODEC_BASE + 0x14c)
#define RK3190_PGAR_ASR_CTL (RK3190_CODEC_BASE + 0x150)
#define RK3190_PGAR_AGC_MAX_H (RK3190_CODEC_BASE + 0x154)
#define RK3190_PGAR_AGC_MAX_L (RK3190_CODEC_BASE + 0x158)
#define RK3190_PGAR_AGC_MIN_H (RK3190_CODEC_BASE + 0x15c)
#define RK3190_PGAR_AGC_MIN_L (RK3190_CODEC_BASE + 0x160)
#define RK3190_PGAR_AGC_CTL5 (RK3190_CODEC_BASE + 0x164)
#endif
/* ADC Interface Control 1 (0x08) */
#define RK3190_ALRCK_POL_MASK (0x1 << 7)
#define RK3190_ALRCK_POL_SFT 7
#define RK3190_ALRCK_POL_EN (0x1 << 7)
#define RK3190_ALRCK_POL_DIS (0x0 << 7)
#define RK3190_ADC_VWL_MASK (0x3 << 5)
#define RK3190_ADC_VWL_SFT 5
#define RK3190_ADC_VWL_32 (0x3 << 5)
#define RK3190_ADC_VWL_24 (0x2 << 5)
#define RK3190_ADC_VWL_20 (0x1 << 5)
#define RK3190_ADC_VWL_16 (0x0 << 5)
#define RK3190_ADC_DF_MASK (0x3 << 3)
#define RK3190_ADC_DF_SFT 3
#define RK3190_ADC_DF_PCM (0x3 << 3)
#define RK3190_ADC_DF_I2S (0x2 << 3)
#define RK3190_ADC_DF_LJ (0x1 << 3)
#define RK3190_ADC_DF_RJ (0x0 << 3)
#define RK3190_ADC_SWAP_MASK (0x1 << 1)
#define RK3190_ADC_SWAP_SFT 1
#define RK3190_ADC_SWAP_EN (0x1 << 1)
#define RK3190_ADC_SWAP_DIS (0x0 << 1)
#define RK3190_ADC_TYPE_MASK 0x1
#define RK3190_ADC_TYPE_SFT 0
#define RK3190_ADC_TYPE_MONO 0x1
#define RK3190_ADC_TYPE_STEREO 0x0
/* ADC Interface Control 2 (0x0c) */
#define RK3190_I2S_MODE_MASK (0x1 << 4)
#define RK3190_I2S_MODE_SFT (4)
#define RK3190_I2S_MODE_MST (0x1 << 4)
#define RK3190_I2S_MODE_SLV (0x0 << 4)
#define RK3190_ADC_WL_MASK (0x3 << 2)
#define RK3190_ADC_WL_SFT (2)
#define RK3190_ADC_WL_32 (0x3 << 2)
#define RK3190_ADC_WL_24 (0x2 << 2)
#define RK3190_ADC_WL_20 (0x1 << 2)
#define RK3190_ADC_WL_16 (0x0 << 2)
#define RK3190_ADC_RST_MASK (0x1 << 1)
#define RK3190_ADC_RST_SFT 91)
#define RK3190_ADC_RST_DIS (0x1 << 1)
#define RK3190_ADC_RST_EN (0x0 << 1)
#define RK3190_ABCLK_POL_MASK 0x1
#define RK3190_ABCLK_POL_SFT 0
#define RK3190_ABCLK_POL_EN 0x1
#define RK3190_ABCLK_POL_DIS 0x0
/* DAC Interface Control 1 (0x10) */
#define RK3190_DLRCK_POL_MASK (0x1 << 7)
#define RK3190_DLRCK_POL_SFT 7
#define RK3190_DLRCK_POL_EN (0x1 << 7)
#define RK3190_DLRCK_POL_DIS (0x0 << 7)
#define RK3190_DAC_VWL_MASK (0x3 << 5)
#define RK3190_DAC_VWL_SFT 5
#define RK3190_DAC_VWL_32 (0x3 << 5)
#define RK3190_DAC_VWL_24 (0x2 << 5)
#define RK3190_DAC_VWL_20 (0x1 << 5)
#define RK3190_DAC_VWL_16 (0x0 << 5)
#define RK3190_DAC_DF_MASK (0x3 << 3)
#define RK3190_DAC_DF_SFT 3
#define RK3190_DAC_DF_PCM (0x3 << 3)
#define RK3190_DAC_DF_I2S (0x2 << 3)
#define RK3190_DAC_DF_LJ (0x1 << 3)
#define RK3190_DAC_DF_RJ (0x0 << 3)
#define RK3190_DAC_SWAP_MASK (0x1 << 2)
#define RK3190_DAC_SWAP_SFT 2
#define RK3190_DAC_SWAP_EN (0x1 << 2)
#define RK3190_DAC_SWAP_DIS (0x0 << 2)
/* DAC Interface Control 2 (0x14) */
#define RK3190_DAC_WL_MASK (0x3 << 2)
#define RK3190_DAC_WL_SFT 2
#define RK3190_DAC_WL_32 (0x3 << 2)
#define RK3190_DAC_WL_24 (0x2 << 2)
#define RK3190_DAC_WL_20 (0x1 << 2)
#define RK3190_DAC_WL_16 (0x0 << 2)
#define RK3190_DAC_RST_MASK (0x1 << 1)
#define RK3190_DAC_RST_SFT 1
#define RK3190_DAC_RST_DIS (0x1 << 1)
#define RK3190_DAC_RST_EN (0x0 << 1)
#define RK3190_DBCLK_POL_MASK 0x1
#define RK3190_DBCLK_POL_SFT 0
#define RK3190_DBCLK_POL_EN 0x1
#define RK3190_DBCLK_POL_DIS 0x0
/* BIST MODE SELECT (0x1c) */
/* SELECT CURR prechagrge/discharge (0x88) */
#define RK3190_PRE_HPOUT (0x1 << 5)
#define RK3190_DIS_HPOUT (0x0 << 5)
#define RK3190_CUR_10UA_EN (0x0 << 4)
#define RK3190_CUR_10UA_DIS (0x1 << 4)
#define RK3190_CUR_I_EN (0x0 << 3)
#define RK3190_CUR_I_DIS (0x1 << 3)
#define RK3190_CUR_2I_EN (0x0 << 2)
#define RK3190_CUR_2I_DIS (0x1 << 2)
#define RK3190_CUR_4I_EN (0x0 << 0)
#define RK3190_CUR_4I_DIS (0x3 << 0)
/* MICBIAS (0x8c) */
#define RK3190_MICBIAS_VOL_ENABLE (3)
#define RK3190_MICBIAS_VOL_SHT 0
#define RK3190_MICBIAS_VOL_MSK 7
#define RK3190_MICBIAS_VOL_MIN (0x0 << 0)
#define RK3190_MICBIAS_VOL_MAX (0x7 << 0)
/* ADC control (0x90) */
#define RK3190_ADC_CURRENT_ENABLE (0x1 << 6)
#define RK3190_ADC_CURRENT_DISABLE (0x0 << 6)
#define RK3190_ADCL_REF_VOL_EN_SFT (5)
#define RK3190_ADCL_REF_VOL_EN (0x1 << 5)
#define RK3190_ADCL_REF_VOL_DIS (0x0 << 5)
#define RK3190_ADCL_ZERO_DET_EN_SFT (4)
#define RK3190_ADCL_ZERO_DET_EN (0x1 << 4)
#define RK3190_ADCL_ZERO_DET_DIS (0x0 << 4)
#define RK3190_ADCR_REF_VOL_EN_SFT (1)
#define RK3190_ADCR_REF_VOL_EN (0x1 << 1)
#define RK3190_ADCR_REF_VOL_DIS (0x0 << 1)
#define RK3190_ADCR_ZERO_DET_EN_SFT (0)
#define RK3190_ADCR_ZERO_DET_EN (0x1 << 0)
#define RK3190_ADCR_ZERO_DET_DIS (0x0 << 0)
/* BST_L BST_R CONTROL (0x94) */
#define RK3190_BSTL_PWRD_SFT (7)
#define RK3190_BSTL_EN (0x1 << 7)
#define RK3190_BSTL_DIS (0x0 << 7)
#define RK3190_BSTL_GAIN_SHT (6)
#define RK3190_BSTL_GAIN_20 (0x1 << 6)
#define RK3190_BSTL_GAIN_0 (0x0 << 6)
#define RK3190_BSTL_MUTE_SHT (5)
#define RK3190_BSTL_MODE_SFT (4)
#define RK3190_BSTL_MODE_SINGLE (0x1 << 4)
#define RK3190_BSTL_MODE_DIFF (0x0 << 4)
#define RK3190_BSTR_PWRD_SFT (3)
#define RK3190_BSTR_EN (0x1 << 3)
#define RK3190_BSTR_DIS (0x0 << 3)
#define RK3190_BSTR_GAIN_SHT (2)
#define RK3190_BSTR_GAIN_20 (0x1 << 2)
#define RK3190_BSTR_GAIN_0 (0x0 << 2)
#define RK3190_BSTR_MUTE_SHT (1)
/* MUXINL ALCL MUXINR ALCR (0x98) */
#define RK3190_MUXINL_BSTL_SHT (7)
#define RK3190_MUXINL_BSTL_EN (0x0 << 7)
#define RK3190_MUXINL_BSTL_DIS (0x1 << 7)
#define RK3190_MUXINL_INL_SHT (6)
#define RK3190_MUXINL_INL_EN (0x0 << 6)
#define RK3190_MUXINL_INL_DIS (0x1 << 6)
#define RK3190_ALCL_PWR_SHT (5)
#define RK3190_ALCL_EN (0x1 << 5)
#define RK3190_ALCL_DIS (0x0 << 5)
#define RK3190_ALCL_MUTE_SHT (4)
#define RK3190_MUXINR_BSTR_SHT (3)
#define RK3190_MUXINR_BSTR_EN (0x0 << 3)
#define RK3190_MUXINR_BSTR_DIS (0x1 << 3)
#define RK3190_MUXINR_INR_SHT (2)
#define RK3190_MUXINR_INR_EN (0x0 << 2)
#define RK3190_MUXINR_INR_DIS (0x1 << 2)
#define RK3190_ALCR_PWR_SHT (1)
#define RK3190_ALCR_EN (0x1 << 1)
#define RK3190_ALCR_DIS (0x0 << 1)
#define RK3190_ALCR_MUTE_SHT (0)
/* ALC_L GAIN (0x9c) */
#define RK3190_ALCL_GAIN_SHT (0)
#define RK3190_ALCL_GAIN_MSK (0x1f)
/* ALC_R GAIN (0xa0) */
#define RK3190_ALCR_GAIN_SHT (0)
#define RK3190_ALCR_GAIN_MSK (0x1f)
/* ADC ENABLE (0xa4) */
#define RK3190_ADCL_CLK_EN_SFT (6)
#define RK3190_ADCL_CLK_EN (0x1 << 6)
#define RK3190_ADCL_CLK_DIS (0x0 << 6)
#define RK3190_ADCL_AMP_EN_SFT (5)
#define RK3190_ADCL_AMP_EN (0x1 << 5)
#define RK3190_ADCL_AMP_DIS (0x0 << 5)
#define RK3190_ADCL_RST_EN (0x1 << 4)
#define RK3190_ADCL_RST_DIS (0x0 << 4)
#define RK3190_ADCR_CLK_EN_SFT (2)
#define RK3190_ADCR_CLK_EN (0x1 << 2)
#define RK3190_ADCR_CLK_DIS (0x0 << 2)
#define RK3190_ADCR_AMP_EN_SFT (1)
#define RK3190_ADCR_AMP_EN (0x1 << 1)
#define RK3190_ADCR_AMP_DIS (0x0 << 1)
#define RK3190_ADCR_RST_EN (0x1 << 0)
#define RK3190_ADCR_RST_DIS (0x0 << 0)
/* DAC & VOUT Control (0xa8) */
#define RK3190_CURRENT_EN (0x1 << 6)
#define RK3190_CURRENT_DIS (0x0 << 6)
#define RK3190_REF_VOL_DACL_EN_SFT (5)
#define RK3190_REF_VOL_DACL_EN (0x1 << 5)
#define RK3190_REF_VOL_DACL_DIS (0x0 << 5)
#define RK3190_ZO_DET_VOUTL_SFT (4)
#define RK3190_ZO_DET_VOUTL_EN (0x1 << 4)
#define RK3190_ZO_DET_VOUTL_DIS (0x0 << 4)
#define RK3190_DET_ERAPHONE_DIS (0x0 << 3)
#define RK3190_DET_ERAPHONE_EN (0x1 << 3)
#define RK3190_REF_VOL_DACR_EN_SFT (1)
#define RK3190_REF_VOL_DACR_EN (0x1 << 1)
#define RK3190_REF_VOL_DACR_DIS (0x0 << 1)
#define RK3190_ZO_DET_VOUTR_SFT (0)
#define RK3190_ZO_DET_VOUTR_EN (0x1 << 0)
#define RK3190_ZO_DET_VOUTR_DIS (0x0 << 0)
/* DAC control (0xac) */
#define RK3190_DACL_REF_VOL_EN_SFT (7)
#define RK3190_DACL_REF_VOL_EN (0x1 << 7)
#define RK3190_DACL_REF_VOL_DIS (0x0 << 7)
#define RK3190_DACL_CLK_EN (0x1 << 6)
#define RK3190_DACL_CLK_DIS (0x0 << 6)
#define RK3190_DACL_EN (0x1 << 5)
#define RK3190_DACL_DIS (0x0 << 5)
#define RK3190_DACL_INIT (0x0 << 4)
#define RK3190_DACL_WORK (0x1 << 4)
#define RK3190_DACR_REF_VOL_EN_SFT (3)
#define RK3190_DACR_REF_VOL_EN (0x1 << 3)
#define RK3190_DACR_REF_VOL_DIS (0x0 << 3)
#define RK3190_DACR_CLK_EN (0x1 << 2)
#define RK3190_DACR_CLK_DIS (0x0 << 2)
#define RK3190_DACR_EN (0x1 << 1)
#define RK3190_DACR_DIS (0x0 << 1)
#define RK3190_DACR_INIT (0x0 << 0)
#define RK3190_DACR_WORK (0x1 << 0)
/* HPMIXL HPMIXR Control (0xb0) */
#define RK3190_HPMIXL_SFT (6)
#define RK3190_HPMIXL_EN (0x1 << 6)
#define RK3190_HPMIXL_DIS (0x0 << 6)
#define RK3190_HPMIXL_INIT1 (0x0 << 5)
#define RK3190_HPMIXL_WORK1 (0x1 << 5)
#define RK3190_HPMIXL_INIT2 (0x0 << 4)
#define RK3190_HPMIXL_WORK2 (0x1 << 4)
#define RK3190_HPMIXR_SFT (2)
#define RK3190_HPMIXR_EN (0x1 << 2)
#define RK3190_HPMIXR_DIS (0x0 << 2)
#define RK3190_HPMIXR_INIT1 (0x0 << 1)
#define RK3190_HPMIXR_WORK1 (0x1 << 1)
#define RK3190_HPMIXR_INIT2 (0x0 << 0)
#define RK3190_HPMIXR_WORK2 (0x1 << 0)
/* HPMIXL Control (0xb4) */
#define RK3190_HPMIXL_BYPASS_SFT (7)
#define RK3190_HPMIXL_SEL_ALCL_SFT (6)
#define RK3190_HPMIXL_SEL_ALCR_SFT (5)
#define RK3190_HPMIXL_SEL_DACL_SFT (4)
#define RK3190_HPMIXR_BYPASS_SFT (3)
#define RK3190_HPMIXR_SEL_ALCL_SFT (2)
#define RK3190_HPMIXR_SEL_ALCR_SFT (1)
#define RK3190_HPMIXR_SEL_DACR_SFT (0)
/* HPOUT Control (0xb8) */
#define RK3190_HPOUTL_PWR_SHT (7)
#define RK3190_HPOUTL_MSK (0x1 << 7)
#define RK3190_HPOUTL_EN (0x1 << 7)
#define RK3190_HPOUTL_DIS (0x0 << 7)
#define RK3190_HPOUTL_INIT_MSK (0x1 << 6)
#define RK3190_HPOUTL_INIT (0x0 << 6)
#define RK3190_HPOUTL_WORK (0x1 << 6)
#define RK3190_HPOUTL_MUTE_SHT (5)
#define RK3190_HPOUTL_MUTE_MSK (0x1 << 5)
#define RK3190_HPOUTL_MUTE_EN (0x0 << 5)
#define RK3190_HPOUTL_MUTE_DIS (0x1 << 5)
#define RK3190_HPOUTR_PWR_SHT (4)
#define RK3190_HPOUTR_MSK (0x1 << 4)
#define RK3190_HPOUTR_EN (0x1 << 4)
#define RK3190_HPOUTR_DIS (0x0 << 4)
#define RK3190_HPOUTR_INIT_MSK (0x1 << 3)
#define RK3190_HPOUTR_WORK (0x1 << 3)
#define RK3190_HPOUTR_INIT (0x0 << 3)
#define RK3190_HPOUTR_MUTE_SHT (2)
#define RK3190_HPOUTR_MUTE_MSK (0x1 << 2)
#define RK3190_HPOUTR_MUTE_EN (0x0 << 2)
#define RK3190_HPOUTR_MUTE_DIS (0x1 << 2)
#define RK3190_HPVREF_PWR_SHT (1)
#define RK3190_HPVREF_EN (0x1 << 1)
#define RK3190_HPVREF_DIS (0x0 << 1)
#define RK3190_HPVREF_WORK (0x1 << 0)
#define RK3190_HPVREF_INIT (0x0 << 0)
/* HPOUT GAIN (0xbc 0xc0) */
#define RK3190_HPOUT_GAIN_SFT (0)
/* SELECT CURR prechagrge/discharge (0xbc) */
#define RK3190_PRE_HPOUT (0x1 << 5)
#define RK3190_DIS_HPOUT (0x0 << 5)
#define RK3190_CUR_10UA_EN (0x0 << 4)
#define RK3190_CUR_10UA_DIS (0x1 << 4)
#define RK3190_CUR_I_EN (0x0 << 3)
#define RK3190_CUR_I_DIS (0x1 << 3)
#define RK3190_CUR_2I_EN (0x0 << 2)
#define RK3190_CUR_2I_DIS (0x1 << 2)
#define RK3190_CUR_4I_EN (0x0 << 0)
#define RK3190_CUR_4I_DIS (0x3 << 0)
/* PGA AGC control 1 (0x100) */
#define RK3190_PGA_AGC_WAY_MASK (0x1 << 6)
#define RK3190_PGA_AGC_WAY_SFT 6
#define RK3190_PGA_AGC_WAY_JACK (0x1 << 6)
#define RK3190_PGA_AGC_WAY_NOR (0x0 << 6)
#define RK3190_PGA_AGC_BK_WAY_SFT 4
#define RK3190_PGA_AGC_BK_WAY_JACK1 (0x1 << 4)
#define RK3190_PGA_AGC_BK_WAY_NOR (0x0 << 4)
#define RK3190_PGA_AGC_BK_WAY_JACK2 (0x2 << 4)
#define RK3190_PGA_AGC_BK_WAY_JACK3 (0x3 << 4)
#define RK3190_PGA_AGC_HOLD_T_MASK 0xf
#define RK3190_PGA_AGC_HOLD_T_SFT 0
#define RK3190_PGA_AGC_HOLD_T_1024 0xa
#define RK3190_PGA_AGC_HOLD_T_512 0x9
#define RK3190_PGA_AGC_HOLD_T_256 0x8
#define RK3190_PGA_AGC_HOLD_T_128 0x7
#define RK3190_PGA_AGC_HOLD_T_64 0x6
#define RK3190_PGA_AGC_HOLD_T_32 0x5
#define RK3190_PGA_AGC_HOLD_T_16 0x4
#define RK3190_PGA_AGC_HOLD_T_8 0x3
#define RK3190_PGA_AGC_HOLD_T_4 0x2
#define RK3190_PGA_AGC_HOLD_T_2 0x1
#define RK3190_PGA_AGC_HOLD_T_0 0x0
/* PGA AGC control 2 (0x104) */
#define RK3190_PGA_AGC_GRU_T_MASK (0xf << 4)
#define RK3190_PGA_AGC_GRU_T_SFT 4
#define RK3190_PGA_AGC_GRU_T_512 (0xa << 4)
#define RK3190_PGA_AGC_GRU_T_256 (0x9 << 4)
#define RK3190_PGA_AGC_GRU_T_128 (0x8 << 4)
#define RK3190_PGA_AGC_GRU_T_64 (0x7 << 4)
#define RK3190_PGA_AGC_GRU_T_32 (0x6 << 4)
#define RK3190_PGA_AGC_GRU_T_16 (0x5 << 4)
#define RK3190_PGA_AGC_GRU_T_8 (0x4 << 4)
#define RK3190_PGA_AGC_GRU_T_4 (0x3 << 4)
#define RK3190_PGA_AGC_GRU_T_2 (0x2 << 4)
#define RK3190_PGA_AGC_GRU_T_1 (0x1 << 4)
#define RK3190_PGA_AGC_GRU_T_0_5 (0x0 << 4)
#define RK3190_PGA_AGC_GRD_T_MASK 0xf
#define RK3190_PGA_AGC_GRD_T_SFT 0
#define RK3190_PGA_AGC_GRD_T_128_32 0xa
#define RK3190_PGA_AGC_GRD_T_64_16 0x9
#define RK3190_PGA_AGC_GRD_T_32_8 0x8
#define RK3190_PGA_AGC_GRD_T_16_4 0x7
#define RK3190_PGA_AGC_GRD_T_8_2 0x6
#define RK3190_PGA_AGC_GRD_T_4_1 0x5
#define RK3190_PGA_AGC_GRD_T_2_0_512 0x4
#define RK3190_PGA_AGC_GRD_T_1_0_256 0x3
#define RK3190_PGA_AGC_GRD_T_0_500_128 0x2
#define RK3190_PGA_AGC_GRD_T_0_250_64 0x1
#define RK3190_PGA_AGC_GRD_T_0_125_32 0x0
/* PGA AGC control 3 (0x108) */
#define RK3190_PGA_AGC_MODE_MASK (0x1 << 7)
#define RK3190_PGA_AGC_MODE_SFT 7
#define RK3190_PGA_AGC_MODE_LIMIT (0x1 << 7)
#define RK3190_PGA_AGC_MODE_NOR (0x0 << 7)
#define RK3190_PGA_AGC_ZO_MASK (0x1 << 6)
#define RK3190_PGA_AGC_ZO_SFT 6
#define RK3190_PGA_AGC_ZO_EN (0x1 << 6)
#define RK3190_PGA_AGC_ZO_DIS (0x0 << 6)
#define RK3190_PGA_AGC_REC_MODE_MASK (0x1 << 5)
#define RK3190_PGA_AGC_REC_MODE_SFT 5
#define RK3190_PGA_AGC_REC_MODE_AC (0x1 << 5)
#define RK3190_PGA_AGC_REC_MODE_RN (0x0 << 5)
#define RK3190_PGA_AGC_FAST_D_MASK (0x1 << 4)
#define RK3190_PGA_AGC_FAST_D_SFT 4
#define RK3190_PGA_AGC_FAST_D_EN (0x1 << 4)
#define RK3190_PGA_AGC_FAST_D_DIS (0x0 << 4)
#define RK3190_PGA_AGC_NG_MASK (0x1 << 3)
#define RK3190_PGA_AGC_NG_SFT 3
#define RK3190_PGA_AGC_NG_EN (0x1 << 3)
#define RK3190_PGA_AGC_NG_DIS (0x0 << 3)
#define RK3190_PGA_AGC_NG_THR_MASK 0x7
#define RK3190_PGA_AGC_NG_THR_SFT 0
#define RK3190_PGA_AGC_NG_THR_N81DB 0x7
#define RK3190_PGA_AGC_NG_THR_N75DB 0x6
#define RK3190_PGA_AGC_NG_THR_N69DB 0x5
#define RK3190_PGA_AGC_NG_THR_N63DB 0x4
#define RK3190_PGA_AGC_NG_THR_N57DB 0x3
#define RK3190_PGA_AGC_NG_THR_N51DB 0x2
#define RK3190_PGA_AGC_NG_THR_N45DB 0x1
#define RK3190_PGA_AGC_NG_THR_N39DB 0x0
/* PGA AGC Control 4 (0x10c) */
#define RK3190_PGA_AGC_ZO_MODE_MASK (0x1 << 5)
#define RK3190_PGA_AGC_ZO_MODE_SFT 5
#define RK3190_PGA_AGC_ZO_MODE_UWRC (0x1 << 5)
#define RK3190_PGA_AGC_ZO_MODE_UARC (0x0 << 5)
#define RK3190_PGA_AGC_VOL_MASK 0x1f
#define RK3190_PGA_AGC_VOL_SFT 0
/* PGA ASR Control (0x110) */
#define RK3190_PGA_SLOW_CLK_MASK (0x1 << 3)
#define RK3190_PGA_SLOW_CLK_SFT 3
#define RK3190_PGA_SLOW_CLK_EN (0x1 << 3)
#define RK3190_PGA_SLOW_CLK_DIS (0x0 << 3)
#define RK3190_PGA_ASR_MASK 0x7
#define RK3190_PGA_ASR_SFT 0
#define RK3190_PGA_ASR_8KHz 0x7
#define RK3190_PGA_ASR_12KHz 0x6
#define RK3190_PGA_ASR_16KHz 0x5
#define RK3190_PGA_ASR_24KHz 0x4
#define RK3190_PGA_ASR_32KHz 0x3
#define RK3190_PGA_ASR_441KHz 0x2
#define RK3190_PGA_ASR_48KHz 0x1
#define RK3190_PGA_ASR_96KHz 0x0
/* PGA AGC Control 5 (0x124) */
#define RK3190_PGA_AGC_MASK (0x1 << 6)
#define RK3190_PGA_AGC_SFT 6
#define RK3190_PGA_AGC_EN (0x1 << 6)
#define RK3190_PGA_AGC_DIS (0x0 << 6)
#define RK3190_PGA_AGC_MAX_G_MASK (0x7 << 3)
#define RK3190_PGA_AGC_MAX_G_SFT 3
#define RK3190_PGA_AGC_MAX_G_28_5DB (0x7 << 3)
#define RK3190_PGA_AGC_MAX_G_22_5DB (0x6 << 3)
#define RK3190_PGA_AGC_MAX_G_16_5DB (0x5 << 3)
#define RK3190_PGA_AGC_MAX_G_10_5DB (0x4 << 3)
#define RK3190_PGA_AGC_MAX_G_4_5DB (0x3 << 3)
#define RK3190_PGA_AGC_MAX_G_N1_5DB (0x2 << 3)
#define RK3190_PGA_AGC_MAX_G_N7_5DB (0x1 << 3)
#define RK3190_PGA_AGC_MAX_G_N13_5DB (0x0 << 3)
#define RK3190_PGA_AGC_MIN_G_MASK 0x7
#define RK3190_PGA_AGC_MIN_G_SFT 0
#define RK3190_PGA_AGC_MIN_G_24DB 0x7
#define RK3190_PGA_AGC_MIN_G_18DB 0x6
#define RK3190_PGA_AGC_MIN_G_12DB 0x5
#define RK3190_PGA_AGC_MIN_G_6DB 0x4
#define RK3190_PGA_AGC_MIN_G_0DB 0x3
#define RK3190_PGA_AGC_MIN_G_N6DB 0x2
#define RK3190_PGA_AGC_MIN_G_N12DB 0x1
#define RK3190_PGA_AGC_MIN_G_N18DB 0x0
enum {
RK3190_HIFI,
RK3190_VOICE,
};
enum {
RK3190_MONO = 1,
RK3190_STEREO,
};
enum {
OFF,
RCV,
SPK_PATH,
HP_PATH,
HP_NO_MIC,
BT,
SPK_HP,
RING_SPK,
RING_HP,
RING_HP_NO_MIC,
RING_SPK_HP,
};
enum {
MIC_OFF,
Main_Mic,
Hands_Free_Mic,
BT_Sco_Mic,
};
struct rk3190_reg_val_typ {
unsigned int reg;
unsigned int value;
};
struct rk3190_init_bit_typ {
unsigned int reg;
unsigned int power_bit;
unsigned int init2_bit;
unsigned int init1_bit;
unsigned int init0_bit;
};
struct rk3190_codec_pdata {
int spk_ctl_gpio;
int hp_ctl_gpio;
int ear_ctl_gpio;
int delay_time;
};
#endif //__RK3190_CODEC_H__

1111
sound/soc/codecs/rk610_codec.c
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268
sound/soc/codecs/rk610_codec.h
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/*
*
* Copyright (C) 2009 rockchip lhh
*
* Based on WM8750.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _RK610_CODEC_H
#define _RK610_CODEC_H
/* RK610 register space */
#define ACCELCODEC_R00 0x00 //ADC High Pass Filter / DSM
#define ACCELCODEC_R01 0x01 //DITHER power
#define ACCELCODEC_R02 0x02 //DITHER power
#define ACCELCODEC_R03 0x03 //DITHER power
#define ACCELCODEC_R04 0x04 //Soft mute / sidetone gain control
#define ACCELCODEC_R05 0x05 //Right interpolate filter volume control (MSB)
#define ACCELCODEC_R06 0x06 //Right interpolate filter volume control (LSB)
#define ACCELCODEC_R07 0x07 //Left interpolate filter volume control (MSB)
#define ACCELCODEC_R08 0x08 //Left interpolate filter volume control (LSB)
#define ACCELCODEC_R09 0x09 //Audio interface control
#define ACCELCODEC_R0A 0x0A //Sample Rate / CLK control
#define ACCELCODEC_R0B 0x0B //Decimation filter / Interpolate filter enable
#define ACCELCODEC_R0C 0x0C //LIN volume
#define ACCELCODEC_R0D 0x0D //LIP volume
#define ACCELCODEC_R0E 0x0E //AL volume
//#define ACCELCODEC_R0F 0x0F //RIN volume
//#define ACCELCODEC_R10 0x10 //RIP volume
//#define ACCELCODEC_R11 0x11 //AR volume
#define ACCELCODEC_R12 0x12 //Input volume
#define ACCELCODEC_R13 0x13 //Left out mix
#define ACCELCODEC_R14 0x14 //Right out mix
#define ACCELCODEC_R15 0x15 //LPF out mix / SCF
#define ACCELCODEC_R16 0x16 //SCF control
#define ACCELCODEC_R17 0x17 //LOUT (AOL) volume
#define ACCELCODEC_R18 0x18 //ROUT (AOR) volume
#define ACCELCODEC_R19 0x19 //MONOOUT (AOM) volume
#define ACCELCODEC_R1A 0x1A //MONOOUT / Reference control
#define ACCELCODEC_R1B 0x1B //Bias Current control
#define ACCELCODEC_R1C 0x1C //ADC control
#define ACCELCODEC_R1D 0x1D //Power Mrg 1
#define ACCELCODEC_R1E 0x1E //Power Mrg 2
#define ACCELCODEC_R1F 0x1F //Power Mrg 3
#define RK610_CACHE_REGNUM 0x1F
//ACCELCODEC_R00
#define ASC_HPF_ENABLE (0x1) //high_pass filter
#define ASC_HPF_DISABLE (0x0)
#define ASC_DSM_MODE_ENABLE (0x1 << 1)
#define ASC_DSM_MODE_DISABLE (0x0 << 1)
#define ASC_SCRAMBLE_ENABLE (0x1 << 2)
#define ASC_SCRAMBLE_DISABLE (0x0 << 2)
#define ASC_DITHER_ENABLE (0x1 << 3)
#define ASC_DITHER_DISABLE (0x0 << 3)
#define ASC_BCLKDIV_4 (0x1 << 4)
#define ASC_BCLKDIV_8 (0x2 << 4)
#define ASC_BCLKDIV_16 (0x3 << 4)
//ACCECODEC_R04
#define ASC_INT_MUTE_L (0x1)
#define ASC_INT_ACTIVE_L (0x0)
#define ASC_INT_MUTE_R (0x1 << 1)
#define ASC_INT_ACTIVE_R (0x0 << 1)
#define ASC_SIDETONE_L_OFF (0x0 << 2)
#define ASC_SIDETONE_L_GAIN_MAX (0x1 << 2)
#define ASC_SIDETONE_R_OFF (0x0 << 5)
#define ASC_SIDETONE_R_GAIN_MAX (0x1 << 5)
//ACCELCODEC_R05
#define ASC_INT_VOL_0DB (0x0)
//ACCELCODEC_R09
#define ASC_DSP_MODE (0x3)
#define ASC_I2S_MODE (0x2)
#define ASC_LEFT_MODE (0x1)
//#define ASC_RIGHT_MODE (0x0)
#define ASC_32BIT_MODE (0x3 << 2)
#define ASC_24BIT_MODE (0x2 << 2)
#define ASC_20BIT_MODE (0x1 << 2)
#define ASC_16BIT_MODE (0x0 << 2)
#define ASC_INVERT_LRCLK (0x1 << 4)
#define ASC_NORMAL_LRCLK (0x0 << 4)
#define ASC_LRSWAP_ENABLE (0x1 << 5)
#define ASC_LRSWAP_DISABLE (0x0 << 5)
#define ASC_MASTER_MODE (0x1 << 6)
#define ASC_SLAVE_MODE (0x0 << 6)
#define ASC_INVERT_BCLK (0x1 << 7)
#define ASC_NORMAL_BCLK (0x0 << 7)
//ACCELCODEC_R0A
#define ASC_USB_MODE (0x1)
#define ASC_NORMAL_MODE (0x0)
#define FREQ96kHz (0x0e << 1)
#define FREQ48kHz (0x00 << 1)
#define FREQ441kHz (0x11 << 1)
#define FREQ32kHz (0x0c << 1)
#define FREQ24kHz (0x1c << 1)
#define FREQ2205kHz (0x1B << 1)
#define FREQ16kHz (0x0a << 1)
#define FREQ12kHz (0x08 << 1)
#define FREQ11025kHz (0x19 << 1)
//#define FREQ9k6Hz 0x09
#define FREQ8kHz (0x06<<1)
#define ASC_CLKDIV2 (0x1 << 6)
#define ASC_CLKNODIV (0x0 << 6)
#define ASC_CLK_ENABLE (0x1 << 7)
#define ASC_CLK_DISABLE (0x0 << 7)
//ACCELCODEC_R0B
#define ASC_DEC_ENABLE (0x1) //decimation filter enable
#define ASC_DEC_DISABLE (0x0)
#define ASC_INT_ENABLE (0x1 << 1) //interpolate filter enable
#define ASC_INT_DISABLE (0x0 << 1)
//Input ACCELCODEC_R0E
#define ASC_INPUT_MUTE (0x1 << 7)
#define ASC_INPUT_ACTIVE (0x0 << 7)
#define ASC_INPUT_VOL_0DB (0x0)
//ACCELCODEC_R12
#define ASC_LINE_INPUT (0)
#define ASC_MIC_INPUT (1 << 7)
#define ASC_MIC_BOOST_0DB (0)
#define ASC_MIC_BOOST_20DB (1 << 5)
//ACCELCODEC_R13
#define ASC_LPGAMXVOL_0DB (0x5)
#define ASC_LPGAMX_ENABLE (0x1 << 3) //the left channel PGA output is directly fed into the left mixer
#define ASC_LPGAMX_DISABLE (0x0 << 3)
#define ASC_ALMXVOL_0DB (0x5 << 4)
#define ASC_ALMX_ENABLE (0x1 << 7) //the left second line input is directly fed into the left mixer
#define ASC_ALMX_DISABLE (0x0 << 7)
//ACCELCODEC_R14
#define ASC_RPGAMXVOL_0DB (0x5)
#define ASC_RPGAMX_ENABLE (0x1 << 3) //the right channel PGA output is directly fed into the right mixer
#define ASC_RPGAMX_DISABLE (0x0 << 3)
#define ASC_ARMXVOL_0DB (0x5 << 4)
#define ASC_ARMX_ENABLE (0x1 << 7) //)the right second line input is directly fed into the right mixer
#define ASC_ARMX_DISABLE (0x0 << 7)
//ACCELCODEC_R15
#define ASC_LDAMX_ENABLE (0x1 << 2) //the left differential signal from DAC is directly fed into the left mixer
#define ASC_LDAMX_DISABLE (0x0 << 2)
#define ASC_RDAMX_ENABLE (0x1 << 3) //the right differential signal from DAC is directly fed into the right mixer
#define ASC_RDAMX_DISABLE (0x0 << 3)
#define ASC_LSCF_MUTE (0x1 << 4) //the left channel LPF is mute
#define ASC_LSCF_ACTIVE (0x0 << 4)
#define ASC_RSCF_MUTE (0x1 << 5) //the right channel LPF is mute
#define ASC_RSCF_ACTIVE (0x0 << 5)
#define ASC_LLPFMX_ENABLE (0x1 << 6) //the left channel LPF output is fed into the left into the mixer
#define ASC_LLPFMX_DISABLE (0x0 << 6)
#define ASC_RLPFMX_ENABLE (0x1 << 7) //the right channel LPF output is fed into the right into the mixer.
#define ASC_RLPFMX_DISABLE (0x0 << 7)
//ACCELCODEC_R17/R18
#define ASC_OUTPUT_MUTE (0x1 << 6)
#define ASC_OUTPUT_ACTIVE (0x0 << 6)
#define ASC_CROSSZERO_EN (0x1 << 7)
#define ASC_OUTPUT_VOL_0DB (0x0F)
//ACCELCODEC_R19
#define ASC_MONO_OUTPUT_MUTE (0x1 << 7)
#define ASC_MONO_OUTPUT_ACTIVE (0x0 << 7)
#define ASC_MONO_CROSSZERO_EN (0x1 << 6)
//ACCELCODEC_R1A
#define ASC_VMDSCL_SLOWEST (0x0 << 2)
#define ASC_VMDSCL_SLOW (0x1 << 2)
#define ASC_VMDSCL_FAST (0x2 << 2)
#define ASC_VMDSCL_FASTEST (0x3 << 2)
#define ASC_MICBIAS_09 (0x1 << 4)
#define ASC_MICBIAS_06 (0x0 << 4)
#define ASC_L2M_ENABLE (0x1 << 5) //the right channel LPF output is fed to mono PA
#define ASC_L2M_DISABLE (0x0 << 5)
#define ASC_R2M_ENABLE (0x1 << 6) //the left channel LPF output is fed to mono PA
#define ASC_R2M_DISABLE (0x0 << 6)
#define ASC_CAPLESS_ENABLE (0x1 << 7) //the capless connection is enable
#define ASC_CAPLESS_DISABLE (0x0 << 7)
//ACCELCODEC_R1C
#define ASC_DITH_0_DIV (0x0 << 3) //the amplitude setting of the ASDM dither(div=vdd/48)
#define ASC_DITH_2_DIV (0x1 << 3)
#define ASC_DITH_4_DIV (0x2 << 3)
#define ASC_DITH_8_DIV (0x3 << 3)
#define ASC_DITH_ENABLE (0x1 << 5) //the ASDM dither is enabled
#define ASC_DITH_DISABLE (0x0 << 5)
#define ASC_DEM_ENABLE (0x1 << 7) //the ASDM DEM is enabled
#define ASC_DEM_DISABLE (0x0 << 7)
//ACCELCODEC_R1D
#define ASC_PDVMID_ENABLE (0x1) //the VMID reference is powered down. VMID is connected to GND
#define ASC_PDVMID_DISABLE (0x0)
#define ASC_PDSDL_ENABLE (0x1 << 2) //the PGA S2D buffer is power down
#define ASC_PDSDL_DISABLE (0x0 << 2)
#define ASC_PDBSTL_ENABLE (0x1 << 4) //the micphone input Op-Amp is power down
#define ASC_PDBSTL_DISABLE (0x0 << 4)
#define ASC_PDPGAL_ENABLE (0x1 << 6) //the PGA is power down
#define ASC_PDPGAL_DISABLE (0x0 << 6)
#define ASC_PDREF_ENABLE (0x1 << 7) //reference generator is power down
#define ASC_PDREF_DISABLE (0x0 << 7)
//ACCELCODEC_R1E
#define ASC_PDPAR_ENABLE (0x1) //the right channel PA is power down
#define ASC_PDPAR_DISABLE (0x0)
#define ASC_PDPAL_ENABLE (0x1 << 1) //the left channel power amplifier is power down
#define ASC_PDPAL_DISABLE (0x0 << 1)
#define ASC_PDMIXR_ENABLE (0x1 << 2) //the right mixer is power down
#define ASC_PDMIXR_DISABLE (0x0 << 2)
#define ASC_PDMIXL_ENABLE (0x1 << 3) //the left mixer is power down
#define ASC_PDMIXL_DISABLE (0x0 << 3)
#define ASC_PDLPFR_ENABLE (0x1 << 4) //the right RC LPF is power down
#define ASC_PDLPFR_DISABLE (0x0 << 4)
#define ASC_PDLPFL_ENABLE (0x1 << 5) //the left channel RC LPF is power down
#define ASC_PDLPFL_DISABLE (0x0 << 5)
#define ASC_PDASDML_ENABLE (0x1 << 7) //the ASDM is power down
#define ASC_PDASDML_DISABLE (0x0 << 7)
//ACCELCODEC_R1F
#define ASC_PDSCFR_ENABLE (0x1 << 1) //the right channel DAC is power down
#define ASC_PDSCFR_DISABLE (0x0 << 1)
#define ASC_PDSCFL_ENABLE (0x1 << 2) //the left channel DAC is power down
#define ASC_PDSCFL_DISABLE (0x0 << 2)
#define ASC_PDMICB_ENABLE (0x1 << 4) //the micbias is power down
#define ASC_PDMICB_DISABLE (0x0 << 4)
#define ASC_PDIB_ENABLE (0x1 << 5) //the left channel LPF is power down
#define ASC_PDIB_DISABLE (0x0 << 5)
#define ASC_PDMIXM_ENABLE (0x1 << 6) //the mon mixer is power down
#define ASC_PDMIXM_DISABLE (0x0 << 6)
#define ASC_PDPAM_ENABLE (0x1 << 7) //the mono PA is power down.
#define ASC_PDPAM_DISABLE (0x0 << 7)
#define LINE_2_MIXER_GAIN (0x5) //left and right PA gain
#define RK610_CODEC_NUM_REG 0x20
#define GPIO_HIGH 1
#define GPIO_LOW 0
extern int rk610_control_init_codec(void);
extern int rk610_codec_pll_set(unsigned int rate);
#endif

3280
sound/soc/codecs/rk616_codec.c
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sound/soc/codecs/rk616_codec.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* rk616.h -- RK616 CODEC ALSA SoC audio driver
*
* Copyright 2013 Rockship
* Author: chenjq <chenjq@rock-chips.com>
*
*/
#ifndef __RK616_CODEC_H__
#define __RK616_CODEC_H__
/* mfd register */
/* CRU_PCM2IS2_CON2 (0x0098) */
#define PCM_TO_I2S_MUX (1 << 3)
#define APS_SEL (1 << 2)
#define APS_CLR (1 << 1)
#define I2S_CHANNEL_SEL (1 << 0)
/* CRU_CFGMISC_CON (0x009C) */
#define MICDET1_PIN_F_CODEC (1 << 18)
#define MICDET2_PIN_F_CODEC (1 << 17)
#define AD_DA_LOOP (1 << 0)
#define AD_DA_LOOP_SFT 0
/* codec register */
#define RK616_CODEC_BASE 0x0800
#define RK616_RESET (RK616_CODEC_BASE + 0x00)
#define RK616_DAC_VOL (RK616_CODEC_BASE + 0x04)
#define RK616_ADC_INT_CTL1 (RK616_CODEC_BASE + 0x08)
#define RK616_ADC_INT_CTL2 (RK616_CODEC_BASE + 0x0c)
#define RK616_DAC_INT_CTL1 (RK616_CODEC_BASE + 0x10)
#define RK616_DAC_INT_CTL2 (RK616_CODEC_BASE + 0x14)
#define RK616_CLK_CHPUMP (RK616_CODEC_BASE + 0x1c)
#define RK616_PGA_AGC_CTL (RK616_CODEC_BASE + 0x28)
#define RK616_PWR_ADD1 (RK616_CODEC_BASE + 0x3c)
#define RK616_BST_CTL (RK616_CODEC_BASE + 0x40)
#define RK616_DIFFIN_CTL (RK616_CODEC_BASE + 0x44)
#define RK616_MIXINL_CTL (RK616_CODEC_BASE + 0x48)
#define RK616_MIXINL_VOL1 (RK616_CODEC_BASE + 0x4c)
#define RK616_MIXINL_VOL2 (RK616_CODEC_BASE + 0x50)
#define RK616_MIXINR_CTL (RK616_CODEC_BASE + 0x54)
#define RK616_MIXINR_VOL1 (RK616_CODEC_BASE + 0x58)
#define RK616_MIXINR_VOL2 (RK616_CODEC_BASE + 0x5c)
#define RK616_PGAL_CTL (RK616_CODEC_BASE + 0x60)
#define RK616_PGAR_CTL (RK616_CODEC_BASE + 0x64)
#define RK616_PWR_ADD2 (RK616_CODEC_BASE + 0x68)
#define RK616_DAC_CTL (RK616_CODEC_BASE + 0x6c)
#define RK616_LINEMIX_CTL (RK616_CODEC_BASE + 0x70)
#define RK616_MUXHP_HPMIX_CTL (RK616_CODEC_BASE + 0x74)
#define RK616_HPMIX_CTL (RK616_CODEC_BASE + 0x78)
#define RK616_HPMIX_VOL1 (RK616_CODEC_BASE + 0x7c)
#define RK616_HPMIX_VOL2 (RK616_CODEC_BASE + 0x80)
#define RK616_LINEOUT1_CTL (RK616_CODEC_BASE + 0x84)
#define RK616_LINEOUT2_CTL (RK616_CODEC_BASE + 0x88)
#define RK616_SPKL_CTL (RK616_CODEC_BASE + 0x8c)
#define RK616_SPKR_CTL (RK616_CODEC_BASE + 0x90)
#define RK616_HPL_CTL (RK616_CODEC_BASE + 0x94)
#define RK616_HPR_CTL (RK616_CODEC_BASE + 0x98)
#define RK616_MICBIAS_CTL (RK616_CODEC_BASE + 0x9c)
#define RK616_MICKEY_DET_CTL (RK616_CODEC_BASE + 0xa0)
#define RK616_PWR_ADD3 (RK616_CODEC_BASE + 0xa4)
#define RK616_ADC_CTL (RK616_CODEC_BASE + 0xa8)
/* Signal zero-crossing detection */
#define RK616_SINGNAL_ZC_CTL1 (RK616_CODEC_BASE + 0xac)
/* Signal zero-crossing detection */
#define RK616_SINGNAL_ZC_CTL2 (RK616_CODEC_BASE + 0xB0)
#define RK616_PGAL_AGC_CTL1 (RK616_CODEC_BASE + 0xc0)
#define RK616_PGAL_AGC_CTL2 (RK616_CODEC_BASE + 0xc4)
#define RK616_PGAL_AGC_CTL3 (RK616_CODEC_BASE + 0xc8)
#define RK616_PGAL_AGC_CTL4 (RK616_CODEC_BASE + 0xcc)
#define RK616_PGAL_ASR_CTL (RK616_CODEC_BASE + 0xd0)
#define RK616_PGAL_AGC_MAX_H (RK616_CODEC_BASE + 0xd4)
#define RK616_PGAL_AGC_MAX_L (RK616_CODEC_BASE + 0xd8)
#define RK616_PGAL_AGC_MIN_H (RK616_CODEC_BASE + 0xdc)
#define RK616_PGAL_AGC_MIN_L (RK616_CODEC_BASE + 0xe0)
#define RK616_PGAL_AGC_CTL5 (RK616_CODEC_BASE + 0xe4)
#define RK616_PGAR_AGC_CTL1 (RK616_CODEC_BASE + 0x100)
#define RK616_PGAR_AGC_CTL2 (RK616_CODEC_BASE + 0x104)
#define RK616_PGAR_AGC_CTL3 (RK616_CODEC_BASE + 0x108)
#define RK616_PGAR_AGC_CTL4 (RK616_CODEC_BASE + 0x10c)
#define RK616_PGAR_ASR_CTL (RK616_CODEC_BASE + 0x110)
#define RK616_PGAR_AGC_MAX_H (RK616_CODEC_BASE + 0x114)
#define RK616_PGAR_AGC_MAX_L (RK616_CODEC_BASE + 0x118)
#define RK616_PGAR_AGC_MIN_H (RK616_CODEC_BASE + 0x11c)
#define RK616_PGAR_AGC_MIN_L (RK616_CODEC_BASE + 0x120)
#define RK616_PGAR_AGC_CTL5 (RK616_CODEC_BASE + 0x124)
/* global definition (0x8c 0x90 0x94 0x98) */
#define RK616_PWRD (0x1 << 7)
#define RK616_PWRD_SFT 7
#define RK616_INIT_MASK (0x1 << 6)
#define RK616_INIT_SFT 6
#define RK616_INIT_RN (0x1 << 6)
#define RK616_INIT_AFT (0x0 << 6)
#define RK616_MUTE (0x1 << 5)
#define RK616_MUTE_SFT 5
#define RK616_VOL_MASK 0x1f
#define RK616_VOL_SFT 0
/* ADC Interface Control 1 (0x08) */
#define RK616_ALRCK_POL_MASK (0x1 << 7)
#define RK616_ALRCK_POL_SFT 7
#define RK616_ALRCK_POL_EN (0x1 << 7)
#define RK616_ALRCK_POL_DIS (0x0 << 7)
#define RK616_ADC_VWL_MASK (0x3 << 5)
#define RK616_ADC_VWL_SFT 5
#define RK616_ADC_VWL_32 (0x3 << 5)
#define RK616_ADC_VWL_24 (0x2 << 5)
#define RK616_ADC_VWL_20 (0x1 << 5)
#define RK616_ADC_VWL_16 (0x0 << 5)
#define RK616_ADC_DF_MASK (0x3 << 3)
#define RK616_ADC_DF_SFT 3
#define RK616_ADC_DF_PCM (0x3 << 3)
#define RK616_ADC_DF_I2S (0x2 << 3)
#define RK616_ADC_DF_LJ (0x1 << 3)
#define RK616_ADC_DF_RJ (0x0 << 3)
#define RK616_ADC_SWAP_MASK (0x1 << 1)
#define RK616_ADC_SWAP_SFT 1
#define RK616_ADC_SWAP_EN (0x1 << 1)
#define RK616_ADC_SWAP_DIS (0x0 << 1)
#define RK616_ADC_TYPE_MASK 0x1
#define RK616_ADC_TYPE_SFT 0
#define RK616_ADC_TYPE_MONO 0x1
#define RK616_ADC_TYPE_STEREO 0x0
/* ADC Interface Control 2 (0x0c) */
#define RK616_I2S_MODE_MASK (0x1 << 4)
#define RK616_I2S_MODE_SFT 4
#define RK616_I2S_MODE_MST (0x1 << 4)
#define RK616_I2S_MODE_SLV (0x0 << 4)
#define RK616_ADC_WL_MASK (0x3 << 2)
#define RK616_ADC_WL_SFT 2
#define RK616_ADC_WL_32 (0x3 << 2)
#define RK616_ADC_WL_24 (0x2 << 2)
#define RK616_ADC_WL_20 (0x1 << 2)
#define RK616_ADC_WL_16 (0x0 << 2)
#define RK616_ADC_RST_MASK (0x1 << 1)
#define RK616_ADC_RST_SFT 1
#define RK616_ADC_RST_DIS (0x1 << 1)
#define RK616_ADC_RST_EN (0x0 << 1)
#define RK616_ABCLK_POL_MASK 0x1
#define RK616_ABCLK_POL_SFT 0
#define RK616_ABCLK_POL_EN 0x1
#define RK616_ABCLK_POL_DIS 0x0
/* DAC Interface Control 1 (0x10) */
#define RK616_DLRCK_POL_MASK (0x1 << 7)
#define RK616_DLRCK_POL_SFT 7
#define RK616_DLRCK_POL_EN (0x1 << 7)
#define RK616_DLRCK_POL_DIS (0x0 << 7)
#define RK616_DAC_VWL_MASK (0x3 << 5)
#define RK616_DAC_VWL_SFT 5
#define RK616_DAC_VWL_32 (0x3 << 5)
#define RK616_DAC_VWL_24 (0x2 << 5)
#define RK616_DAC_VWL_20 (0x1 << 5)
#define RK616_DAC_VWL_16 (0x0 << 5)
#define RK616_DAC_DF_MASK (0x3 << 3)
#define RK616_DAC_DF_SFT 3
#define RK616_DAC_DF_PCM (0x3 << 3)
#define RK616_DAC_DF_I2S (0x2 << 3)
#define RK616_DAC_DF_LJ (0x1 << 3)
#define RK616_DAC_DF_RJ (0x0 << 3)
#define RK616_DAC_SWAP_MASK (0x1 << 2)
#define RK616_DAC_SWAP_SFT 2
#define RK616_DAC_SWAP_EN (0x1 << 2)
#define RK616_DAC_SWAP_DIS (0x0 << 2)
/* DAC Interface Control 2 (0x14) */
#define RK616_DAC_WL_MASK (0x3 << 2)
#define RK616_DAC_WL_SFT 2
#define RK616_DAC_WL_32 (0x3 << 2)
#define RK616_DAC_WL_24 (0x2 << 2)
#define RK616_DAC_WL_20 (0x1 << 2)
#define RK616_DAC_WL_16 (0x0 << 2)
#define RK616_DAC_RST_MASK (0x1 << 1)
#define RK616_DAC_RST_SFT 1
#define RK616_DAC_RST_DIS (0x1 << 1)
#define RK616_DAC_RST_EN (0x0 << 1)
#define RK616_DBCLK_POL_MASK 0x1
#define RK616_DBCLK_POL_SFT 0
#define RK616_DBCLK_POL_EN 0x1
#define RK616_DBCLK_POL_DIS 0x0
/* PGA AGC Enable (0x28) */
#define RK616_PGAL_AGC_EN_MASK (0x1 << 5)
#define RK616_PGAL_AGC_EN_SFT 5
#define RK616_PGAL_AGC_EN (0x1 << 5)
#define RK616_PGAL_AGC_DIS (0x0 << 5)
#define RK616_PGAR_AGC_EN_MASK (0x1 << 4)
#define RK616_PGAR_AGC_EN_SFT 4
#define RK616_PGAR_AGC_EN (0x1 << 4)
#define RK616_PGAR_AGC_DIS (0x0 << 4)
/* Power Management Addition 1 (0x3c) */
#define RK616_ADC_PWRD (0x1 << 6)
#define RK616_ADC_PWRD_SFT 6
#define RK616_DIFFIN_MIR_PGAR_RLPWRD (0x1 << 5)
#define RK616_DIFFIN_MIR_PGAR_RLPWRD_SFT 5
#define RK616_MIC1_MIC2_MIL_PGAL_RLPWRD (0x1 << 4)
#define RK616_MIC1_MIC2_MIL_PGAL_RLPWRD_SFT 4
#define RK616_ADCL_RLPWRD (0x1 << 3)
#define RK616_ADCL_RLPWRD_SFT 3
#define RK616_ADCR_RLPWRD (0x1 << 2)
#define RK616_ADCR_RLPWRD_SFT 2
/* BST Control (0x40) */
#define RK616_BSTL_PWRD (0x1 << 7)
#define RK616_BSTL_PWRD_SFT 7
#define RK616_BSTL_MODE_MASK (0x1 << 6)
#define RK616_BSTL_MODE_SFT 6
#define RK616_BSTL_MODE_SE (0x1 << 6)
#define RK616_BSTL_MODE_DIFF (0x0 << 6)
#define RK616_BSTL_GAIN_MASK (0x1 << 5)
#define RK616_BSTL_GAIN_SFT 5
#define RK616_BSTL_GAIN_20DB (0x1 << 5)
#define RK616_BSTL_GAIN_0DB (0x0 << 5)
#define RK616_BSTL_MUTE (0x1 << 4)
#define RK616_BSTL_MUTE_SFT 4
#define RK616_BSTR_PWRD (0x1 << 3)
#define RK616_BSTR_PWRD_SFT 3
#define RK616_BSTR_MODE_MASK (0x1 << 2)
#define RK616_BSTR_MODE_SFT 2
#define RK616_BSTR_MODE_SE (0x1 << 2)
#define RK616_BSTR_MODE_DIFF (0x0 << 2)
#define RK616_BSTR_GAIN_MASK (0x1 << 1)
#define RK616_BSTR_GAIN_SFT 1
#define RK616_BSTR_GAIN_20DB (0x1 << 1)
#define RK616_BSTR_GAIN_0DB (0x0 << 1)
#define RK616_BSTR_MUTE 0x1
#define RK616_BSTR_MUTE_SFT 0
/* DIFFIN Control (0x44) */
#define RK616_DIFFIN_PWRD (0x1 << 5)
#define RK616_DIFFIN_PWRD_SFT 5
#define RK616_DIFFIN_MODE_MASK (0x1 << 4)
#define RK616_DIFFIN_MODE_SFT 4
#define RK616_DIFFIN_MODE_SE (0x1 << 4)
#define RK616_DIFFIN_MODE_DIFF (0x0 << 4)
#define RK616_DIFFIN_GAIN_MASK (0x1 << 3)
#define RK616_DIFFIN_GAIN_SFT 3
#define RK616_DIFFIN_GAIN_20DB (0x1 << 3)
#define RK616_DIFFIN_GAIN_0DB (0x0 << 3)
#define RK616_DIFFIN_MUTE (0x1 << 2)
#define RK616_DIFFIN_MUTE_SFT 2
#define RK616_MIRM_F_MASK (0x1 << 1)
#define RK616_MIRM_F_SFT 1
#define RK616_MIRM_F_IN1N (0x1 << 1)
#define RK616_MIRM_F_DIFFIN (0x0 << 1)
#define RK616_HMM_F_MASK 0x1
#define RK616_HMM_F_SFT 0
#define RK616_HMM_F_IN1N 0x1
#define RK616_HMM_F_DIFFIN 0x0
/* BSTR MUXMIC MIXINL Control (0x48) */
#define RK616_SE_BSTR_F_MASK (0x1 << 6)
#define RK616_SE_BSTR_F_SFT 6
#define RK616_SE_BSTR_F_MIN2P (0x1 << 6)
#define RK616_SE_BSTR_F_MIN2N (0x0 << 6)
#define RK616_MM_F_MASK (0x1 << 5)
#define RK616_MM_F_SFT 5
#define RK616_MM_F_BSTR (0x1 << 5)
#define RK616_MM_F_BSTL (0x0 << 5)
#define RK616_MIL_PWRD (0x1 << 4)
#define RK616_MIL_PWRD_SFT 4
#define RK616_MIL_MUTE (0x1 << 3)
#define RK616_MIL_MUTE_SFT 3
#define RK616_MIL_F_IN3L (0x1 << 2)
#define RK616_MIL_F_IN3L_SFT 2
#define RK616_MIL_F_IN1P (0x1 << 1)
#define RK616_MIL_F_IN1P_SFT 1
#define RK616_MIL_F_MUX (0x1 << 0)
#define RK616_MIL_F_MUX_SFT 0
/* MIXINL volume 1 (0x4c) */
#define RK616_MIL_F_MUX_VOL_MASK (0x7 << 3)
#define RK616_MIL_F_MUX_VOL_SFT 3
#define RK616_MIL_F_IN1P_VOL_MASK 0x7
#define RK616_MIL_F_IN1P_VOL_SFT 0
/* MIXINL volume 2 (0x50) */
#define RK616_MIL_F_IN3L_VOL_MASK 0x7
#define RK616_MIL_F_IN3L_VOL_SFT 0
/* MIXINR Control (0x54) */
#define RK616_MIR_PWRD (0x1 << 5)
#define RK616_MIR_PWRD_SFT 5
#define RK616_MIR_MUTE (0x1 << 4)
#define RK616_MIR_MUTE_SFT 4
#define RK616_MIR_F_MIC2N (0x1 << 3)
#define RK616_MIR_F_MIC2N_SFT 3
#define RK616_MIR_F_IN1P (0x1 << 2)
#define RK616_MIR_F_IN1P_SFT 2
#define RK616_MIR_F_IN3R (0x1 << 1)
#define RK616_MIR_F_IN3R_SFT 1
#define RK616_MIR_F_MIRM 0x1
#define RK616_MIR_F_MIRM_SFT 0
/* MIXINR volume 1 (0x58) */
#define RK616_MIR_F_MIRM_VOL_MASK (0x7 << 3)
#define RK616_MIR_F_MIRM_VOL_SFT 3
#define RK616_MIR_F_IN3R_VOL_MASK 0x7
#define RK616_MIR_F_IN3R_VOL_SFT 0
/* MIXINR volume 2 (0x5c) */
#define RK616_MIR_F_MIC2N_VOL_MASK (0x7 << 3)
#define RK616_MIR_F_MIC2N_VOL_SFT 3
#define RK616_MIR_F_IN1P_VOL_MASK 0x7
#define RK616_MIR_F_IN1P_VOL_SFT 0
/* PGA Control (0x60 0x64) */
#define RK616_PGA_PWRD (0x1 << 7)
#define RK616_PGA_PWRD_SFT 7
#define RK616_PGA_MUTE (0x1 << 6)
#define RK616_PGA_MUTE_SFT 6
#define RK616_PGA_VOL_MASK (0x1f << 0)
#define RK616_PGA_VOL_SFT 0
/* Power Management Addition 2 (0x68) */
#define RK616_HPL_HPR_PWRD (0x1 << 7)
#define RK616_HPL_HPR_PWRD_SFT 7
#define RK616_DAC_PWRD (0x1 << 6)
#define RK616_DAC_PWRD_SFT 6
#define RK616_DACL_RLPWRD (0x1 << 5)
#define RK616_DACL_RLPWRD_SFT 5
#define RK616_DACL_SPKL_RLPWRD (0x1 << 4)
#define RK616_DACL_SPKL_RLPWRD_SFT 4
#define RK616_DACR_RLPWRD (0x1 << 3)
#define RK616_DACR_RLPWRD_SFT 3
#define RK616_DACR_SPKR_RLPWRD (0x1 << 2)
#define RK616_DACR_SPKR_RLPWRD_SFT 2
#define RK616_LM_LO_RLPWRD (0x1 << 1)
#define RK616_LM_LO_RLPWRD_SFT 1
#define RK616_HM_RLPWRD 0x1
#define RK616_HM_RLPWRD_SFT 0
/* DAC Control (0x6c) */
#define RK616_DACL_INIT_MASK (0x1 << 5)
#define RK616_DACL_INIT_SFT 5
#define RK616_DACL_INIT_WORK (0x1 << 5)
#define RK616_DACL_INIT_NOT (0x0 << 5)
#define RK616_DACR_INIT_MASK (0x1 << 4)
#define RK616_DACR_INIT_SFT 4
#define RK616_DACR_INIT_WORK (0x1 << 4)
#define RK616_DACR_INIT_NOT (0x0 << 4)
#define RK616_DACL_PWRD (0x1 << 3)
#define RK616_DACL_PWRD_SFT 3
#define RK616_DACR_PWRD (0x1 << 2)
#define RK616_DACR_PWRD_SFT 2
#define RK616_DACR_CLK_PWRD (0x1 << 1)
#define RK616_DACR_CLK_PWRD_SFT 1
#define RK616_DACL_CLK_PWRD 0x1
#define RK616_DACL_CLK_PWRD_SFT 0
/* Linemix Control (0x70) */
#define RK616_LM_PWRD (0x1 << 4)
#define RK616_LM_PWRD_SFT 4
#define RK616_LM_F_PGAR (0x1 << 3)
#define RK616_LM_F_PGAR_SFT 3
#define RK616_LM_F_PGAL (0x1 << 2)
#define RK616_LM_F_PGAL_SFT 2
#define RK616_LM_F_DACR (0x1 << 1)
#define RK616_LM_F_DACR_SFT 1
#define RK616_LM_F_DACL 0x1
#define RK616_LM_F_DACL_SFT 0
/* MUXHP HPMIX Control (0x74) */
#define RK616_HML_PWRD (0x1 << 5)
#define RK616_HML_PWRD_SFT 5
#define RK616_HML_INIT_MASK (0x1 << 4)
#define RK616_HML_INIT_SFT 4
#define RK616_HML_INIT_RN (0x1 << 4)
#define RK616_HML_INIT_AFT (0x0 << 4)
#define RK616_HMR_PWRD (0x1 << 3)
#define RK616_HMR_PWRD_SFT 3
#define RK616_HMR_INIT_MASK (0x1 << 2)
#define RK616_HMR_INIT_SFT 2
#define RK616_HMR_INIT_RN (0x1 << 2)
#define RK616_HMR_INIT_AFT (0x0 << 2)
#define RK616_MHL_F_MASK (0x1 << 1)
#define RK616_MHL_F_SFT 1
#define RK616_MHL_F_DACL (0x1 << 1)
#define RK616_MHL_F_HPMIXL (0x0 << 1)
#define RK616_MHR_F_MASK 0x1
#define RK616_MHR_F_SFT 0
#define RK616_MHR_F_DACR 0x1
#define RK616_MHR_F_HPMIXR 0x0
/* HPMIX Control (0x78) */
#define RK616_HML_F_HMM (0x1 << 7)
#define RK616_HML_F_HMM_SFT 7
#define RK616_HML_F_IN1P (0x1 << 6)
#define RK616_HML_F_IN1P_SFT 6
#define RK616_HML_F_PGAL (0x1 << 5)
#define RK616_HML_F_PGAL_SFT 5
#define RK616_HML_F_DACL (0x1 << 4)
#define RK616_HML_F_DACL_SFT 4
#define RK616_HMR_F_HMM (0x1 << 3)
#define RK616_HMR_F_HMM_SFT 3
#define RK616_HMR_F_PGAR (0x1 << 2)
#define RK616_HMR_F_PGAR_SFT 2
#define RK616_HMR_F_PGAL (0x1 << 1)
#define RK616_HMR_F_PGAL_SFT 1
#define RK616_HMR_F_DACR 0x1
#define RK616_HMR_F_DACR_SFT 0
/* HPMIX Volume Control 1 (0x7c) */
#define RK616_HML_F_IN1P_VOL_MASK 0x7
#define RK616_HML_F_IN1P_VOL_SFT 0
/* HPMIX Volume Control 2 (0x80) */
#define RK616_HML_F_HMM_VOL_MASK (0x7 << 3)
#define RK616_HML_F_HMM_VOL_SFT 3
#define RK616_HMR_F_HMM_VOL_MASK 0x7
#define RK616_HMR_F_HMM_VOL_SFT 0
/* Lineout1 Control (0x84 0x88) */
#define RK616_LINEOUT_PWRD (0x1 << 6)
#define RK616_LINEOUT_PWRD_SFT 6
#define RK616_LINEOUT_MUTE (0x1 << 5)
#define RK616_LINEOUT_MUTE_SFT 5
#define RK616_LINEOUT_VOL_MASK 0x1f
#define RK616_LINEOUT_VOL_SFT 0
/* Micbias Control 1 (0x9c) */
#define RK616_MICBIAS1_PWRD (0x1 << 7)
#define RK616_MICBIAS1_PWRD_SFT 7
#define RK616_MICBIAS2_PWRD (0x1 << 6)
#define RK616_MICBIAS2_PWRD_SFT 6
#define RK616_MICBIAS1_V_MASK (0x7 << 3)
#define RK616_MICBIAS1_V_SFT 3
#define RK616_MICBIAS1_V_1_7 (0x7 << 3)
#define RK616_MICBIAS1_V_1_6 (0x6 << 3)
#define RK616_MICBIAS1_V_1_5 (0x5 << 3)
#define RK616_MICBIAS1_V_1_4 (0x4 << 3)
#define RK616_MICBIAS1_V_1_3 (0x3 << 3)
#define RK616_MICBIAS1_V_1_2 (0x2 << 3)
#define RK616_MICBIAS1_V_1_1 (0x1 << 3)
#define RK616_MICBIAS1_V_1_0 (0x0 << 3)
#define RK616_MICBIAS2_V_MASK 0x7
#define RK616_MICBIAS2_V_SFT 0
#define RK616_MICBIAS2_V_1_7 0x7
#define RK616_MICBIAS2_V_1_6 0x6
#define RK616_MICBIAS2_V_1_5 0x5
#define RK616_MICBIAS2_V_1_4 0x4
#define RK616_MICBIAS2_V_1_3 0x3
#define RK616_MICBIAS2_V_1_2 0x2
#define RK616_MICBIAS2_V_1_1 0x1
#define RK616_MICBIAS2_V_1_0 0x0
/* MIC Key Detection Control (0xa0) */
#define RK616_MK1_DET_MASK (0x1 << 7)
#define RK616_MK1_DET_SFT 7
#define RK616_MK1_EN (0x1 << 7)
#define RK616_MK1_DIS (0x0 << 7)
#define RK616_MK2_DET_MASK (0x1 << 6)
#define RK616_MK2_DET_SFT 6
#define RK616_MK2_EN (0x1 << 6)
#define RK616_MK2_DIS (0x0 << 6)
#define RK616_MK1_DET_I_MASK (0x7 << 3)
#define RK616_MK1_DET_I_SFT 3
#define RK616_MK1_DET_I_1500 (0x7 << 3)
#define RK616_MK1_DET_I_1300 (0x6 << 3)
#define RK616_MK1_DET_I_1100 (0x5 << 3)
#define RK616_MK1_DET_I_900 (0x4 << 3)
#define RK616_MK1_DET_I_700 (0x3 << 3)
#define RK616_MK1_DET_I_500 (0x2 << 3)
#define RK616_MK1_DET_I_300 (0x1 << 3)
#define RK616_MK1_DET_I_100 (0x0 << 3)
#define RK616_MK2_DET_I_MASK 0x7
#define RK616_MK2_DET_I_SFT 0
#define RK616_MK2_DET_I_1500 0x7
#define RK616_MK2_DET_I_1300 0x6
#define RK616_MK2_DET_I_1100 0x5
#define RK616_MK2_DET_I_900 0x4
#define RK616_MK2_DET_I_700 0x3
#define RK616_MK2_DET_I_500 0x2
#define RK616_MK2_DET_I_300 0x1
#define RK616_MK2_DET_I_100 0x0
/* Power Management Addition 3 (0xa4) */
#define RK616_ADCL_ZO_PWRD (0x1 << 3)
#define RK616_ADCL_ZO_PWRD_SFT 3
#define RK616_ADCR_ZO_PWRD (0x1 << 2)
#define RK616_ADCR_ZO_PWRD_SFT 2
#define RK616_DACL_ZO_PWRD (0x1 << 1)
#define RK616_DACL_ZO_PWRD_SFT 1
#define RK616_DACR_ZO_PWRD 0x1
#define RK616_DACR_ZO_PWRD_SFT 0
/* ADC control (0xa8) */
#define RK616_ADCL_CLK_PWRD (0x1 << 5)
#define RK616_ADCL_CLK_PWRD_SFT 5
#define RK616_ADCL_PWRD (0x1 << 4)
#define RK616_ADCL_PWRD_SFT 4
#define RK616_ADCL_CLEAR_MASK (0x1 << 3)
#define RK616_ADCL_CLEAR_SFT 3
#define RK616_ADCL_CLEAR_EN (0x1 << 3)
#define RK616_ADCL_CLEAR_DIS (0x0 << 3)
#define RK616_ADCR_CLK_PWRD (0x1 << 2)
#define RK616_ADCR_CLK_PWRD_SFT 2
#define RK616_ADCR_PWRD (0x1 << 1)
#define RK616_ADCR_PWRD_SFT 1
#define RK616_ADCR_CLEAR_MASK 0x1
#define RK616_ADCR_CLEAR_SFT 0
#define RK616_ADCR_CLEAR_EN 0x1
#define RK616_ADCR_CLEAR_DIS 0x0
/* PGA AGC control 1 (0xc0 0x110) */
#define RK616_PGA_AGC_WAY_MASK (0x1 << 4)
#define RK616_PGA_AGC_WAY_SFT 4
#define RK616_PGA_AGC_WAY_JACK (0x1 << 4)
#define RK616_PGA_AGC_WAY_NOR (0x0 << 4)
#define RK616_PGA_AGC_HOLD_T_MASK 0xf
#define RK616_PGA_AGC_HOLD_T_SFT 0
#define RK616_PGA_AGC_HOLD_T_1024 0xa
#define RK616_PGA_AGC_HOLD_T_512 0x9
#define RK616_PGA_AGC_HOLD_T_256 0x8
#define RK616_PGA_AGC_HOLD_T_128 0x7
#define RK616_PGA_AGC_HOLD_T_64 0x6
#define RK616_PGA_AGC_HOLD_T_32 0x5
#define RK616_PGA_AGC_HOLD_T_16 0x4
#define RK616_PGA_AGC_HOLD_T_8 0x3
#define RK616_PGA_AGC_HOLD_T_4 0x2
#define RK616_PGA_AGC_HOLD_T_2 0x1
#define RK616_PGA_AGC_HOLD_T_0 0x0
/* PGA AGC control 2 (0xc4 0x104) */
#define RK616_PGA_AGC_GRU_T_MASK (0xf << 4)
#define RK616_PGA_AGC_GRU_T_SFT 4
#define RK616_PGA_AGC_GRU_T_512 (0xa << 4)
#define RK616_PGA_AGC_GRU_T_256 (0x9 << 4)
#define RK616_PGA_AGC_GRU_T_128 (0x8 << 4)
#define RK616_PGA_AGC_GRU_T_64 (0x7 << 4)
#define RK616_PGA_AGC_GRU_T_32 (0x6 << 4)
#define RK616_PGA_AGC_GRU_T_16 (0x5 << 4)
#define RK616_PGA_AGC_GRU_T_8 (0x4 << 4)
#define RK616_PGA_AGC_GRU_T_4 (0x3 << 4)
#define RK616_PGA_AGC_GRU_T_2 (0x2 << 4)
#define RK616_PGA_AGC_GRU_T_1 (0x1 << 4)
#define RK616_PGA_AGC_GRU_T_0_5 (0x0 << 4)
#define RK616_PGA_AGC_GRD_T_MASK 0xf
#define RK616_PGA_AGC_GRD_T_SFT 0
#define RK616_PGA_AGC_GRD_T_128_32 0xa
#define RK616_PGA_AGC_GRD_T_64_16 0x9
#define RK616_PGA_AGC_GRD_T_32_8 0x8
#define RK616_PGA_AGC_GRD_T_16_4 0x7
#define RK616_PGA_AGC_GRD_T_8_2 0x6
#define RK616_PGA_AGC_GRD_T_4_1 0x5
#define RK616_PGA_AGC_GRD_T_2_0_512 0x4
#define RK616_PGA_AGC_GRD_T_1_0_256 0x3
#define RK616_PGA_AGC_GRD_T_0_500_128 0x2
#define RK616_PGA_AGC_GRD_T_0_250_64 0x1
#define RK616_PGA_AGC_GRD_T_0_125_32 0x0
/* PGA AGC control 3 (0xc8 0x108) */
#define RK616_PGA_AGC_MODE_MASK (0x1 << 7)
#define RK616_PGA_AGC_MODE_SFT 7
#define RK616_PGA_AGC_MODE_LIMIT (0x1 << 7)
#define RK616_PGA_AGC_MODE_NOR (0x0 << 7)
#define RK616_PGA_AGC_ZO_MASK (0x1 << 6)
#define RK616_PGA_AGC_ZO_SFT 6
#define RK616_PGA_AGC_ZO_EN (0x1 << 6)
#define RK616_PGA_AGC_ZO_DIS (0x0 << 6)
#define RK616_PGA_AGC_REC_MODE_MASK (0x1 << 5)
#define RK616_PGA_AGC_REC_MODE_SFT 5
#define RK616_PGA_AGC_REC_MODE_AC (0x1 << 5)
#define RK616_PGA_AGC_REC_MODE_RN (0x0 << 5)
#define RK616_PGA_AGC_FAST_D_MASK (0x1 << 4)
#define RK616_PGA_AGC_FAST_D_SFT 4
#define RK616_PGA_AGC_FAST_D_EN (0x1 << 4)
#define RK616_PGA_AGC_FAST_D_DIS (0x0 << 4)
#define RK616_PGA_AGC_NG_MASK (0x1 << 3)
#define RK616_PGA_AGC_NG_SFT 3
#define RK616_PGA_AGC_NG_EN (0x1 << 3)
#define RK616_PGA_AGC_NG_DIS (0x0 << 3)
#define RK616_PGA_AGC_NG_THR_MASK 0x7
#define RK616_PGA_AGC_NG_THR_SFT 0
#define RK616_PGA_AGC_NG_THR_N81DB 0x7
#define RK616_PGA_AGC_NG_THR_N75DB 0x6
#define RK616_PGA_AGC_NG_THR_N69DB 0x5
#define RK616_PGA_AGC_NG_THR_N63DB 0x4
#define RK616_PGA_AGC_NG_THR_N57DB 0x3
#define RK616_PGA_AGC_NG_THR_N51DB 0x2
#define RK616_PGA_AGC_NG_THR_N45DB 0x1
#define RK616_PGA_AGC_NG_THR_N39DB 0x0
/* PGA AGC Control 4 (0xcc 0x10c) */
#define RK616_PGA_AGC_ZO_MODE_MASK (0x1 << 5)
#define RK616_PGA_AGC_ZO_MODE_SFT 5
#define RK616_PGA_AGC_ZO_MODE_UWRC (0x1 << 5)
#define RK616_PGA_AGC_ZO_MODE_UARC (0x0 << 5)
#define RK616_PGA_AGC_VOL_MASK 0x1f
#define RK616_PGA_AGC_VOL_SFT 0
/* PGA ASR Control (0xd0 0x110) */
#define RK616_PGA_SLOW_CLK_MASK (0x1 << 3)
#define RK616_PGA_SLOW_CLK_SFT 3
#define RK616_PGA_SLOW_CLK_EN (0x1 << 3)
#define RK616_PGA_SLOW_CLK_DIS (0x0 << 3)
#define RK616_PGA_ASR_MASK 0x7
#define RK616_PGA_ASR_SFT 0
#define RK616_PGA_ASR_8KHz 0x5
#define RK616_PGA_ASR_12KHz 0x4
#define RK616_PGA_ASR_16KHz 0x3
#define RK616_PGA_ASR_24KHz 0x2
#define RK616_PGA_ASR_32KHz 0x1
#define RK616_PGA_ASR_48KHz 0x0
/* PGA AGC Control 5 (0xe4 0x124) */
#define RK616_PGA_AGC_MASK (0x1 << 6)
#define RK616_PGA_AGC_SFT 6
#define RK616_PGA_AGC_EN (0x1 << 6)
#define RK616_PGA_AGC_DIS (0x0 << 6)
#define RK616_PGA_AGC_MAX_G_MASK (0x7 << 3)
#define RK616_PGA_AGC_MAX_G_SFT 3
#define RK616_PGA_AGC_MAX_G_28_5DB (0x7 << 3)
#define RK616_PGA_AGC_MAX_G_22_5DB (0x6 << 3)
#define RK616_PGA_AGC_MAX_G_16_5DB (0x5 << 3)
#define RK616_PGA_AGC_MAX_G_10_5DB (0x4 << 3)
#define RK616_PGA_AGC_MAX_G_4_5DB (0x3 << 3)
#define RK616_PGA_AGC_MAX_G_N1_5DB (0x2 << 3)
#define RK616_PGA_AGC_MAX_G_N7_5DB (0x1 << 3)
#define RK616_PGA_AGC_MAX_G_N13_5DB (0x0 << 3)
#define RK616_PGA_AGC_MIN_G_MASK 0x7
#define RK616_PGA_AGC_MIN_G_SFT 0
#define RK616_PGA_AGC_MIN_G_24DB 0x7
#define RK616_PGA_AGC_MIN_G_18DB 0x6
#define RK616_PGA_AGC_MIN_G_12DB 0x5
#define RK616_PGA_AGC_MIN_G_6DB 0x4
#define RK616_PGA_AGC_MIN_G_0DB 0x3
#define RK616_PGA_AGC_MIN_G_N6DB 0x2
#define RK616_PGA_AGC_MIN_G_N12DB 0x1
#define RK616_PGA_AGC_MIN_G_N18DB 0x0
enum {
RK616_HIFI,
RK616_VOICE,
};
enum {
RK616_MONO = 1,
RK616_STEREO,
};
enum {
OFF,
RCV,
SPK_PATH,
HP_PATH,
HP_NO_MIC,
BT,
SPK_HP,
RING_SPK,
RING_HP,
RING_HP_NO_MIC,
RING_SPK_HP,
};
enum {
MIC_OFF,
MAIN_MIC,
HANDS_FREE_MIC,
BT_SCO_MIC,
};
struct rk616_reg_val_typ {
unsigned int reg;
unsigned int value;
};
struct rk616_init_bit_typ {
unsigned int reg;
unsigned int power_bit;
unsigned int init_bit;
};
bool rk616_get_for_mid(void);
#ifdef CONFIG_HDMI
extern int hdmi_is_insert(void);
#endif
#ifdef CONFIG_HDMI_RK30
extern int hdmi_get_hotplug(void);
#endif
#endif /* __RK616_CODEC_H__ */

1299
sound/soc/codecs/rt3261-dsp.c
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42
sound/soc/codecs/rt3261-dsp.h
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@@ -1,42 +0,0 @@
/*
* rt3261-dsp.h -- RT3261 ALSA SoC DSP driver
*
* Copyright 2011 Realtek Microelectronics
* Author: Johnny Hsu <johnnyhsu@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RT3261_DSP_H__
#define __RT3261_DSP_H__
/* Debug String Length */
#define RT3261_DSP_REG_DISP_LEN 25
enum {
RT3261_DSP_DIS,
RT3261_DSP_AEC_NS_FENS,
RT3261_DSP_HFBF,
RT3261_DSP_FFP,
};
struct rt3261_dsp_param {
u16 cmd_fmt;
u16 addr;
u16 data;
u8 cmd;
};
int rt3261_dsp_write(struct snd_soc_codec *codec, struct rt3261_dsp_param *param);
unsigned int rt3261_dsp_read(struct snd_soc_codec *codec, unsigned int reg);
int rt3261_dsp_probe(struct snd_soc_codec *codec);
int rt_codec_dsp_ioctl_common(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg);
#ifdef CONFIG_PM
int rt3261_dsp_suspend(struct snd_soc_codec *codec);
int rt3261_dsp_resume(struct snd_soc_codec *codec);
#endif
#endif /* __RT3261_DSP_H__ */

3749
sound/soc/codecs/rt3261.c
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2170
sound/soc/codecs/rt3261.h
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467
sound/soc/codecs/rt3261_ioctl.c
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@@ -1,467 +0,0 @@
/*
* rt3261_ioctl.h -- RT3261 ALSA SoC audio driver IO control
*
* Copyright 2012 Realtek Microelectronics
* Author: Bard <bardliao@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/spi/spi.h>
#include <sound/soc.h>
#include "rt_codec_ioctl.h"
#include "rt3261_ioctl.h"
#include "rt3261.h"
#if defined (CONFIG_SND_SOC_RT3261)
#include "rt3261-dsp.h"
#endif
static hweq_t hweq_param[] = {
{/* NORMAL */
{0},
{0},
0x0000,
},
{/* SPK */
{0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0, 0xb1, 0xb2},
{0x1c10,0x01f4, 0xc5e9, 0x1a98, 0x1d2c, 0xc882, 0x1c10, 0x01f4, 0xe904, 0x1c10, 0x01f4, 0xe904, 0x1c10, 0x01f4, 0x1c10, 0x01f4, 0x2000, 0x0000, 0x2000},
0x0000,
},
{/* HP */
{0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 0xb0, 0xb1, 0xb2},
{0x1c10,0x01f4, 0xc5e9, 0x1a98, 0x1d2c, 0xc882, 0x1c10, 0x01f4, 0xe904, 0x1c10, 0x01f4, 0xe904, 0x1c10, 0x01f4, 0x1c10, 0x01f4, 0x2000, 0x0000, 0x2000},
0x0000,
},
};
#define RT3261_HWEQ_LEN ARRAY_SIZE(hweq_param)
int rt3261_update_eqmode(
struct snd_soc_codec *codec, int mode)
{
struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
int i;
static int eq_mode;
if(codec == NULL || mode >= RT3261_HWEQ_LEN)
return -EINVAL;
dev_dbg(codec->dev, "%s(): mode=%d\n", __func__, mode);
if(mode == eq_mode)
return 0;
for(i = 0; i <= EQ_REG_NUM; i++) {
if(hweq_param[mode].reg[i])
ioctl_ops->index_write(codec, hweq_param[mode].reg[i],
hweq_param[mode].value[i]);
else
break;
}
snd_soc_update_bits(codec, RT3261_EQ_CTRL2, RT3261_EQ_CTRL_MASK,
hweq_param[mode].ctrl);
snd_soc_update_bits(codec, RT3261_EQ_CTRL1,
RT3261_EQ_UPD, RT3261_EQ_UPD);
snd_soc_update_bits(codec, RT3261_EQ_CTRL1, RT3261_EQ_UPD, 0);
eq_mode = mode;
return 0;
}
static void set_drc_agc_enable(struct snd_soc_codec *codec, int enable, int path)
{
snd_soc_update_bits(codec, RT3261_DRC_AGC_1, RT3261_DRC_AGC_P_MASK |
RT3261_DRC_AGC_MASK | RT3261_DRC_AGC_UPD,
enable << RT3261_DRC_AGC_SFT | path << RT3261_DRC_AGC_P_SFT |
1 << RT3261_DRC_AGC_UPD_BIT);
}
static void set_drc_agc_parameters(struct snd_soc_codec *codec, int attack_rate,
int sample_rate, int recovery_rate, int limit_level)
{
snd_soc_update_bits(codec, RT3261_DRC_AGC_3, RT3261_DRC_AGC_TAR_MASK,
limit_level << RT3261_DRC_AGC_TAR_SFT);
snd_soc_update_bits(codec, RT3261_DRC_AGC_1, RT3261_DRC_AGC_AR_MASK |
RT3261_DRC_AGC_R_MASK | RT3261_DRC_AGC_UPD |
RT3261_DRC_AGC_RC_MASK, attack_rate << RT3261_DRC_AGC_AR_SFT |
sample_rate << RT3261_DRC_AGC_R_SFT |
recovery_rate << RT3261_DRC_AGC_RC_SFT |
0x1 << RT3261_DRC_AGC_UPD_BIT);
}
static void set_digital_boost_gain(struct snd_soc_codec *codec,
int post_gain, int pre_gain)
{
snd_soc_update_bits(codec, RT3261_DRC_AGC_2,
RT3261_DRC_AGC_POB_MASK | RT3261_DRC_AGC_PRB_MASK,
post_gain << RT3261_DRC_AGC_POB_SFT |
pre_gain << RT3261_DRC_AGC_PRB_SFT);
snd_soc_update_bits(codec, RT3261_DRC_AGC_1,
RT3261_DRC_AGC_UPD, 1 << RT3261_DRC_AGC_UPD_BIT);
}
static void set_noise_gate(struct snd_soc_codec *codec, int noise_gate_en,
int noise_gate_hold_en, int compression_gain, int noise_gate_th)
{
snd_soc_update_bits(codec, RT3261_DRC_AGC_3,
RT3261_DRC_AGC_NGB_MASK | RT3261_DRC_AGC_NG_MASK |
RT3261_DRC_AGC_NGH_MASK | RT3261_DRC_AGC_NGT_MASK,
noise_gate_en << RT3261_DRC_AGC_NG_SFT |
noise_gate_hold_en << RT3261_DRC_AGC_NGH_SFT |
compression_gain << RT3261_DRC_AGC_NGB_SFT |
noise_gate_th << RT3261_DRC_AGC_NGT_SFT);
snd_soc_update_bits(codec, RT3261_DRC_AGC_1,
RT3261_DRC_AGC_UPD, 1 << RT3261_DRC_AGC_UPD_BIT);
}
static void set_drc_agc_compression(struct snd_soc_codec *codec,
int compression_en, int compression_ratio)
{
snd_soc_update_bits(codec, RT3261_DRC_AGC_2,
RT3261_DRC_AGC_CP_MASK | RT3261_DRC_AGC_CPR_MASK,
compression_en << RT3261_DRC_AGC_CP_SFT |
compression_ratio << RT3261_DRC_AGC_CPR_SFT);
snd_soc_update_bits(codec, RT3261_DRC_AGC_1,
RT3261_DRC_AGC_UPD, 1 << RT3261_DRC_AGC_UPD_BIT);
}
static void get_drc_agc_enable(struct snd_soc_codec *codec, int *enable, int *path)
{
unsigned int reg = snd_soc_read(codec, RT3261_DRC_AGC_1);
*enable = (reg & RT3261_DRC_AGC_MASK) >> RT3261_DRC_AGC_SFT;
*path = (reg & RT3261_DRC_AGC_P_MASK) >> RT3261_DRC_AGC_P_SFT;
}
void get_drc_agc_parameters(struct snd_soc_codec *codec, int *attack_rate,
int *sample_rate, int *recovery_rate, int *limit_level)
{
unsigned int reg = snd_soc_read(codec, RT3261_DRC_AGC_3);
*limit_level = (reg & RT3261_DRC_AGC_TAR_MASK) >>
RT3261_DRC_AGC_TAR_SFT;
reg = snd_soc_read(codec, RT3261_DRC_AGC_1);
*attack_rate = (reg & RT3261_DRC_AGC_AR_MASK) >> RT3261_DRC_AGC_AR_SFT;
*sample_rate = (reg & RT3261_DRC_AGC_R_MASK) >> RT3261_DRC_AGC_R_SFT;
*recovery_rate = (reg & RT3261_DRC_AGC_RC_MASK) >>
RT3261_DRC_AGC_RC_SFT;
}
static void get_digital_boost_gain(struct snd_soc_codec *codec,
int *post_gain, int *pre_gain)
{
unsigned int reg = snd_soc_read(codec, RT3261_DRC_AGC_2);
*post_gain = (reg & RT3261_DRC_AGC_POB_MASK) >> RT3261_DRC_AGC_POB_SFT;
*pre_gain = (reg & RT3261_DRC_AGC_PRB_MASK) >> RT3261_DRC_AGC_PRB_SFT;
}
static void get_noise_gate(struct snd_soc_codec *codec, int *noise_gate_en,
int *noise_gate_hold_en, int *compression_gain, int *noise_gate_th)
{
unsigned int reg = snd_soc_read(codec, RT3261_DRC_AGC_3);
printk("get_noise_gate reg=0x%04x\n",reg);
*noise_gate_en = (reg & RT3261_DRC_AGC_NG_MASK) >>
RT3261_DRC_AGC_NG_SFT;
*noise_gate_hold_en = (reg & RT3261_DRC_AGC_NGH_MASK) >>
RT3261_DRC_AGC_NGH_SFT;
*compression_gain = (reg & RT3261_DRC_AGC_NGB_MASK) >>
RT3261_DRC_AGC_NGB_SFT;
*noise_gate_th = (reg & RT3261_DRC_AGC_NGT_MASK) >>
RT3261_DRC_AGC_NGT_SFT;
}
static void get_drc_agc_compression(struct snd_soc_codec *codec,
int *compression_en, int *compression_ratio)
{
unsigned int reg = snd_soc_read(codec, RT3261_DRC_AGC_2);
*compression_en = (reg & RT3261_DRC_AGC_CP_MASK) >>
RT3261_DRC_AGC_CP_SFT;
*compression_ratio = (reg & RT3261_DRC_AGC_CPR_MASK) >>
RT3261_DRC_AGC_CPR_SFT;
}
int rt3261_ioctl_common(struct snd_hwdep *hw, struct file *file,
unsigned int cmd, unsigned long arg)
{
struct snd_soc_codec *codec = hw->private_data;
struct rt_codec_cmd __user *_rt_codec = (struct rt_codec_cmd *)arg;
struct rt_codec_cmd rt_codec;
struct rt_codec_ops *ioctl_ops = rt_codec_get_ioctl_ops();
int *buf, mask1 = 0, mask2 = 0;
static int eq_mode;
if (copy_from_user(&rt_codec, _rt_codec, sizeof(rt_codec))) {
dev_err(codec->dev,"copy_from_user faild\n");
return -EFAULT;
}
dev_dbg(codec->dev, "%s(): rt_codec.number=%zu, cmd=%d\n",
__func__, rt_codec.number, cmd);
buf = kmalloc(sizeof(*buf) * rt_codec.number, GFP_KERNEL);
if (buf == NULL)
return -ENOMEM;
if (copy_from_user(buf, rt_codec.buf, sizeof(*buf) * rt_codec.number)) {
goto err;
}
switch (cmd) {
case RT_SET_CODEC_HWEQ_IOCTL:
if (eq_mode == *buf)
break;
eq_mode = *buf;
rt3261_update_eqmode(codec, eq_mode);
break;
case RT_GET_CODEC_ID:
*buf = snd_soc_read(codec, RT3261_VENDOR_ID2);
if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
goto err;
break;
case RT_SET_CODEC_SPK_VOL_IOCTL:
if(*(buf) <= 0x27) {
snd_soc_update_bits(codec, RT3261_SPK_VOL,
RT3261_L_VOL_MASK | RT3261_R_VOL_MASK,
*(buf) << RT3261_L_VOL_SFT |
*(buf) << RT3261_R_VOL_SFT);
}
break;
case RT_SET_CODEC_MIC_GAIN_IOCTL:
if(*(buf) <= 0x8) {
snd_soc_update_bits(codec, RT3261_IN1_IN2,
RT3261_BST_MASK1, *(buf) << RT3261_BST_SFT1);
snd_soc_update_bits(codec, RT3261_IN3_IN4,
RT3261_BST_MASK2, *(buf) << RT3261_BST_SFT2);
}
break;
case RT_SET_CODEC_3D_SPK_IOCTL:
if(rt_codec.number < 4)
break;
if (NULL == ioctl_ops->index_update_bits)
break;
mask1 = 0;
if(*buf != -1)
mask1 |= RT3261_3D_SPK_MASK;
if(*(buf + 1) != -1)
mask1 |= RT3261_3D_SPK_M_MASK;
if(*(buf + 2) != -1)
mask1 |= RT3261_3D_SPK_CG_MASK;
if(*(buf + 3) != -1)
mask1 |= RT3261_3D_SPK_SG_MASK;
ioctl_ops->index_update_bits(codec, RT3261_3D_SPK, mask1,
*(buf) << RT3261_3D_SPK_SFT |
*(buf + 1) << RT3261_3D_SPK_M_SFT |
*(buf + 2) << RT3261_3D_SPK_CG_SFT |
*(buf + 3) << RT3261_3D_SPK_SG_SFT);
break;
case RT_SET_CODEC_MP3PLUS_IOCTL:
if(rt_codec.number < 5)
break;
mask1 = mask2 = 0;
if(*buf != -1)
mask1 |= RT3261_M_MP3_MASK;
if(*(buf + 1) != -1)
mask1 |= RT3261_EG_MP3_MASK;
if(*(buf + 2) != -1)
mask2 |= RT3261_OG_MP3_MASK;
if(*(buf + 3) != -1)
mask2 |= RT3261_HG_MP3_MASK;
if(*(buf + 4) != -1)
mask2 |= RT3261_MP3_WT_MASK;
snd_soc_update_bits(codec, RT3261_MP3_PLUS1, mask1,
*(buf) << RT3261_M_MP3_SFT |
*(buf + 1) << RT3261_EG_MP3_SFT);
snd_soc_update_bits(codec, RT3261_MP3_PLUS2, mask2,
*(buf + 2) << RT3261_OG_MP3_SFT |
*(buf + 3) << RT3261_HG_MP3_SFT |
*(buf + 4) << RT3261_MP3_WT_SFT);
break;
case RT_SET_CODEC_3D_HEADPHONE_IOCTL:
if(rt_codec.number < 4)
break;
if (NULL == ioctl_ops->index_update_bits)
break;
mask1 = 0;
if(*buf != -1)
mask1 |= RT3261_3D_HP_MASK;
if(*(buf + 1) != -1)
mask1 |= RT3261_3D_BT_MASK;
if(*(buf + 2) != -1)
mask1 |= RT3261_3D_1F_MIX_MASK;
if(*(buf + 3) != -1)
mask1 |= RT3261_3D_HP_M_MASK;
snd_soc_update_bits(codec, RT3261_3D_HP, mask1,
*(buf)<<RT3261_3D_HP_SFT |
*(buf + 1) << RT3261_3D_BT_SFT |
*(buf + 2) << RT3261_3D_1F_MIX_SFT |
*(buf + 3) << RT3261_3D_HP_M_SFT);
if(*(buf + 4) != -1)
ioctl_ops->index_update_bits(codec,
0x59, 0x1f, *(buf+4));
break;
case RT_SET_CODEC_BASS_BACK_IOCTL:
if(rt_codec.number < 3)
break;
mask1 = 0;
if(*buf != -1)
mask1 |= RT3261_BB_MASK;
if(*(buf + 1) != -1)
mask1 |= RT3261_BB_CT_MASK;
if(*(buf + 2) != -1)
mask1 |= RT3261_G_BB_BST_MASK;
snd_soc_update_bits(codec, RT3261_BASE_BACK, mask1,
*(buf) << RT3261_BB_SFT |
*(buf + 1) << RT3261_BB_CT_SFT |
*(buf + 2) << RT3261_G_BB_BST_SFT);
break;
case RT_SET_CODEC_DIPOLE_SPK_IOCTL:
if(rt_codec.number < 2)
break;
if (NULL == ioctl_ops->index_update_bits)
break;
mask1 = 0;
if(*buf != -1)
mask1 |= RT3261_DP_SPK_MASK;
if(*(buf + 1) != -1)
mask1 |= RT3261_DP_ATT_MASK;
ioctl_ops->index_update_bits(codec, RT3261_DIP_SPK_INF,
mask1, *(buf) << RT3261_DP_SPK_SFT |
*(buf + 1) << RT3261_DP_ATT_SFT );
break;
case RT_SET_CODEC_DRC_AGC_ENABLE_IOCTL:
if(rt_codec.number < 2)
break;
set_drc_agc_enable(codec, *(buf), *(buf + 1));
break;
case RT_SET_CODEC_DRC_AGC_PAR_IOCTL:
if(rt_codec.number < 4)
break;
set_drc_agc_parameters(codec, *(buf), *(buf + 1),
*(buf + 2), *(buf + 3));
break;
case RT_SET_CODEC_DIGI_BOOST_GAIN_IOCTL:
if(rt_codec.number < 2)
break;
set_digital_boost_gain(codec, *(buf), *(buf + 1));
break;
case RT_SET_CODEC_NOISE_GATE_IOCTL:
if(rt_codec.number < 4)
break;
set_noise_gate(codec, *(buf), *(buf + 1),
*(buf + 2), *(buf + 3));
break;
case RT_SET_CODEC_DRC_AGC_COMP_IOCTL:
if(rt_codec.number < 2)
break;
set_drc_agc_compression(codec, *(buf), *(buf + 1));
break;
case RT_SET_CODEC_WNR_ENABLE_IOCTL:
if (NULL == ioctl_ops->index_update_bits)
break;
ioctl_ops->index_update_bits(codec, RT3261_WND_1,
RT3261_WND_MASK, *(buf) << RT3261_WND_SFT );
break;
case RT_GET_CODEC_DRC_AGC_ENABLE_IOCTL:
if(rt_codec.number < 2)
break;
get_drc_agc_enable(codec, (buf), (buf + 1));
if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
goto err;
break;
case RT_GET_CODEC_DRC_AGC_PAR_IOCTL:
if(rt_codec.number < 4)
break;
get_drc_agc_parameters(codec, (buf), (buf + 1),
(buf + 2), (buf + 3));
if (copy_to_user(rt_codec.buf, buf,
sizeof(*buf) * rt_codec.number))
goto err;
break;
case RT_GET_CODEC_DIGI_BOOST_GAIN_IOCTL:
if(rt_codec.number < 2)
break;
get_digital_boost_gain(codec, (buf), (buf + 1));
if (copy_to_user(rt_codec.buf, buf,
sizeof(*buf) * rt_codec.number))
goto err;
break;
case RT_GET_CODEC_NOISE_GATE_IOCTL:
if(rt_codec.number < 4)
break;
get_noise_gate(codec, (buf), (buf + 1), (buf + 2), (buf + 3));
if (copy_to_user(rt_codec.buf, buf,
sizeof(*buf) * rt_codec.number))
goto err;
break;
case RT_GET_CODEC_DRC_AGC_COMP_IOCTL:
if(rt_codec.number < 2)
break;
get_drc_agc_compression(codec, (buf), (buf + 1));
if (copy_to_user(rt_codec.buf, buf,
sizeof(*buf) * rt_codec.number))
goto err;
break;
case RT_GET_CODEC_SPK_VOL_IOCTL:
*buf = (snd_soc_read(codec, RT3261_SPK_VOL) & RT3261_L_VOL_MASK)
>> RT3261_L_VOL_SFT;
if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
goto err;
break;
case RT_GET_CODEC_MIC_GAIN_IOCTL:
*buf = (snd_soc_read(codec, RT3261_IN1_IN2) & RT3261_BST_MASK1)
>> RT3261_BST_SFT1;
if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
goto err;
break;
#if defined (CONFIG_SND_SOC_RT3261)
case RT_READ_CODEC_DSP_IOCTL:
case RT_WRITE_CODEC_DSP_IOCTL:
case RT_GET_CODEC_DSP_MODE_IOCTL:
return rt_codec_dsp_ioctl_common(hw, file, cmd, arg);
#endif
case RT_GET_CODEC_HWEQ_IOCTL:
case RT_GET_CODEC_3D_SPK_IOCTL:
case RT_GET_CODEC_MP3PLUS_IOCTL:
case RT_GET_CODEC_3D_HEADPHONE_IOCTL:
case RT_GET_CODEC_BASS_BACK_IOCTL:
case RT_GET_CODEC_DIPOLE_SPK_IOCTL:
default:
break;
}
kfree(buf);
return 0;
err:
kfree(buf);
return -EFAULT;
}
EXPORT_SYMBOL_GPL(rt3261_ioctl_common);

35
sound/soc/codecs/rt3261_ioctl.h
View File

@@ -1,35 +0,0 @@
/*
* rt3261_ioctl.h -- RT3261 ALSA SoC audio driver IO control
*
* Copyright 2012 Realtek Microelectronics
* Author: Bard <bardliao@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RT3261_IOCTL_H__
#define __RT3261_IOCTL_H__
#include <sound/hwdep.h>
#include <linux/ioctl.h>
enum {
NORMAL=0,
SPK,
HP,
MODE_NUM,
};
#define EQ_REG_NUM 19
typedef struct hweq_s {
unsigned int reg[EQ_REG_NUM];
unsigned int value[EQ_REG_NUM];
unsigned int ctrl;
} hweq_t;
int rt3261_ioctl_common(struct snd_hwdep *hw, struct file *file,
unsigned int cmd, unsigned long arg);
int rt3261_update_eqmode(struct snd_soc_codec *codec, int mode);
#endif /* __RT3261_IOCTL_H__ */

1855
sound/soc/codecs/rt5512.c
View File

File diff suppressed because it is too large Load Diff

50
sound/soc/codecs/rt5512.h
View File

@@ -1,50 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SND_SOC_CODEC_RT5512_H
#define __SND_SOC_CODEC_RT5512_H
#define RT5512_CODEC_NAME "rt5512-codec"
#define RT5512_DRV_VER "1.0.1_G"
#define RT5512_CLK_DIV_ID 1
#define FOR_MID 1
struct rt5512_codec_chip
{
struct device *dev;
struct i2c_client *client;
struct snd_soc_jack *rt_jack;
enum snd_soc_control_type control_type;
int curr_outpath;
int curr_inpath;
};
enum {
OFF,
RCV,
SPK_PATH,
HP_PATH,
HP_NO_MIC,
BT,
SPK_HP,
RING_SPK,
RING_HP,
RING_HP_NO_MIC,
RING_SPK_HP,
};
enum {
MIC_OFF,
Main_Mic,
Hands_Free_Mic,
BT_Sco_Mic,
};
#if 1
#define RT_DBG(format, args...) pr_info("%s:%s() line-%d: " format, RT5512_CODEC_NAME, __FUNCTION__, __LINE__, ##args)
#else
#define RT_DBG(format, args...)
#endif /* #if 1 */
#endif /* #ifndef __SND_SOC_CODEC_RT5512_H */

1234
sound/soc/codecs/rt5621.c
View File

File diff suppressed because it is too large Load Diff

515
sound/soc/codecs/rt5621.h
View File

@@ -1,515 +0,0 @@
/*
* rt5621.h -- RT5621 ALSA SoC audio driver
*
* Copyright 2011 Realtek Microelectronics
* Author: Johnny Hsu <johnnyhsu@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RT5621_H__
#define __RT5621_H__
#define RT5621_RESET 0X00 //RESET CODEC TO DEFAULT
#define RT5621_SPK_OUT_VOL 0X02 //SPEAKER OUT VOLUME
#define RT5621_HP_OUT_VOL 0X04 //HEADPHONE OUTPUT VOLUME
#define RT5621_MONO_AUX_OUT_VOL 0X06 //MONO OUTPUT/AUXOUT VOLUME
#define RT5621_AUXIN_VOL 0X08 //AUXIN VOLUME
#define RT5621_LINE_IN_VOL 0X0A //LINE IN VOLUME
#define RT5621_STEREO_DAC_VOL 0X0C //STEREO DAC VOLUME
#define RT5621_MIC_VOL 0X0E //MICROPHONE VOLUME
#define RT5621_MIC_ROUTING_CTRL 0X10 //MIC ROUTING CONTROL
#define RT5621_ADC_REC_GAIN 0X12 //ADC RECORD GAIN
#define RT5621_ADC_REC_MIXER 0X14 //ADC RECORD MIXER CONTROL
#define RT5621_SOFT_VOL_CTRL_TIME 0X16 //SOFT VOLUME CONTROL TIME
#define RT5621_OUTPUT_MIXER_CTRL 0X1C //OUTPUT MIXER CONTROL
#define RT5621_MIC_CTRL 0X22 //MICROPHONE CONTROL
#define RT5621_AUDIO_INTERFACE 0X34 //AUDIO INTERFACE
#define RT5621_STEREO_AD_DA_CLK_CTRL 0X36 //STEREO AD/DA CLOCK CONTROL
#define RT5621_COMPANDING_CTRL 0X38 //COMPANDING CONTROL
#define RT5621_PWR_MANAG_ADD1 0X3A //POWER MANAGMENT ADDITION 1
#define RT5621_PWR_MANAG_ADD2 0X3C //POWER MANAGMENT ADDITION 2
#define RT5621_PWR_MANAG_ADD3 0X3E //POWER MANAGMENT ADDITION 3
#define RT5621_ADD_CTRL_REG 0X40 //ADDITIONAL CONTROL REGISTER
#define RT5621_GLOBAL_CLK_CTRL_REG 0X42 //GLOBAL CLOCK CONTROL REGISTER
#define RT5621_PLL_CTRL 0X44 //PLL CONTROL
#define RT5621_GPIO_OUTPUT_PIN_CTRL 0X4A //GPIO OUTPUT PIN CONTROL
#define RT5621_GPIO_PIN_CONFIG 0X4C //GPIO PIN CONFIGURATION
#define RT5621_GPIO_PIN_POLARITY 0X4E //GPIO PIN POLARITY/TYPE
#define RT5621_GPIO_PIN_STICKY 0X50 //GPIO PIN STICKY
#define RT5621_GPIO_PIN_WAKEUP 0X52 //GPIO PIN WAKE UP
#define RT5621_GPIO_PIN_STATUS 0X54 //GPIO PIN STATUS
#define RT5621_GPIO_PIN_SHARING 0X56 //GPIO PIN SHARING
#define RT5621_OVER_TEMP_CURR_STATUS 0X58 //OVER TEMPERATURE AND CURRENT STATUS
#define RT5621_JACK_DET_CTRL 0X5A //JACK DETECT CONTROL REGISTER
#define RT5621_MISC_CTRL 0X5E //MISC CONTROL
#define RT5621_PSEDUEO_SPATIAL_CTRL 0X60 //PSEDUEO STEREO & SPATIAL EFFECT BLOCK CONTROL
#define RT5621_EQ_CTRL 0X62 //EQ CONTROL
#define RT5621_EQ_MODE_ENABLE 0X66 //EQ MODE CHANGE ENABLE
#define RT5621_AVC_CTRL 0X68 //AVC CONTROL
#define RT5621_HID_CTRL_INDEX 0X6A //HIDDEN CONTROL INDEX PORT
#define RT5621_HID_CTRL_DATA 0X6C //HIDDEN CONTROL DATA PORT
#define RT5621_VENDOR_ID1 0x7C //VENDOR ID1
#define RT5621_VENDOR_ID2 0x7E //VENDOR ID2
//global definition
#define RT_L_MUTE (0x1<<15) //MUTE LEFT CONTROL BIT
#define RT_L_ZC (0x1<<14) //LEFT ZERO CROSS CONTROL BIT
#define RT_L_SM (0x1<<13) //LEFT SOFTMUTE CONTROL BIT
#define RT_R_MUTE (0x1<<7) //MUTE RIGHT CONTROL BIT
#define RT_R_ZC (0x1<<6) //RIGHT ZERO CROSS CONTROL BIT
#define RT_R_SM (0x1<<5) //RIGHT SOFTMUTE CONTROL BIT
#define RT_M_HP_MIXER (0x1<<15) //Mute source to HP Mixer
#define RT_M_SPK_MIXER (0x1<<14) //Mute source to Speaker Mixer
#define RT_M_MONO_MIXER (0x1<<13) //Mute source to Mono Mixer
#define SPK_CLASS_AB 0
#define SPK_CLASS_D 1
//Mic Routing Control(0x10)
#define M_MIC1_TO_HP_MIXER (0x1<<15) //Mute MIC1 to HP mixer
#define M_MIC1_TO_SPK_MIXER (0x1<<14) //Mute MiC1 to SPK mixer
#define M_MIC1_TO_MONO_MIXER (0x1<<13) //Mute MIC1 to MONO mixer
#define MIC1_DIFF_INPUT_CTRL (0x1<<12) //MIC1 different input control
#define M_MIC2_TO_HP_MIXER (0x1<<7) //Mute MIC2 to HP mixer
#define M_MIC2_TO_SPK_MIXER (0x1<<6) //Mute MiC2 to SPK mixer
#define M_MIC2_TO_MONO_MIXER (0x1<<5) //Mute MIC2 to MONO mixer
#define MIC2_DIFF_INPUT_CTRL (0x1<<4) //MIC2 different input control
//ADC Record Gain(0x12)
#define M_ADC_L_TO_HP_MIXER (0x1<<15) //Mute left of ADC to HP Mixer
#define M_ADC_R_TO_HP_MIXER (0x1<<14) //Mute right of ADC to HP Mixer
#define M_ADC_L_TO_MONO_MIXER (0x1<<13) //Mute left of ADC to MONO Mixer
#define M_ADC_R_TO_MONO_MIXER (0x1<<12) //Mute right of ADC to MONO Mixer
#define ADC_L_GAIN_MASK (0x1f<<7) //ADC Record Gain Left channel Mask
#define ADC_L_ZC_DET (0x1<<6) //ADC Zero-Cross Detector Control
#define ADC_R_ZC_DET (0x1<<5) //ADC Zero-Cross Detector Control
#define ADC_R_GAIN_MASK (0x1f<<0) //ADC Record Gain Right channel Mask
//ADC Input Mixer Control(0x14)
#define M_MIC1_TO_ADC_L_MIXER (0x1<<14) //Mute mic1 to left channel of ADC mixer
#define M_MIC2_TO_ADC_L_MIXER (0x1<<13) //Mute mic2 to left channel of ADC mixer
#define M_LINEIN_L_TO_ADC_L_MIXER (0x1<<12) //Mute line In left channel to left channel of ADC mixer
#define M_AUXIN_L_TO_ADC_L_MIXER (0x1<<11) //Mute aux In left channel to left channel of ADC mixer
#define M_HPMIXER_L_TO_ADC_L_MIXER (0x1<<10) //Mute HP mixer left channel to left channel of ADC mixer
#define M_SPKMIXER_L_TO_ADC_L_MIXER (0x1<<9) //Mute SPK mixer left channel to left channel of ADC mixer
#define M_MONOMIXER_L_TO_ADC_L_MIXER (0x1<<8) //Mute MONO mixer left channel to left channel of ADC mixer
#define M_MIC1_TO_ADC_R_MIXER (0x1<<6) //Mute mic1 to right channel of ADC mixer
#define M_MIC2_TO_ADC_R_MIXER (0x1<<5) //Mute mic2 to right channel of ADC mixer
#define M_LINEIN_R_TO_ADC_R_MIXER (0x1<<4) //Mute lineIn right channel to right channel of ADC mixer
#define M_AUXIN_R_TO_ADC_R_MIXER (0x1<<3) //Mute aux In right channel to right channel of ADC mixer
#define M_HPMIXER_R_TO_ADC_R_MIXER (0x1<<2) //Mute HP mixer right channel to right channel of ADC mixer
#define M_SPKMIXER_R_TO_ADC_R_MIXER (0x1<<1) //Mute SPK mixer right channel to right channel of ADC mixer
#define M_MONOMIXER_R_TO_ADC_R_MIXER (0x1<<0) //Mute MONO mixer right channel to right channel of ADC mixer
//Output Mixer Control(0x1C)
#define SPKOUT_N_SOUR_MASK (0x3<<14)
#define SPKOUT_N_SOUR_LN (0x2<<14)
#define SPKOUT_N_SOUR_RP (0x1<<14)
#define SPKOUT_N_SOUR_RN (0x0<<14)
#define SPK_OUTPUT_CLASS_AB (0x0<<13)
#define SPK_OUTPUT_CLASS_D (0x1<<13)
#define SPK_CLASS_AB_S_AMP (0x0<<12)
#define SPK_CALSS_AB_W_AMP (0x1<<12)
#define SPKOUT_INPUT_SEL_MASK (0x3<<10)
#define SPKOUT_INPUT_SEL_MONOMIXER (0x3<<10)
#define SPKOUT_INPUT_SEL_SPKMIXER (0x2<<10)
#define SPKOUT_INPUT_SEL_HPMIXER (0x1<<10)
#define SPKOUT_INPUT_SEL_VMID (0x0<<10)
#define HPL_INPUT_SEL_HPLMIXER (0x1<<9)
#define HPR_INPUT_SEL_HPRMIXER (0x1<<8)
#define MONO_AUX_INPUT_SEL_MASK (0x3<<6)
#define MONO_AUX_INPUT_SEL_MONO (0x3<<6)
#define MONO_AUX_INPUT_SEL_SPK (0x2<<6)
#define MONO_AUX_INPUT_SEL_HP (0x1<<6)
#define MONO_AUX_INPUT_SEL_VMID (0x0<<6)
//Micphone Control define(0x22)
#define MIC1 1
#define MIC2 2
#define MIC_BIAS_90_PRECNET_AVDD 1
#define MIC_BIAS_75_PRECNET_AVDD 2
#define MIC1_BOOST_CTRL_MASK (0x3<<10)
#define MIC1_BOOST_CTRL_BYPASS (0x0<<10)
#define MIC1_BOOST_CTRL_20DB (0x1<<10)
#define MIC1_BOOST_CTRL_30DB (0x2<<10)
#define MIC1_BOOST_CTRL_40DB (0x3<<10)
#define MIC2_BOOST_CTRL_MASK (0x3<<8)
#define MIC2_BOOST_CTRL_BYPASS (0x0<<8)
#define MIC2_BOOST_CTRL_20DB (0x1<<8)
#define MIC2_BOOST_CTRL_30DB (0x2<<8)
#define MIC2_BOOST_CTRL_40DB (0x3<<8)
#define MICBIAS_VOLT_CTRL_MASK (0x1<<5)
#define MICBIAS_VOLT_CTRL_90P (0x0<<5)
#define MICBIAS_VOLT_CTRL_75P (0x1<<5)
#define MICBIAS_SHORT_CURR_DET_MASK (0x3)
#define MICBIAS_SHORT_CURR_DET_600UA (0x0)
#define MICBIAS_SHORT_CURR_DET_1200UA (0x1)
#define MICBIAS_SHORT_CURR_DET_1800UA (0x2)
//Audio Interface(0x34)
#define SDP_MASTER_MODE (0x0<<15) //Main I2S interface select Master mode
#define SDP_SLAVE_MODE (0x1<<15) //Main I2S interface select Slave mode
#define I2S_PCM_MODE (0x1<<14) //PCM 0:mode A ,1:mode B
#define MAIN_I2S_BCLK_POL_CTRL (0x1<<7) //0:Normal 1:Invert
#define ADC_DATA_L_R_SWAP (0x1<<5) //0:ADC data appear at left phase of LRCK
//1:ADC data appear at right phase of LRCK
#define DAC_DATA_L_R_SWAP (0x1<<4) //0:DAC data appear at left phase of LRCK
//1:DAC data appear at right phase of LRCK
//Data Length Slection
#define I2S_DL_MASK (0x3<<2) //main i2s Data Length mask
#define I2S_DL_16 (0x0<<2) //16 bits
#define I2S_DL_20 (0x1<<2) //20 bits
#define I2S_DL_24 (0x2<<2) //24 bits
#define I2S_DL_32 (0x3<<2) //32 bits
//PCM Data Format Selection
#define I2S_DF_MASK (0x3) //main i2s Data Format mask
#define I2S_DF_I2S (0x0) //I2S FORMAT
#define I2S_DF_RIGHT (0x1) //RIGHT JUSTIFIED format
#define I2S_DF_LEFT (0x2) //LEFT JUSTIFIED format
#define I2S_DF_PCM (0x3) //PCM format
//Stereo AD/DA Clock Control(0x36h)
#define I2S_PRE_DIV_MASK (0x7<<12)
#define I2S_PRE_DIV_1 (0x0<<12) //DIV 1
#define I2S_PRE_DIV_2 (0x1<<12) //DIV 2
#define I2S_PRE_DIV_4 (0x2<<12) //DIV 4
#define I2S_PRE_DIV_8 (0x3<<12) //DIV 8
#define I2S_PRE_DIV_16 (0x4<<12) //DIV 16
#define I2S_PRE_DIV_32 (0x5<<12) //DIV 32
#define I2S_SCLK_DIV_MASK (0x7<<9)
#define I2S_SCLK_DIV_1 (0x0<<9) //DIV 1
#define I2S_SCLK_DIV_2 (0x1<<9) //DIV 2
#define I2S_SCLK_DIV_3 (0x2<<9) //DIV 3
#define I2S_SCLK_DIV_4 (0x3<<9) //DIV 4
#define I2S_SCLK_DIV_6 (0x4<<9) //DIV 6
#define I2S_SCLK_DIV_8 (0x5<<9) //DIV 8
#define I2S_SCLK_DIV_12 (0x6<<9) //DIV 12
#define I2S_SCLK_DIV_16 (0x7<<9) //DIV 16
#define I2S_WCLK_DIV_PRE_MASK (0xF<<5)
#define I2S_WCLK_PRE_DIV_1 (0x0<<5) //DIV 1
#define I2S_WCLK_PRE_DIV_2 (0x1<<5) //DIV 2
#define I2S_WCLK_PRE_DIV_3 (0x2<<5) //DIV 3
#define I2S_WCLK_PRE_DIV_4 (0x3<<5) //DIV 4
#define I2S_WCLK_PRE_DIV_5 (0x4<<5) //DIV 5
#define I2S_WCLK_PRE_DIV_6 (0x5<<5) //DIV 6
#define I2S_WCLK_PRE_DIV_7 (0x6<<5) //DIV 7
#define I2S_WCLK_PRE_DIV_8 (0x7<<5) //DIV 8
//........................
#define I2S_WCLK_DIV_MASK (0x7<<2)
#define I2S_WCLK_DIV_2 (0x0<<2) //DIV 2
#define I2S_WCLK_DIV_4 (0x1<<2) //DIV 4
#define I2S_WCLK_DIV_8 (0x2<<2) //DIV 8
#define I2S_WCLK_DIV_16 (0x3<<2) //DIV 16
#define I2S_WCLK_DIV_32 (0x4<<2) //DIV 32
#define ADDA_FILTER_CLK_SEL_256FS (0<<1) //256FS
#define ADDA_FILTER_CLK_SEL_384FS (1<<1) //384FS
#define ADDA_OSR_SEL_64FS (0) //64FS
#define ADDA_OSR_SEL_128FS (1) //128FS
//Power managment addition 1 (0x3A),0:Disable,1:Enable
#define PWR_MAIN_I2S_EN (0x1<<15)
#define PWR_ZC_DET_PD_EN (0x1<<14)
#define PWR_MIC1_BIAS_EN (0x1<<11)
#define PWR_SHORT_CURR_DET_EN (0x1<<10)
#define PWR_SOFTGEN_EN (0x1<<8)
#define PWR_DEPOP_BUF_HP (0x1<<6)
#define PWR_HP_OUT_AMP (0x1<<5)
#define PWR_HP_OUT_ENH_AMP (0x1<<4)
#define PWR_DEPOP_BUF_AUX (0x1<<2)
#define PWR_AUX_OUT_AMP (0x1<<1)
#define PWR_AUX_OUT_ENH_AMP (0x1)
//Power managment addition 2(0x3C),0:Disable,1:Enable
#define PWR_CLASS_AB (0x1<<15)
#define PWR_CLASS_D (0x1<<14)
#define PWR_VREF (0x1<<13)
#define PWR_PLL (0x1<<12)
#define PWR_DAC_REF_CIR (0x1<<10)
#define PWR_L_DAC_CLK (0x1<<9)
#define PWR_R_DAC_CLK (0x1<<8)
#define PWR_L_ADC_CLK_GAIN (0x1<<7)
#define PWR_R_ADC_CLK_GAIN (0x1<<6)
#define PWR_L_HP_MIXER (0x1<<5)
#define PWR_R_HP_MIXER (0x1<<4)
#define PWR_SPK_MIXER (0x1<<3)
#define PWR_MONO_MIXER (0x1<<2)
#define PWR_L_ADC_REC_MIXER (0x1<<1)
#define PWR_R_ADC_REC_MIXER (0x1)
//Power managment addition 3(0x3E),0:Disable,1:Enable
#define PWR_MAIN_BIAS (0x1<<15)
#define PWR_AUXOUT_L_VOL_AMP (0x1<<14)
#define PWR_AUXOUT_R_VOL_AMP (0x1<<13)
#define PWR_SPK_OUT (0x1<<12)
#define PWR_HP_L_OUT_VOL (0x1<<10)
#define PWR_HP_R_OUT_VOL (0x1<<9)
#define PWR_LINEIN_L_VOL (0x1<<7)
#define PWR_LINEIN_R_VOL (0x1<<6)
#define PWR_AUXIN_L_VOL (0x1<<5)
#define PWR_AUXIN_R_VOL (0x1<<4)
#define PWR_MIC1_FUN_CTRL (0x1<<3)
#define PWR_MIC2_FUN_CTRL (0x1<<2)
#define PWR_MIC1_BOOST_MIXER (0x1<<1)
#define PWR_MIC2_BOOST_MIXER (0x1)
//Additional Control Register(0x40)
#define AUXOUT_SEL_DIFF (0x1<<15) //Differential Mode
#define AUXOUT_SEL_SE (0x1<<15) //Single-End Mode
#define SPK_AB_AMP_CTRL_MASK (0x7<<12)
#define SPK_AB_AMP_CTRL_RATIO_225 (0x0<<12) //2.25 Vdd
#define SPK_AB_AMP_CTRL_RATIO_200 (0x1<<12) //2.00 Vdd
#define SPK_AB_AMP_CTRL_RATIO_175 (0x2<<12) //1.75 Vdd
#define SPK_AB_AMP_CTRL_RATIO_150 (0x3<<12) //1.50 Vdd
#define SPK_AB_AMP_CTRL_RATIO_125 (0x4<<12) //1.25 Vdd
#define SPK_AB_AMP_CTRL_RATIO_100 (0x5<<12) //1.00 Vdd
#define SPK_D_AMP_CTRL_MASK (0x3<<10)
#define SPK_D_AMP_CTRL_RATIO_175 (0x0<<10) //1.75 Vdd
#define SPK_D_AMP_CTRL_RATIO_150 (0x1<<10) //1.50 Vdd
#define SPK_D_AMP_CTRL_RATIO_125 (0x2<<10) //1.25 Vdd
#define SPK_D_AMP_CTRL_RATIO_100 (0x3<<10) //1.00 Vdd
#define STEREO_DAC_HI_PASS_FILTER_EN (0x1<<9) //Stereo DAC high pass filter enable
#define STEREO_ADC_HI_PASS_FILTER_EN (0x1<<8) //Stereo ADC high pass filter enable
#define DIG_VOL_BOOST_MASK (0x3<<4) //Digital volume Boost mask
#define DIG_VOL_BOOST_0DB (0x0<<4) //Digital volume Boost 0DB
#define DIG_VOL_BOOST_6DB (0x1<<4) //Digital volume Boost 6DB
#define DIG_VOL_BOOST_12DB (0x2<<4) //Digital volume Boost 12DB
#define DIG_VOL_BOOST_18DB (0x3<<4) //Digital volume Boost 18DB
//Global Clock Control Register(0x42)
#define SYSCLK_SOUR_SEL_MASK (0x1<<15)
#define SYSCLK_SOUR_SEL_MCLK (0x0<<15) //system Clock source from MCLK
#define SYSCLK_SOUR_SEL_PLL (0x1<<15) //system Clock source from PLL
#define PLLCLK_SOUR_SEL_MCLK (0x0<<14) //PLL clock source from MCLK
#define PLLCLK_SOUR_SEL_BITCLK (0x1<<14) //PLL clock source from BITCLK
#define PLLCLK_DIV_RATIO_MASK (0x3<<1)
#define PLLCLK_DIV_RATIO_DIV1 (0x0<<1) //DIV 1
#define PLLCLK_DIV_RATIO_DIV2 (0x1<<1) //DIV 2
#define PLLCLK_DIV_RATIO_DIV4 (0x2<<1) //DIV 4
#define PLLCLK_DIV_RATIO_DIV8 (0x3<<1) //DIV 8
#define PLLCLK_PRE_DIV1 (0x0) //DIV 1
#define PLLCLK_PRE_DIV2 (0x1) //DIV 2
//PLL Control(0x44)
#define PLL_CTRL_M_VAL(m) ((m)&0xf)
#define PLL_CTRL_K_VAL(k) (((k)&0x7)<<4)
#define PLL_CTRL_N_VAL(n) (((n)&0xff)<<8)
//GPIO Pin Configuration(0x4C)
#define GPIO_PIN_MASK (0x1<<1)
#define GPIO_PIN_SET_INPUT (0x1<<1)
#define GPIO_PIN_SET_OUTPUT (0x0<<1)
//Pin Sharing(0x56)
#define LINEIN_L_PIN_SHARING (0x1<<15)
#define LINEIN_L_PIN_AS_LINEIN_L (0x0<<15)
#define LINEIN_L_PIN_AS_JD1 (0x1<<15)
#define LINEIN_R_PIN_SHARING (0x1<<14)
#define LINEIN_R_PIN_AS_LINEIN_R (0x0<<14)
#define LINEIN_R_PIN_AS_JD2 (0x1<<14)
#define GPIO_PIN_SHARING (0x3)
#define GPIO_PIN_AS_GPIO (0x0)
#define GPIO_PIN_AS_IRQOUT (0x1)
#define GPIO_PIN_AS_PLLOUT (0x3)
//Jack Detect Control Register(0x5A)
#define JACK_DETECT_MASK (0x3<<14)
#define JACK_DETECT_USE_JD2 (0x3<<14)
#define JACK_DETECT_USE_JD1 (0x2<<14)
#define JACK_DETECT_USE_GPIO (0x1<<14)
#define JACK_DETECT_OFF (0x0<<14)
#define SPK_EN_IN_HI (0x1<<11)
#define AUX_R_EN_IN_HI (0x1<<10)
#define AUX_L_EN_IN_HI (0x1<<9)
#define HP_EN_IN_HI (0x1<<8)
#define SPK_EN_IN_LO (0x1<<7)
#define AUX_R_EN_IN_LO (0x1<<6)
#define AUX_L_EN_IN_LO (0x1<<5)
#define HP_EN_IN_LO (0x1<<4)
////MISC CONTROL(0x5E)
#define DISABLE_FAST_VREG (0x1<<15)
#define SPK_CLASS_AB_OC_PD (0x1<<13)
#define SPK_CLASS_AB_OC_DET (0x1<<12)
#define HP_DEPOP_MODE3_EN (0x1<<10)
#define HP_DEPOP_MODE2_EN (0x1<<9)
#define HP_DEPOP_MODE1_EN (0x1<<8)
#define AUXOUT_DEPOP_MODE3_EN (0x1<<6)
#define AUXOUT_DEPOP_MODE2_EN (0x1<<5)
#define AUXOUT_DEPOP_MODE1_EN (0x1<<4)
#define M_DAC_L_INPUT (0x1<<3)
#define M_DAC_R_INPUT (0x1<<2)
#define IRQOUT_INV_CTRL (0x1<<0)
//Psedueo Stereo & Spatial Effect Block Control(0x60)
#define SPATIAL_CTRL_EN (0x1<<15)
#define ALL_PASS_FILTER_EN (0x1<<14)
#define PSEUDO_STEREO_EN (0x1<<13)
#define STEREO_EXPENSION_EN (0x1<<12)
#define GAIN_3D_PARA_L_MASK (0x7<<9)
#define GAIN_3D_PARA_L_1_00 (0x0<<9)
#define GAIN_3D_PARA_L_1_25 (0x1<<9)
#define GAIN_3D_PARA_L_1_50 (0x2<<9)
#define GAIN_3D_PARA_L_1_75 (0x3<<9)
#define GAIN_3D_PARA_L_2_00 (0x4<<9)
#define GAIN_3D_PARA_R_MASK (0x7<<6)
#define GAIN_3D_PARA_R_1_00 (0x0<<6)
#define GAIN_3D_PARA_R_1_25 (0x1<<6)
#define GAIN_3D_PARA_R_1_50 (0x2<<6)
#define GAIN_3D_PARA_R_1_75 (0x3<<6)
#define GAIN_3D_PARA_R_2_00 (0x4<<6)
#define RATIO_3D_L_MASK (0x3<<4)
#define RATIO_3D_L_0_0 (0x0<<4)
#define RATIO_3D_L_0_66 (0x1<<4)
#define RATIO_3D_L_1_0 (0x2<<4)
#define RATIO_3D_R_MASK (0x3<<2)
#define RATIO_3D_R_0_0 (0x0<<2)
#define RATIO_3D_R_0_66 (0x1<<2)
#define RATIO_3D_R_1_0 (0x2<<2)
#define APF_MASK (0x3)
#define APF_FOR_48K (0x3)
#define APF_FOR_44_1K (0x2)
#define APF_FOR_32K (0x1)
//EQ CONTROL(0x62)
#define EN_HW_EQ_BLK (0x1<<15) //HW EQ block control
#define EN_HW_EQ_HPF_MODE (0x1<<14) //High Frequency shelving filter mode
#define EN_HW_EQ_SOUR (0x1<<11) //0:DAC PATH,1:ADC PATH
#define EN_HW_EQ_HPF (0x1<<4) //EQ High Pass Filter Control
#define EN_HW_EQ_BP3 (0x1<<3) //EQ Band-3 Control
#define EN_HW_EQ_BP2 (0x1<<2) //EQ Band-2 Control
#define EN_HW_EQ_BP1 (0x1<<1) //EQ Band-1 Control
#define EN_HW_EQ_LPF (0x1<<0) //EQ Low Pass Filter Control
//EQ Mode Change Enable(0x66)
#define EQ_HPF_CHANGE_EN (0x1<<4) //EQ High Pass Filter Mode Change Enable
#define EQ_BP3_CHANGE_EN (0x1<<3) //EQ Band-3 Pass Filter Mode Change Enable
#define EQ_BP2_CHANGE_EN (0x1<<2) //EQ Band-2 Pass Filter Mode Change Enable
#define EQ_BP1_CHANGE_EN (0x1<<1) //EQ Band-1 Pass Filter Mode Change Enable
#define EQ_LPF_CHANGE_EN (0x1<<0) //EQ Low Pass Filter Mode Change Enable
//AVC Control(0x68)
#define AVC_ENABLE (0x1<<15)
#define AVC_TARTGET_SEL_MASK (0x1<<14)
#define AVC_TARTGET_SEL_R (0x1<<14)
#define AVC_TARTGET_SEL_L (0x0<<14)
#define RT5621_PLL_FR_MCLK 0
#define RT5621_PLL_FR_BCLK 1
#define REALTEK_HWDEP 0
//WaveOut channel for realtek codec
enum
{
RT_WAVOUT_SPK =(0x1<<0),
RT_WAVOUT_SPK_R =(0x1<<1),
RT_WAVOUT_SPK_L =(0x1<<2),
RT_WAVOUT_HP =(0x1<<3),
RT_WAVOUT_HP_R =(0x1<<4),
RT_WAVOUT_HP_L =(0x1<<5),
RT_WAVOUT_MONO =(0x1<<6),
RT_WAVOUT_AUXOUT =(0x1<<7),
RT_WAVOUT_AUXOUT_R =(0x1<<8),
RT_WAVOUT_AUXOUT_L =(0x1<<9),
RT_WAVOUT_LINEOUT =(0x1<<10),
RT_WAVOUT_LINEOUT_R =(0x1<<11),
RT_WAVOUT_LINEOUT_L =(0x1<<12),
RT_WAVOUT_DAC =(0x1<<13),
RT_WAVOUT_ALL_ON =(0x1<<14),
};
//WaveIn channel for realtek codec
enum
{
RT_WAVIN_R_MONO_MIXER =(0x1<<0),
RT_WAVIN_R_SPK_MIXER =(0x1<<1),
RT_WAVIN_R_HP_MIXER =(0x1<<2),
RT_WAVIN_R_PHONE =(0x1<<3),
RT_WAVIN_R_AUXIN =(0x1<<3),
RT_WAVIN_R_LINE_IN =(0x1<<4),
RT_WAVIN_R_MIC2 =(0x1<<5),
RT_WAVIN_R_MIC1 =(0x1<<6),
RT_WAVIN_L_MONO_MIXER =(0x1<<8),
RT_WAVIN_L_SPK_MIXER =(0x1<<9),
RT_WAVIN_L_HP_MIXER =(0x1<<10),
RT_WAVIN_L_PHONE =(0x1<<11),
RT_WAVIN_L_AUXIN =(0x1<<11),
RT_WAVIN_L_LINE_IN =(0x1<<12),
RT_WAVIN_L_MIC2 =(0x1<<13),
RT_WAVIN_L_MIC1 =(0x1<<14),
};
enum
{
POWER_STATE_D0=0,
POWER_STATE_D1,
POWER_STATE_D1_PLAYBACK,
POWER_STATE_D1_RECORD,
POWER_STATE_D2,
POWER_STATE_D2_PLAYBACK,
POWER_STATE_D2_RECORD,
POWER_STATE_D3,
POWER_STATE_D4
};
#if REALTEK_HWDEP
struct rt56xx_reg_state
{
unsigned int reg_index;
unsigned int reg_value;
};
struct rt56xx_cmd
{
size_t number;
struct rt56xx_reg_state __user *buf;
};
enum
{
RT_READ_CODEC_REG_IOCTL = _IOR('R', 0x01, struct rt56xx_cmd),
RT_READ_ALL_CODEC_REG_IOCTL = _IOR('R', 0x02, struct rt56xx_cmd),
RT_WRITE_CODEC_REG_IOCTL = _IOW('R', 0x03, struct rt56xx_cmd),
};
#endif
#endif /* __RT5621_H__ */

206
sound/soc/codecs/rt5623.c
View File

@@ -1,206 +0,0 @@
/*
* rt5623.c -- RT5623 ALSA SoC audio codec driver
*
* Copyright 2011 Realtek Semiconductor Corp.
* Author: Johnny Hsu <johnnyhsu@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include "rt5623.h"
#define MODEM_ON 1
#define MODEM_OFF 0
static struct i2c_client *i2c_client;
static int status;
static int codec_write(struct i2c_client *client, unsigned int reg,
unsigned int value)
{
u8 data[3];
data[0] = reg;
data[1] = (value >> 8) & 0xff;
data[2] = value & 0xff;
//printk("%s: reg=0x%x value=0x%x\n",__func__,reg,value);
if (i2c_master_send(client, data, 3) == 3)
return 0;
else
return -EIO;
}
static unsigned int codec_read(struct i2c_client *client,
unsigned int r)
{
struct i2c_msg xfer[2];
u8 reg = r;
u16 data;
int ret;
/* Write register */
xfer[0].addr = client->addr;
xfer[0].flags = 0;
xfer[0].len = 1;
xfer[0].buf = &reg;
xfer[0].scl_rate = 100 * 1000;
/* Read data */
xfer[1].addr = client->addr;
xfer[1].flags = I2C_M_RD;
xfer[1].len = 2;
xfer[1].buf = (u8 *)&data;
xfer[1].scl_rate = 100 * 1000;
ret = i2c_transfer(client->adapter, xfer, 2);
if (ret != 2) {
dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
return 0;
}
//printk("%s: reg=0x%x value=0x%x\n",__func__,reg,(data >> 8) | ((data & 0xff) << 8));
return (data >> 8) | ((data & 0xff) << 8);
}
struct rt5623_reg {
u8 reg_index;
u16 reg_value;
};
static struct rt5623_reg init_data[] = {
{RT5623_PWR_MANAG_ADD3 , 0x8000},
{RT5623_PWR_MANAG_ADD2 , 0x2000},
{RT5623_LINE_IN_VOL , 0xa808},
{RT5623_STEREO_DAC_VOL , 0x6808},
{RT5623_OUTPUT_MIXER_CTRL , 0x1400},
{RT5623_ADC_REC_GAIN , 0xf58b},
{RT5623_ADC_REC_MIXER , 0x7d7d},
{RT5623_AUDIO_INTERFACE , 0x8083},
{RT5623_STEREO_AD_DA_CLK_CTRL , 0x0a2d},
{RT5623_PWR_MANAG_ADD1 , 0x8000},
{RT5623_PWR_MANAG_ADD2 , 0xb7f3},
{RT5623_PWR_MANAG_ADD3 , 0x90c0},
{RT5623_SPK_OUT_VOL , 0x0000},
{RT5623_PLL_CTRL , 0x481f},
{RT5623_GLOBAL_CLK_CTRL_REG , 0x8000},
{RT5623_STEREO_AD_DA_CLK_CTRL , 0x3a2d},
};
#define RT5623_INIT_REG_NUM ARRAY_SIZE(init_data)
static int rt5623_reg_init(struct i2c_client *client)
{
int i;
for (i = 0; i < RT5623_INIT_REG_NUM; i++)
codec_write(client, init_data[i].reg_index,
init_data[i].reg_value);
return 0;
}
static int rt5623_reset(struct i2c_client *client)
{
return codec_write(client, RT5623_RESET, 0);
}
void rt5623_on(void)
{
if(status == MODEM_OFF)
{
printk("enter %s\n",__func__);
rt5623_reset(i2c_client);
rt5623_reg_init(i2c_client);
status = MODEM_ON;
}
}
EXPORT_SYMBOL(rt5623_on);
void rt5623_off(void)
{
if(status == MODEM_ON)
{
printk("enter %s\n",__func__);
codec_write(i2c_client, RT5623_SPK_OUT_VOL, 0x8080);
rt5623_reset(i2c_client);
codec_write(i2c_client, RT5623_PWR_MANAG_ADD3, 0x0000);
codec_write(i2c_client, RT5623_PWR_MANAG_ADD2, 0x0000);
codec_write(i2c_client, RT5623_PWR_MANAG_ADD1, 0x0000);
status = MODEM_OFF;
}
}
EXPORT_SYMBOL(rt5623_off);
static const struct i2c_device_id rt5623_i2c_id[] = {
{ "rt5623", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, rt5623_i2c_id);
static int rt5623_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
pr_info("%s(%d)\n", __func__, __LINE__);
i2c_client = i2c;
rt5623_reset(i2c);
status = MODEM_ON;
rt5623_off( );
return 0;
}
static int rt5623_i2c_remove(struct i2c_client *i2c)
{
return 0;
}
struct i2c_driver rt5623_i2c_driver = {
.driver = {
.name = "rt5623",
.owner = THIS_MODULE,
},
.probe = rt5623_i2c_probe,
.remove = rt5623_i2c_remove,
.id_table = rt5623_i2c_id,
};
static int __init rt5623_modinit(void)
{
return i2c_add_driver(&rt5623_i2c_driver);
}
late_initcall(rt5623_modinit);
static void __exit rt5623_modexit(void)
{
i2c_del_driver(&rt5623_i2c_driver);
}
module_exit(rt5623_modexit);
MODULE_DESCRIPTION("ASoC RT5623 driver");
MODULE_AUTHOR("Johnny Hsu <johnnyhsu@realtek.com>");
MODULE_LICENSE("GPL");

506
sound/soc/codecs/rt5623.h
View File

@@ -1,506 +0,0 @@
/*
* rt5623.h -- RT5623 ALSA SoC audio driver
*
* Copyright 2011 Realtek Microelectronics
* Author: Johnny Hsu <johnnyhsu@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RT5623_H__
#define __RT5623_H__
#define RT5623_RESET 0x00
#define RT5623_SPK_OUT_VOL 0x02
#define RT5623_HP_OUT_VOL 0x04
#define RT5623_MONO_AUX_OUT_VOL 0x06
#define RT5623_AUXIN_VOL 0x08
#define RT5623_LINE_IN_VOL 0x0a
#define RT5623_STEREO_DAC_VOL 0x0c
#define RT5623_MIC_VOL 0x0e
#define RT5623_MIC_ROUTING_CTRL 0x10
#define RT5623_ADC_REC_GAIN 0x12
#define RT5623_ADC_REC_MIXER 0x14
#define RT5623_SOFT_VOL_CTRL_TIME 0x16
#define RT5623_OUTPUT_MIXER_CTRL 0x1c
#define RT5623_MIC_CTRL 0x22
#define RT5623_AUDIO_INTERFACE 0x34
#define RT5623_STEREO_AD_DA_CLK_CTRL 0x36
#define RT5623_COMPANDING_CTRL 0x38
#define RT5623_PWR_MANAG_ADD1 0x3a
#define RT5623_PWR_MANAG_ADD2 0x3c
#define RT5623_PWR_MANAG_ADD3 0x3e
#define RT5623_ADD_CTRL_REG 0x40
#define RT5623_GLOBAL_CLK_CTRL_REG 0x42
#define RT5623_PLL_CTRL 0x44
#define RT5623_GPIO_OUTPUT_PIN_CTRL 0x4a
#define RT5623_GPIO_PIN_CONFIG 0x4c
#define RT5623_GPIO_PIN_POLARITY 0x4e
#define RT5623_GPIO_PIN_STICKY 0x50
#define RT5623_GPIO_PIN_WAKEUP 0x52
#define RT5623_GPIO_PIN_STATUS 0x54
#define RT5623_GPIO_PIN_SHARING 0x56
#define RT5623_OVER_TEMP_CURR_STATUS 0x58
#define RT5623_JACK_DET_CTRL 0x5a
#define RT5623_MISC_CTRL 0x5e
#define RT5623_PSEDUEO_SPATIAL_CTRL 0x60
#define RT5623_EQ_CTRL 0x62
#define RT5623_EQ_MODE_ENABLE 0x66
#define RT5623_AVC_CTRL 0x68
#define RT5623_HID_CTRL_INDEX 0x6a
#define RT5623_HID_CTRL_DATA 0x6c
#define RT5623_VENDOR_ID1 0x7c
#define RT5623_VENDOR_ID2 0x7e
/* global definition */
#define RT5623_L_MUTE (0x1 << 15)
#define RT5623_L_MUTE_SFT 15
#define RT5623_L_ZC (0x1 << 14)
#define RT5623_L_SM (0x1 << 13)
#define RT5623_L_VOL_MASK (0x1f << 8)
#define RT5623_L_VOL_SFT 8
#define RT5623_ADCL_VOL_SFT 7
#define RT5623_R_MUTE (0x1 << 7)
#define RT5623_R_MUTE_SFT 7
#define RT5623_R_ZC (0x1 << 6)
#define RT5623_R_VOL_MASK (0x1f)
#define RT5623_R_VOL_SFT 0
#define RT5623_M_HPMIX (0x1 << 15)
#define RT5623_M_SPKMIX (0x1 << 14)
#define RT5623_M_MONOMIX (0x1 << 13)
#define RT5623_SPK_CLASS_AB 0
#define RT5623_SPK_CLASS_D 1
/* AUXIN Volume (0x08) */
#define RT5623_M_AXI_TO_HPM (0x1 << 15)
#define RT5623_M_AXI_TO_HPM_SFT 15
#define RT5623_M_AXI_TO_SPKM (0x1 << 14)
#define RT5623_M_AXI_TO_SPKM_SFT 14
#define RT5623_M_AXI_TO_MOM (0x1 << 13)
#define RT5623_M_AXI_TO_MOM_SFT 13
/* LINE_IN Volume (0x0a) */
#define RT5623_M_LINEIN_TO_HPM (0x1 << 15)
#define RT5623_M_LINEIN_TO_HPM_SFT 15
#define RT5623_M_LINEIN_TO_SPKM (0x1 << 14)
#define RT5623_M_LINEIN_TO_SPKM_SFT 14
#define RT5623_M_LINEIN_TO_MOM (0x1 << 13)
#define RT5623_M_LINEIN_TO_MOM_SFT 13
/* Stereo DAC Volume (0x0c) */
#define RT5623_M_DAC_TO_HPM (0x1 << 15)
#define RT5623_M_DAC_TO_HPM_SFT 15
#define RT5623_M_DAC_TO_SPKM (0x1 << 14)
#define RT5623_M_DAC_TO_SPKM_SFT 14
#define RT5623_M_DAC_TO_MOM (0x1 << 13)
#define RT5623_M_DAC_TO_MOM_SFT 13
/* Mic Routing Control(0x10) */
#define RT5623_M_MIC1_TO_HP_MIXER (0x1 << 15)
#define RT5623_M_MIC1_TO_HP_MIXER_SFT 15
#define RT5623_M_MIC1_TO_SPK_MIXER (0x1 << 14)
#define RT5623_M_MIC1_TO_SPK_MIXER_SFT 14
#define RT5623_M_MIC1_TO_MONO_MIXER (0x1 << 13)
#define RT5623_M_MIC1_TO_MONO_MIXER_SFT 13
#define RT5623_MIC1_DIFF_INPUT_CTRL (0x1 << 12)
#define RT5623_MIC1_DIFF_INPUT_CTRL_SFT 12
#define RT5623_M_MIC2_TO_HP_MIXER (0x1 << 7)
#define RT5623_M_MIC2_TO_HP_MIXER_SFT 7
#define RT5623_M_MIC2_TO_SPK_MIXER (0x1 << 6)
#define RT5623_M_MIC2_TO_SPK_MIXER_SFT 6
#define RT5623_M_MIC2_TO_MONO_MIXER (0x1 << 5)
#define RT5623_M_MIC2_TO_MONO_MIXER_SFT 5
#define RT5623_MIC2_DIFF_INPUT_CTRL (0x1 << 4)
#define RT5623_MIC2_DIFF_INPUT_CTRL_SFT 4
/* ADC Record Gain (0x12) */
#define RT5623_M_ADC_L_TO_HP_MIXER (0x1 << 15)
#define RT5623_M_ADC_L_TO_HP_MIXER_SFT 15
#define RT5623_M_ADC_R_TO_HP_MIXER (0x1 << 14)
#define RT5623_M_ADC_R_TO_HP_MIXER_SFT 14
#define RT5623_M_ADC_L_TO_MONO_MIXER (0x1 << 13)
#define RT5623_M_ADC_L_TO_MONO_MIXER_SFT 13
#define RT5623_M_ADC_R_TO_MONO_MIXER (0x1 << 12)
#define RT5623_M_ADC_R_TO_MONO_MIXER_SFT 12
#define RT5623_ADC_L_GAIN_MASK (0x1f << 7)
#define RT5623_ADC_L_ZC_DET (0x1 << 6)
#define RT5623_ADC_R_ZC_DET (0x1 << 5)
#define RT5623_ADC_R_GAIN_MASK (0x1f << 0)
/* ADC Input Mixer Control (0x14) */
#define RT5623_M_MIC1_TO_ADC_L_MIXER (0x1 << 14)
#define RT5623_M_MIC1_TO_ADC_L_MIXER_SFT 14
#define RT5623_M_MIC2_TO_ADC_L_MIXER (0x1 << 13)
#define RT5623_M_MIC2_TO_ADC_L_MIXER_SFT 13
#define RT5623_M_LINEIN_L_TO_ADC_L_MIXER (0x1 << 12)
#define RT5623_M_LINEIN_L_TO_ADC_L_MIXER_SFT 12
#define RT5623_M_AUXIN_L_TO_ADC_L_MIXER (0x1 << 11)
#define RT5623_M_AUXIN_L_TO_ADC_L_MIXER_SFT 11
#define RT5623_M_HPMIXER_L_TO_ADC_L_MIXER (0x1 << 10)
#define RT5623_M_HPMIXER_L_TO_ADC_L_MIXER_SFT 10
#define RT5623_M_SPKMIXER_L_TO_ADC_L_MIXER (0x1 << 9)
#define RT5623_M_SPKMIXER_L_TO_ADC_L_MIXER_SFT 9
#define RT5623_M_MONOMIXER_L_TO_ADC_L_MIXER (0x1 << 8)
#define RT5623_M_MONOMIXER_L_TO_ADC_L_MIXER_SFT 8
#define RT5623_M_MIC1_TO_ADC_R_MIXER (0x1 << 6)
#define RT5623_M_MIC1_TO_ADC_R_MIXER_SFT 6
#define RT5623_M_MIC2_TO_ADC_R_MIXER (0x1 << 5)
#define RT5623_M_MIC2_TO_ADC_R_MIXER_SFT 5
#define RT5623_M_LINEIN_R_TO_ADC_R_MIXER (0x1 << 4)
#define RT5623_M_LINEIN_R_TO_ADC_R_MIXER_SFT 4
#define RT5623_M_AUXIN_R_TO_ADC_R_MIXER (0x1 << 3)
#define RT5623_M_AUXIN_R_TO_ADC_R_MIXER_SFT 3
#define RT5623_M_HPMIXER_R_TO_ADC_R_MIXER (0x1 << 2)
#define RT5623_M_HPMIXER_R_TO_ADC_R_MIXER_SFT 2
#define RT5623_M_SPKMIXER_R_TO_ADC_R_MIXER (0x1 << 1)
#define RT5623_M_SPKMIXER_R_TO_ADC_R_MIXER_SFT 1
#define RT5623_M_MONOMIXER_R_TO_ADC_R_MIXER (0x1 << 0)
#define RT5623_M_MONOMIXER_R_TO_ADC_R_MIXER_SFT 0
/* Output Mixer Control(0x1c) */
#define RT5623_SPKOUT_N_SOUR_MASK (0x3 << 14)
#define RT5623_SPKOUT_N_SOUR_SFT 14
#define RT5623_SPKOUT_N_SOUR_LN (0x2 << 14)
#define RT5623_SPKOUT_N_SOUR_RP (0x1 << 14)
#define RT5623_SPKOUT_N_SOUR_RN (0x0 << 14)
#define RT5623_SPK_OUTPUT_CLASS_MASK (0x1 << 13)
#define RT5623_SPK_OUTPUT_CLASS_SFT 13
#define RT5623_SPK_OUTPUT_CLASS_AB (0x0 << 13)
#define RT5623_SPK_OUTPUT_CLASS_D (0x1 << 13)
#define RT5623_SPK_CLASS_AB_S_AMP (0x0 << 12)
#define RT5623_SPK_CALSS_AB_W_AMP (0x1 << 12)
#define RT5623_SPKOUT_INPUT_SEL_MASK (0x3 << 10)
#define RT5623_SPKOUT_INPUT_SEL_SFT 10
#define RT5623_SPKOUT_INPUT_SEL_MONOMIXER (0x3 << 10)
#define RT5623_SPKOUT_INPUT_SEL_SPKMIXER (0x2 << 10)
#define RT5623_SPKOUT_INPUT_SEL_HPMIXER (0x1 << 10)
#define RT5623_SPKOUT_INPUT_SEL_VMID (0x0 << 10)
#define RT5623_HPL_INPUT_SEL_HPLMIXER_MASK (0x1 << 9)
#define RT5623_HPL_INPUT_SEL_HPLMIXER_SFT 9
#define RT5623_HPL_INPUT_SEL_HPLMIXER (0x1 << 9)
#define RT5623_HPR_INPUT_SEL_HPRMIXER_MASK (0x1 << 8)
#define RT5623_HPR_INPUT_SEL_HPRMIXER_SFT 8
#define RT5623_HPR_INPUT_SEL_HPRMIXER (0x1 << 8)
#define RT5623_MONO_AUX_INPUT_SEL_MASK (0x3 << 6)
#define RT5623_MONO_AUX_INPUT_SEL_SFT 6
#define RT5623_MONO_AUX_INPUT_SEL_MONO (0x3 << 6)
#define RT5623_MONO_AUX_INPUT_SEL_SPK (0x2 << 6)
#define RT5623_MONO_AUX_INPUT_SEL_HP (0x1 << 6)
#define RT5623_MONO_AUX_INPUT_SEL_VMID (0x0 << 6)
/* Micphone Control define(0x22) */
#define RT5623_MIC1 1
#define RT5623_MIC2 2
#define RT5623_MIC_BIAS_90_PRECNET_AVDD 1
#define RT5623_MIC_BIAS_75_PRECNET_AVDD 2
#define RT5623_MIC1_BOOST_CTRL_MASK (0x3 << 10)
#define RT5623_MIC1_BOOST_CTRL_SFT 10
#define RT5623_MIC1_BOOST_CTRL_BYPASS 0x0 << 10)
#define RT5623_MIC1_BOOST_CTRL_20DB (0x1 << 10)
#define RT5623_MIC1_BOOST_CTRL_30DB (0x2 << 10)
#define RT5623_MIC1_BOOST_CTRL_40DB (0x3 << 10)
#define RT5623_MIC2_BOOST_CTRL_MASK (0x3 << 8)
#define RT5623_MIC2_BOOST_CTRL_SFT 8
#define RT5623_MIC2_BOOST_CTRL_BYPASS (0x0 << 8)
#define RT5623_MIC2_BOOST_CTRL_20DB (0x1 << 8)
#define RT5623_MIC2_BOOST_CTRL_30DB (0x2 << 8)
#define RT5623_MIC2_BOOST_CTRL_40DB (0x3 << 8)
#define RT5623_MICBIAS_VOLT_CTRL_MASK (0x1 << 5)
#define RT5623_MICBIAS_VOLT_CTRL_90P (0x0 << 5)
#define RT5623_MICBIAS_VOLT_CTRL_75P (0x1 << 5)
#define RT5623_MICBIAS_SHORT_CURR_DET_MASK (0x3)
#define RT5623_MICBIAS_SHORT_CURR_DET_600UA (0x0)
#define RT5623_MICBIAS_SHORT_CURR_DET_1200UA (0x1)
#define RT5623_MICBIAS_SHORT_CURR_DET_1800UA (0x2)
/* Audio Interface (0x34) */
#define RT5623_SDP_MASTER_MODE (0x0 << 15)
#define RT5623_SDP_SLAVE_MODE (0x1 << 15)
#define RT5623_I2S_PCM_MODE (0x1 << 14)
#define RT5623_MAIN_I2S_BCLK_POL_CTRL (0x1 << 7)
/* 0:ADC data appear at left phase of LRCK
* 1:ADC data appear at right phase of LRCK
*/
#define RT5623_ADC_DATA_L_R_SWAP (0x1 << 5)
/* 0:DAC data appear at left phase of LRCK
* 1:DAC data appear at right phase of LRCK
*/
#define RT5623_DAC_DATA_L_R_SWAP (0x1 << 4)
#define RT5623_I2S_DL_MASK (0x3 << 2)
#define RT5623_I2S_DL_16 (0x0 << 2)
#define RT5623_I2S_DL_20 (0x1 << 2)
#define RT5623_I2S_DL_24 (0x2 << 2)
#define RT5623_I2S_DL_32 (0x3 << 2)
#define RT5623_I2S_DF_MASK (0x3)
#define RT5623_I2S_DF_I2S (0x0)
#define RT5623_I2S_DF_RIGHT (0x1)
#define RT5623_I2S_DF_LEFT (0x2)
#define RT5623_I2S_DF_PCM (0x3)
/* Stereo AD/DA Clock Control(0x36h) */
#define RT5623_I2S_PRE_DIV_MASK (0x7 << 12)
#define RT5623_I2S_PRE_DIV_1 (0x0 << 12)
#define RT5623_I2S_PRE_DIV_2 (0x1 << 12)
#define RT5623_I2S_PRE_DIV_4 (0x2 << 12)
#define RT5623_I2S_PRE_DIV_8 (0x3 << 12)
#define RT5623_I2S_PRE_DIV_16 (0x4 << 12)
#define RT5623_I2S_PRE_DIV_32 (0x5 << 12)
#define RT5623_I2S_SCLK_DIV_MASK (0x7 << 9)
#define RT5623_I2S_SCLK_DIV_1 (0x0 << 9)
#define RT5623_I2S_SCLK_DIV_2 (0x1 << 9)
#define RT5623_I2S_SCLK_DIV_3 (0x2 << 9)
#define RT5623_I2S_SCLK_DIV_4 (0x3 << 9)
#define RT5623_I2S_SCLK_DIV_6 (0x4 << 9)
#define RT5623_I2S_SCLK_DIV_8 (0x5 << 9)
#define RT5623_I2S_SCLK_DIV_12 (0x6 << 9)
#define RT5623_I2S_SCLK_DIV_16 (0x7 << 9)
#define RT5623_I2S_WCLK_DIV_PRE_MASK (0xF << 5)
#define RT5623_I2S_WCLK_PRE_DIV_1 (0x0 << 5)
#define RT5623_I2S_WCLK_PRE_DIV_2 (0x1 << 5)
#define RT5623_I2S_WCLK_PRE_DIV_3 (0x2 << 5)
#define RT5623_I2S_WCLK_PRE_DIV_4 (0x3 << 5)
#define RT5623_I2S_WCLK_PRE_DIV_5 (0x4 << 5)
#define RT5623_I2S_WCLK_PRE_DIV_6 (0x5 << 5)
#define RT5623_I2S_WCLK_PRE_DIV_7 (0x6 << 5)
#define RT5623_I2S_WCLK_PRE_DIV_8 (0x7 << 5)
#define RT5623_I2S_WCLK_DIV_MASK (0x7 << 2)
#define RT5623_I2S_WCLK_DIV_2 (0x0 << 2)
#define RT5623_I2S_WCLK_DIV_4 (0x1 << 2)
#define RT5623_I2S_WCLK_DIV_8 (0x2 << 2)
#define RT5623_I2S_WCLK_DIV_16 (0x3 << 2)
#define RT5623_I2S_WCLK_DIV_32 (0x4 << 2)
#define RT5623_ADDA_FILTER_CLK_SEL_256FS (0 << 1)
#define RT5623_ADDA_FILTER_CLK_SEL_384FS (1 << 1)
#define RT5623_ADDA_OSR_SEL_64FS (0)
#define RT5623_ADDA_OSR_SEL_128FS (1)
/* Power managment addition 1 (0x3a) */
#define RT5623_PWR_MAIN_I2S_EN (0x1 << 15)
#define RT5623_PWR_MAIN_I2S_EN_BIT 15
#define RT5623_PWR_ZC_DET_PD_EN (0x1 << 14)
#define RT5623_PWR_ZC_DET_PD_EN_BIT 14
#define RT5623_PWR_MIC1_BIAS_EN (0x1 << 11)
#define RT5623_PWR_MIC1_BIAS_EN_BIT 11
#define RT5623_PWR_SHORT_CURR_DET_EN (0x1 << 10)
#define RT5623_PWR_SHORT_CURR_DET_EN_BIT 10
#define RT5623_PWR_SOFTGEN_EN (0x1 << 8)
#define RT5623_PWR_SOFTGEN_EN_BIT 8
#define RT5623_PWR_DEPOP_BUF_HP (0x1 << 6)
#define RT5623_PWR_DEPOP_BUF_HP_BIT 6
#define RT5623_PWR_HP_OUT_AMP (0x1 << 5)
#define RT5623_PWR_HP_OUT_AMP_BIT 5
#define RT5623_PWR_HP_OUT_ENH_AMP (0x1 << 4)
#define RT5623_PWR_HP_OUT_ENH_AMP_BIT 4
#define RT5623_PWR_DEPOP_BUF_AUX (0x1 << 2)
#define RT5623_PWR_DEPOP_BUF_AUX_BIT 2
#define RT5623_PWR_AUX_OUT_AMP (0x1 << 1)
#define RT5623_PWR_AUX_OUT_AMP_BIT 1
#define RT5623_PWR_AUX_OUT_ENH_AMP (0x1)
#define RT5623_PWR_AUX_OUT_ENH_AMP_BIT 0
/* Power managment addition 2 (0x3c) */
#define RT5623_PWR_CLASS_AB (0x1 << 15)
#define RT5623_PWR_CLASS_AB_BIT 15
#define RT5623_PWR_CLASS_D (0x1 << 14)
#define RT5623_PWR_CLASS_D_BIT 14
#define RT5623_PWR_VREF (0x1 << 13)
#define RT5623_PWR_VREF_BIT 13
#define RT5623_PWR_PLL (0x1 << 12)
#define RT5623_PWR_PLL_BIT 12
#define RT5623_PWR_DAC_REF_CIR (0x1 << 10)
#define RT5623_PWR_DAC_REF_CIR_BIT 10
#define RT5623_PWR_L_DAC_CLK (0x1 << 9)
#define RT5623_PWR_L_DAC_CLK_BIT 9
#define RT5623_PWR_R_DAC_CLK (0x1 << 8)
#define RT5623_PWR_R_DAC_CLK_BIT 8
#define RT5623_PWR_L_ADC_CLK_GAIN (0x1 << 7)
#define RT5623_PWR_L_ADC_CLK_GAIN_BIT 7
#define RT5623_PWR_R_ADC_CLK_GAIN (0x1 << 6)
#define RT5623_PWR_R_ADC_CLK_GAIN_BIT 6
#define RT5623_PWR_L_HP_MIXER (0x1 << 5)
#define RT5623_PWR_L_HP_MIXER_BIT 5
#define RT5623_PWR_R_HP_MIXER (0x1 << 4)
#define RT5623_PWR_R_HP_MIXER_BIT 4
#define RT5623_PWR_SPK_MIXER (0x1 << 3)
#define RT5623_PWR_SPK_MIXER_BIT 3
#define RT5623_PWR_MONO_MIXER (0x1 << 2)
#define RT5623_PWR_MONO_MIXER_BIT 2
#define RT5623_PWR_L_ADC_REC_MIXER (0x1 << 1)
#define RT5623_PWR_L_ADC_REC_MIXER_BIT 1
#define RT5623_PWR_R_ADC_REC_MIXER (0x1)
#define RT5623_PWR_R_ADC_REC_MIXER_BIT 0
/* Power managment addition 3 (0x3e) */
#define RT5623_PWR_MAIN_BIAS (0x1 << 15)
#define RT5623_PWR_MAIN_BIAS_BIT 15
#define RT5623_PWR_AUXOUT_L_VOL_AMP (0x1 << 14)
#define RT5623_PWR_AUXOUT_L_VOL_AMP_BIT 14
#define RT5623_PWR_AUXOUT_R_VOL_AMP (0x1 << 13)
#define RT5623_PWR_AUXOUT_R_VOL_AMP_BIT 13
#define RT5623_PWR_SPK_OUT (0x1 << 12)
#define RT5623_PWR_SPK_OUT_BIT 12
#define RT5623_PWR_HP_L_OUT_VOL (0x1 << 10)
#define RT5623_PWR_HP_L_OUT_VOL_BIT 10
#define RT5623_PWR_HP_R_OUT_VOL (0x1 << 9)
#define RT5623_PWR_HP_R_OUT_VOL_BIT 9
#define RT5623_PWR_LINEIN_L_VOL (0x1 << 7)
#define RT5623_PWR_LINEIN_L_VOL_BIT 7
#define RT5623_PWR_LINEIN_R_VOL (0x1 << 6)
#define RT5623_PWR_LINEIN_R_VOL_BIT 6
#define RT5623_PWR_AUXIN_L_VOL (0x1 << 5)
#define RT5623_PWR_AUXIN_L_VOL_BIT 5
#define RT5623_PWR_AUXIN_R_VOL (0x1 << 4)
#define RT5623_PWR_AUXIN_R_VOL_BIT 4
#define RT5623_PWR_MIC1_FUN_CTRL (0x1 << 3)
#define RT5623_PWR_MIC1_FUN_CTRL_BIT 3
#define RT5623_PWR_MIC2_FUN_CTRL (0x1 << 2)
#define RT5623_PWR_MIC2_FUN_CTRL_BIT 2
#define RT5623_PWR_MIC1_BOOST_MIXER (0x1 << 1)
#define RT5623_PWR_MIC1_BOOST_MIXER_BIT 1
#define RT5623_PWR_MIC2_BOOST_MIXER (0x1)
#define RT5623_PWR_MIC2_BOOST_MIXER_BIT 0
/* Additional Control Register (0x40) */
#define RT5623_AUXOUT_SEL_DIFF (0x1 << 15)
#define RT5623_AUXOUT_SEL_SE (0x1 << 15)
#define RT5623_SPK_AB_AMP_CTRL_MASK (0x7 << 12)
#define RT5623_SPK_AB_AMP_CTRL_RATIO_225 (0x0 << 12)
#define RT5623_SPK_AB_AMP_CTRL_RATIO_200 (0x1 << 12)
#define RT5623_SPK_AB_AMP_CTRL_RATIO_175 (0x2 << 12)
#define RT5623_SPK_AB_AMP_CTRL_RATIO_150 (0x3 << 12)
#define RT5623_SPK_AB_AMP_CTRL_RATIO_125 (0x4 << 12)
#define RT5623_SPK_AB_AMP_CTRL_RATIO_100 (0x5 << 12)
#define RT5623_SPK_D_AMP_CTRL_MASK (0x3 << 10)
#define RT5623_SPK_D_AMP_CTRL_RATIO_175 (0x0 << 10)
#define RT5623_SPK_D_AMP_CTRL_RATIO_150 (0x1 << 10)
#define RT5623_SPK_D_AMP_CTRL_RATIO_125 (0x2 << 10)
#define RT5623_SPK_D_AMP_CTRL_RATIO_100 (0x3 << 10)
#define RT5623_STEREO_DAC_HI_PASS_FILTER_EN (0x1 << 9)
#define RT5623_STEREO_ADC_HI_PASS_FILTER_EN (0x1 << 8)
#define RT5623_DIG_VOL_BOOST_MASK (0x3 << 4)
#define RT5623_DIG_VOL_BOOST_0DB (0x0 << 4)
#define RT5623_DIG_VOL_BOOST_6DB (0x1 << 4)
#define RT5623_DIG_VOL_BOOST_12DB (0x2 << 4)
#define RT5623_DIG_VOL_BOOST_18DB (0x3 << 4)
/* Global Clock Control Register (0x42) */
#define RT5623_SYSCLK_SOUR_SEL_MASK (0x1 << 15)
#define RT5623_SYSCLK_SOUR_SEL_MCLK (0x0 << 15)
#define RT5623_SYSCLK_SOUR_SEL_PLL (0x1 << 15)
#define RT5623_PLLCLK_SOUR_SEL_MCLK (0x0 << 14)
#define RT5623_PLLCLK_SOUR_SEL_BITCLK (0x1 << 14)
#define RT5623_PLLCLK_DIV_RATIO_MASK (0x3 << 1)
#define RT5623_PLLCLK_DIV_RATIO_DIV1 (0x0 << 1)
#define RT5623_PLLCLK_DIV_RATIO_DIV2 (0x1 << 1)
#define RT5623_PLLCLK_DIV_RATIO_DIV4 (0x2 << 1)
#define RT5623_PLLCLK_DIV_RATIO_DIV8 (0x3 << 1)
#define PLLCLK_PRE_DIV1 (0x0)
#define PLLCLK_PRE_DIV2 (0x1)
/* GPIO Pin Configuration (0x4c) */
#define RT5623_GPIO_PIN_MASK (0x1 << 1)
#define RT5623_GPIO_PIN_SET_INPUT (0x1 << 1)
#define RT5623_GPIO_PIN_SET_OUTPUT (0x0 << 1)
/* Pin Sharing (0x56) */
#define RT5623_LINEIN_L_PIN_SHARING (0x1 << 15)
#define RT5623_LINEIN_L_PIN_AS_LINEIN_L (0x0 << 15)
#define RT5623_LINEIN_L_PIN_AS_JD1 (0x1 << 15)
#define RT5623_LINEIN_R_PIN_SHARING (0x1 << 14)
#define RT5623_LINEIN_R_PIN_AS_LINEIN_R (0x0 << 14)
#define RT5623_LINEIN_R_PIN_AS_JD2 (0x1 << 14)
#define RT5623_GPIO_PIN_SHARE (0x3)
#define RT5623_GPIO_PIN_AS_GPIO (0x0)
#define RT5623_GPIO_PIN_AS_IRQOUT (0x1)
#define RT5623_GPIO_PIN_AS_PLLOUT (0x3)
/* Jack Detect Control Register (0x5a) */
#define RT5623_JACK_DETECT_MASK (0x3 << 14)
#define RT5623_JACK_DETECT_USE_JD2 (0x3 << 14)
#define RT5623_JACK_DETECT_USE_JD1 (0x2 << 14)
#define RT5623_JACK_DETECT_USE_GPIO (0x1 << 14)
#define RT5623_JACK_DETECT_OFF (0x0 << 14)
#define RT5623_SPK_EN_IN_HI (0x1 << 11)
#define RT5623_AUX_R_EN_IN_HI (0x1 << 10)
#define RT5623_AUX_L_EN_IN_HI (0x1 << 9)
#define RT5623_HP_EN_IN_HI (0x1 << 8)
#define RT5623_SPK_EN_IN_LO (0x1 << 7)
#define RT5623_AUX_R_EN_IN_LO (0x1 << 6)
#define RT5623_AUX_L_EN_IN_LO (0x1 << 5)
#define RT5623_HP_EN_IN_LO (0x1 << 4)
/* MISC CONTROL (0x5e) */
#define RT5623_DISABLE_FAST_VREG (0x1 << 15)
#define RT5623_SPK_CLASS_AB_OC_PD (0x1 << 13)
#define RT5623_SPK_CLASS_AB_OC_DET (0x1 << 12)
#define RT5623_HP_DEPOP_MODE3_EN (0x1 << 10)
#define RT5623_HP_DEPOP_MODE2_EN (0x1 << 9)
#define RT5623_HP_DEPOP_MODE1_EN (0x1 << 8)
#define RT5623_AUXOUT_DEPOP_MODE3_EN (0x1 << 6)
#define RT5623_AUXOUT_DEPOP_MODE2_EN (0x1 << 5)
#define RT5623_AUXOUT_DEPOP_MODE1_EN (0x1 << 4)
#define RT5623_M_DAC_L_INPUT (0x1 << 3)
#define RT5623_M_DAC_R_INPUT (0x1 << 2)
#define RT5623_IRQOUT_INV_CTRL (0x1 << 0)
/* Psedueo Stereo & Spatial Effect Block Control (0x60) */
#define RT5623_SPATIAL_CTRL_EN (0x1 << 15)
#define RT5623_ALL_PASS_FILTER_EN (0x1 << 14)
#define RT5623_PSEUDO_STEREO_EN (0x1 << 13)
#define RT5623_STEREO_EXPENSION_EN (0x1 << 12)
#define RT5623_GAIN_3D_PARA_L_MASK (0x7 << 9)
#define RT5623_GAIN_3D_PARA_L_1_00 (0x0 << 9)
#define RT5623_GAIN_3D_PARA_L_1_25 (0x1 << 9)
#define RT5623_GAIN_3D_PARA_L_1_50 (0x2 << 9)
#define RT5623_GAIN_3D_PARA_L_1_75 (0x3 << 9)
#define RT5623_GAIN_3D_PARA_L_2_00 (0x4 << 9)
#define RT5623_GAIN_3D_PARA_R_MASK (0x7 << 6)
#define RT5623_GAIN_3D_PARA_R_1_00 (0x0 << 6)
#define RT5623_GAIN_3D_PARA_R_1_25 (0x1 << 6)
#define RT5623_GAIN_3D_PARA_R_1_50 (0x2 << 6)
#define RT5623_GAIN_3D_PARA_R_1_75 (0x3 << 6)
#define RT5623_GAIN_3D_PARA_R_2_00 (0x4 << 6)
#define RT5623_RATIO_3D_L_MASK (0x3 << 4)
#define RT5623_RATIO_3D_L_0_0 (0x0 << 4)
#define RT5623_RATIO_3D_L_0_66 (0x1 << 4)
#define RT5623_RATIO_3D_L_1_0 (0x2 << 4)
#define RT5623_RATIO_3D_R_MASK (0x3 << 2)
#define RT5623_RATIO_3D_R_0_0 (0x0 << 2)
#define RT5623_RATIO_3D_R_0_66 (0x1 << 2)
#define RT5623_RATIO_3D_R_1_0 (0x2 << 2)
#define RT5623_APF_MASK (0x3)
#define RT5623_APF_FOR_48K (0x3)
#define RT5623_APF_FOR_44_1K (0x2)
#define RT5623_APF_FOR_32K (0x1)
/* EQ CONTROL (0x62) */
#define RT5623_EN_HW_EQ_BLK (0x1 << 15)
#define RT5623_EN_HW_EQ_HPF_MODE (0x1 << 14)
#define RT5623_EN_HW_EQ_SOUR (0x1 << 11)
#define RT5623_EN_HW_EQ_HPF (0x1 << 4)
#define RT5623_EN_HW_EQ_BP3 (0x1 << 3)
#define RT5623_EN_HW_EQ_BP2 (0x1 << 2)
#define RT5623_EN_HW_EQ_BP1 (0x1 << 1)
#define RT5623_EN_HW_EQ_LPF (0x1 << 0)
/* EQ Mode Change Enable (0x66) */
#define RT5623_EQ_HPF_CHANGE_EN (0x1 << 4)
#define RT5623_EQ_BP3_CHANGE_EN (0x1 << 3)
#define RT5623_EQ_BP2_CHANGE_EN (0x1 << 2)
#define RT5623_EQ_BP1_CHANGE_EN (0x1 << 1)
#define RT5623_EQ_LPF_CHANGE_EN (0x1 << 0)
/* AVC Control (0x68) */
#define RT5623_AVC_ENABLE (0x1 << 15)
#define RT5623_AVC_TARTGET_SEL_MASK (0x1 << 14)
#define RT5623_AVC_TARTGET_SEL_R (0x1 << 14)
#define RT5623_AVC_TARTGET_SEL_L (0x0 << 14)
#define RT5623_PLL_FR_MCLK 0
#define RT5623_PLL_FR_BCLK 1
#endif /* __RT5623_H__ */

3185
sound/soc/codecs/rt5625.c
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823
sound/soc/codecs/rt5625.h
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@@ -1,823 +0,0 @@
/*
* rt5625.h -- RT5625 ALSA SoC audio driver
*
* Copyright 2011 Realtek Microelectronics
* Author: Johnny Hsu <johnnyhsu@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RT5625_H__
#define __RT5625_H__
#define RT5625_RESET 0x00
#define RT5625_SPK_OUT_VOL 0x02
#define RT5625_HP_OUT_VOL 0x04
#define RT5625_AUX_OUT_VOL 0x06
#define RT5625_PHONEIN_VOL 0x08
#define RT5625_LINE_IN_VOL 0x0a
#define RT5625_DAC_VOL 0x0c
#define RT5625_MIC_VOL 0x0e
#define RT5625_DAC_MIC_CTRL 0x10
#define RT5625_ADC_REC_GAIN 0x12
#define RT5625_ADC_REC_MIXER 0x14
#define RT5625_VDAC_OUT_VOL 0x18
#define RT5625_VODSP_PDM_CTL 0x1a
#define RT5625_OUTMIX_CTRL 0x1c
#define RT5625_VODSP_CTL 0x1e
#define RT5625_MIC_CTRL 0x22
#define RT5625_DMIC_CTRL 0x24
#define RT5625_PD_CTRL 0x26
#define RT5625_F_DAC_ADC_VDAC 0x2e
#define RT5625_SDP_CTRL 0x34
#define RT5625_EXT_SDP_CTRL 0x36
#define RT5625_PWR_ADD1 0x3a
#define RT5625_PWR_ADD2 0x3c
#define RT5625_PWR_ADD3 0x3e
#define RT5625_GEN_CTRL1 0x40
#define RT5625_GEN_CTRL2 0x42
#define RT5625_PLL_CTRL 0x44
#define RT5625_PLL2_CTRL 0x46
#define RT5625_LDO_CTRL 0x48
#define RT5625_GPIO_CONFIG 0x4c
#define RT5625_GPIO_POLAR 0x4e
#define RT5625_GPIO_STICKY 0x50
#define RT5625_GPIO_WAKEUP 0x52
#define RT5625_GPIO_STATUS 0x54
#define RT5625_GPIO_SHARING 0x56
#define RT5625_OTC_STATUS 0x58
#define RT5625_SOFT_VOL_CTRL 0x5a
#define RT5625_GPIO_OUT_CTRL 0x5c
#define RT5625_MISC_CTRL 0x5e
#define RT5625_DAC_CLK_CTRL1 0x60
#define RT5625_DAC_CLK_CTRL2 0x62
#define RT5625_VDAC_CLK_CTRL1 0x64
#define RT5625_PS_CTRL 0x68
#define RT5625_PRIV_INDEX 0x6a
#define RT5625_PRIV_DATA 0x6c
#define RT5625_EQ_CTRL 0x6e
#define RT5625_DSP_ADDR 0x70
#define RT5625_DSP_DATA 0x72
#define RT5625_DSP_CMD 0x74
#define RT5625_VENDOR_ID1 0x7c
#define RT5625_VENDOR_ID2 0x7e
/* global definition */
#define RT5625_L_MUTE (0x1 << 15)
#define RT5625_L_MUTE_SFT 15
#define RT5625_L_ZC (0x1 << 14)
#define RT5625_L_VOL_MASK (0x1f << 8)
#define RT5625_L_HVOL_MASK (0x3f << 8)
#define RT5625_L_VOL_SFT 8
#define RT5625_R_MUTE (0x1 << 7)
#define RT5625_R_MUTE_SFT 7
#define RT5625_R_ZC (0x1 << 6)
#define RT5625_R_VOL_MASK (0x1f)
#define RT5625_R_HVOL_MASK (0x3f)
#define RT5625_R_VOL_SFT 0
#define RT5625_M_HPMIX (0x1 << 15)
#define RT5625_M_SPKMIX (0x1 << 14)
#define RT5625_M_MONOMIX (0x1 << 13)
/* Phone Input (0x08) */
#define RT5625_M_PHO_HM (0x1 << 15)
#define RT5625_M_PHO_HM_SFT 15
#define RT5625_M_PHO_SM (0x1 << 14)
#define RT5625_M_PHO_SM_SFT 14
#define RT5625_PHO_DIFF (0x1 << 13)
#define RT5625_PHO_DIFF_SFT 13
#define RT5625_PHO_DIFF_DIS (0x0 << 13)
#define RT5625_PHO_DIFF_EN (0x1 << 13)
/* Linein Volume (0x0a) */
#define RT5625_M_LI_HM (0x1 << 15)
#define RT5625_M_LI_HM_SFT 15
#define RT5625_M_LI_SM (0x1 << 14)
#define RT5625_M_LI_SM_SFT 14
#define RT5625_M_LI_MM (0x1 << 13)
#define RT5625_M_LI_MM_SFT 13
/* MIC Input Volume (0x0e) */
#define RT5625_MIC1_DIFF_MASK (0x1 << 15)
#define RT5625_MIC1_DIFF_SFT 15
#define RT5625_MIC1_DIFF_DIS (0x0 << 15)
#define RT5625_MIC1_DIFF_EN (0x1 << 15)
#define RT5625_MIC2_DIFF_MASK (0x1 << 7)
#define RT5625_MIC2_DIFF_SFT 7
#define RT5625_MIC2_DIFF_DIS (0x0 << 7)
#define RT5625_MIC2_DIFF_EN (0x1 << 7)
/* Stereo DAC and MIC Routing Control (0x10) */
#define RT5625_M_MIC1_HM (0x1 << 15)
#define RT5625_M_MIC1_HM_SFT 15
#define RT5625_M_MIC1_SM (0x1 << 14)
#define RT5625_M_MIC1_SM_SFT 14
#define RT5625_M_MIC1_MM (0x1 << 13)
#define RT5625_M_MIC1_MM_SFT 13
#define RT5625_M_MIC2_HM (0x1 << 11)
#define RT5625_M_MIC2_HM_SFT 11
#define RT5625_M_MIC2_SM (0x1 << 10)
#define RT5625_M_MIC2_SM_SFT 10
#define RT5625_M_MIC2_MM (0x1 << 9)
#define RT5625_M_MIC2_MM_SFT 9
#define RT5625_M_DACL_HM (0x1 << 3)
#define RT5625_M_DACL_HM_SFT 3
#define RT5625_M_DACR_HM (0x1 << 2)
#define RT5625_M_DACR_HM_SFT 2
#define RT5625_M_DAC_SM (0x1 << 1)
#define RT5625_M_DAC_SM_SFT 1
#define RT5625_M_DAC_MM (0x1)
#define RT5625_M_DAC_MM_SFT 0
/* ADC Record Gain (0x12) */
#define RT5625_M_ADCL_HM (0x1 << 15)
#define RT5625_M_ADCL_HM_SFT 15
#define RT5625_M_ADCL_MM (0x1 << 14)
#define RT5625_M_ADCL_MM_SFT 14
#define RT5625_ADCL_ZCD (0x1 << 13)
#define RT5625_G_ADCL_MASK (0x1f << 8)
#define RT5625_M_ADCR_HM (0x1 << 7)
#define RT5625_M_ADCR_HM_SFT 7
#define RT5625_M_ADCR_MM (0x1 << 6)
#define RT5625_M_ADCR_MM_SFT 6
#define RT5625_ADCR_ZCD (0x1 << 5)
#define RT5625_G_ADCR_MASK (0x1f)
/* ADC Record Mixer Control (0x14) */
#define RT5625_M_RM_L_MIC1 (0x1 << 14)
#define RT5625_M_RM_L_MIC1_SFT 14
#define RT5625_M_RM_L_MIC2 (0x1 << 13)
#define RT5625_M_RM_L_MIC2_SFT 13
#define RT5625_M_RM_L_LINE (0x1 << 12)
#define RT5625_M_RM_L_LINE_SFT 12
#define RT5625_M_RM_L_PHO (0x1 << 11)
#define RT5625_M_RM_L_PHO_SFT 11
#define RT5625_M_RM_L_HM (0x1 << 10)
#define RT5625_M_RM_L_HM_SFT 10
#define RT5625_M_RM_L_SM (0x1 << 9)
#define RT5625_M_RM_L_SM_SFT 9
#define RT5625_M_RM_L_MM (0x1 << 8)
#define RT5625_M_RM_L_MM_SFT 8
#define RT5625_M_RM_R_MIC1 (0x1 << 6)
#define RT5625_M_RM_R_MIC1_SFT 6
#define RT5625_M_RM_R_MIC2 (0x1 << 5)
#define RT5625_M_RM_R_MIC2_SFT 5
#define RT5625_M_RM_R_LINE (0x1 << 4)
#define RT5625_M_RM_R_LINE_SFT 4
#define RT5625_M_RM_R_PHO (0x1 << 3)
#define RT5625_M_RM_R_PHO_SFT 3
#define RT5625_M_RM_R_HM (0x1 << 2)
#define RT5625_M_RM_R_HM_SFT 2
#define RT5625_M_RM_R_SM (0x1 << 1)
#define RT5625_M_RM_R_SM_SFT 1
#define RT5625_M_RM_R_MM (0x1)
#define RT5625_M_RM_R_MM_SFT 0
/* Voice DAC Volume (0x18) */
#define RT5625_M_VDAC_HM (0x1 << 15)
#define RT5625_M_VDAC_HM_SFT 15
#define RT5625_M_VDAC_SM (0x1 << 14)
#define RT5625_M_VDAC_SM_SFT 14
#define RT5625_M_VDAC_MM (0x1 << 13)
#define RT5625_M_VDAC_MM_SFT 13
/* AEC & PDM Control (0x1a) */
#define RT5625_SRC1_PWR (0x1 << 15)
#define RT5625_SRC1_PWR_SFT 15
#define RT5625_SRC2_PWR (0x1 << 13)
#define RT5625_SRC2_PWR_SFT 13
#define RT5625_SRC2_S_MASK (0x1 << 12)
#define RT5625_SRC2_S_SFT 12
#define RT5625_SRC2_S_TXDP (0x0 << 12)
#define RT5625_SRC2_S_TXDC (0x1 << 12)
#define RT5625_RXDP_PWR (0x1 << 11)
#define RT5625_RXDP_PWR_SFT 11
#define RT5625_RXDP_S_MASK (0x3 << 9)
#define RT5625_RXDP_S_SFT 9
#define RT5625_RXDP_S_SRC1 (0x0 << 9)
#define RT5625_RXDP_S_ADCL (0x1 << 9)
#define RT5625_RXDP_S_VOICE (0x2 << 9)
#define RT5625_RXDP_S_ADCR (0x3 << 9)
#define RT5625_RXDC_PWR (0x1 << 8)
#define RT5625_RXDC_PWR_SFT 8
#define RT5625_PCM_S_MASK (0x1 << 7)
#define RT5625_PCM_S_SFT 7
#define RT5625_PCM_S_ADCR (0x0 << 7)
#define RT5625_PCM_S_TXDP (0x1 << 7)
#define RT5625_REC_IIS_S_MASK (0x3 << 4)
#define RT5625_REC_IIS_S_SFT 4
#define RT5625_REC_IIS_S_ADC (0x0 << 4)
#define RT5625_REC_IIS_S_VOICE (0x1 << 4)
#define RT5625_REC_IIS_S_SRC2 (0x2 << 4)
/* Output Mixer Control (0x1c) */
#define RT5625_SPKN_S_MASK (0x3 << 14)
#define RT5625_SPKN_S_SFT 14
#define RT5625_SPKN_S_LN (0x2 << 14)
#define RT5625_SPKN_S_RP (0x1 << 14)
#define RT5625_SPKN_S_RN (0x0 << 14)
#define RT5625_SPK_T_MASK (0x1 << 13)
#define RT5625_SPK_T_SFT 13
#define RT5625_SPK_T_CLS_D (0x1 << 13)
#define RT5625_SPK_T_CLS_AB (0x0 << 13)
#define RT5625_CLS_AB_MASK (0x1 << 12)
#define RT5625_CLS_AB_SFT 12
#define RT5625_CLS_AB_S_AMP (0x0 << 12)
#define RT5625_CLS_AB_W_AMP (0x1 << 12)
#define RT5625_SPKVOL_S_MASK (0x3 << 10)
#define RT5625_SPKVOL_S_SFT 10
#define RT5625_SPKVOL_S_MM (0x3 << 10)
#define RT5625_SPKVOL_S_SM (0x2 << 10)
#define RT5625_SPKVOL_S_HM (0x1 << 10)
#define RT5625_SPKVOL_S_VMID (0x0 << 10)
#define RT5625_HPVOL_L_S_MASK (0x1 << 9)
#define RT5625_HPVOL_L_S_SFT 9
#define RT5625_HPVOL_L_S_HM (0x1 << 9)
#define RT5625_HPVOL_L_S_VMID (0x0 << 9)
#define RT5625_HPVOL_R_S_MASK (0x1 << 8)
#define RT5625_HPVOL_R_S_SFT 8
#define RT5625_HPVOL_R_S_HM (0x1 << 8)
#define RT5625_HPVOL_R_S_VMID (0x0 << 8)
#define RT5625_AUXVOL_S_MASK (0x3 << 6)
#define RT5625_AUXVOL_S_SFT 6
#define RT5625_AUXVOL_S_MM (0x3 << 6)
#define RT5625_AUXVOL_S_SM (0x2 << 6)
#define RT5625_AUXVOL_S_HM (0x1 << 6)
#define RT5625_AUXVOL_S_VMID (0x0 << 6)
#define RT5625_AUXOUT_MODE (0x1 << 4)
#define RT5625_AUXOUT_MODE_SFT 4
#define RT5625_DACL_HP_MASK (0x1 << 1)
#define RT5625_DACL_HP_SFT 1
#define RT5625_DACL_HP_MUTE (0x0 << 1)
#define RT5625_DACL_HP_ON (0x1 << 1)
#define RT5625_DACR_HP_MASK (0x1)
#define RT5625_DACR_HP_SFT 0
#define RT5625_DACR_HP_MUTE (0x0)
#define RT5625_DACR_HP_ON (0x1)
/* VoDSP Control (0x1e) */
#define RT5625_DSP_SCLK_S_MASK (0x1 << 15)
#define RT5625_DSP_SCLK_S_SFT 15
#define RT5625_DSP_SCLK_S_MCLK (0x0 << 15)
#define RT5625_DSP_SCLK_S_VCLK (0x1 << 15)
#define RT5625_DSP_LRCK_MASK (0x1 << 13)
#define RT5625_DSP_LRCK_SFT 13
#define RT5625_DSP_LRCK_8K (0x0 << 13)
#define RT5625_DSP_LRCK_16K (0x1 << 13)
#define RT5625_DSP_TP_MASK (0x1 << 3)
#define RT5625_DSP_TP_SFT 3
#define RT5625_DSP_TP_NOR (0x0 << 3)
#define RT5625_DSP_TP_TEST (0x1 << 3)
#define RT5625_DSP_BP_MASK (0x1 << 2)
#define RT5625_DSP_BP_SFT 2
#define RT5625_DSP_BP_EN (0x0 << 2)
#define RT5625_DSP_BP_NOR (0x1 << 2)
#define RT5625_DSP_PD_MASK (0x1 << 1)
#define RT5625_DSP_PD_SFT 1
#define RT5625_DSP_PD_EN (0x0 << 1)
#define RT5625_DSP_PD_NOR (0x1 << 1)
#define RT5625_DSP_RST_MASK (0x1)
#define RT5625_DSP_RST_SFT 0
#define RT5625_DSP_RST_EN (0x0)
#define RT5625_DSP_RST_NOR (0x1)
/* Microphone Control (0x22) */
#define RT5625_MIC1_BST_MASK (0x3 << 10)
#define RT5625_MIC1_BST_SFT 10
#define RT5625_MIC1_BST_BYPASS (0x0 << 10)
#define RT5625_MIC1_BST_20DB (0x1 << 10)
#define RT5625_MIC1_BST_30DB (0x2 << 10)
#define RT5625_MIC1_BST_40DB (0x3 << 10)
#define RT5625_MIC2_BST_MASK (0x3 << 8)
#define RT5625_MIC2_BST_SFT 8
#define RT5625_MIC2_BST_BYPASS (0x0 << 8)
#define RT5625_MIC2_BST_20DB (0x1 << 8)
#define RT5625_MIC2_BST_30DB (0x2 << 8)
#define RT5625_MIC2_BST_40DB (0x3 << 8)
#define RT5625_MB1_OV_MASK (0x1 << 5)
#define RT5625_MB1_OV_90P (0x0 << 5)
#define RT5625_MB1_OV_75P (0x1 << 5)
#define RT5625_MB2_OV_MASK (0x1 << 4)
#define RT5625_MB2_OV_90P (0x0 << 4)
#define RT5625_MB2_OV_75P (0x1 << 4)
#define RT5625_SCD_THD_MASK (0x3)
#define RT5625_SCD_THD_600UA (0x0)
#define RT5625_SCD_THD_1500UA (0x1)
#define RT5625_SCD_THD_2000UA (0x2)
/* Digital Boost Control (0x24) */
#define RT5625_DIG_BST_MASK (0x7)
#define RT5625_DIG_BST_SFT 0
/* Power Down Control/Status (0x26) */
#define RT5625_PWR_PR7 (0x1 << 15)
#define RT5625_PWR_PR6 (0x1 << 14)
#define RT5625_PWR_PR5 (0x1 << 13)
#define RT5625_PWR_PR3 (0x1 << 11)
#define RT5625_PWR_PR2 (0x1 << 10)
#define RT5625_PWR_PR1 (0x1 << 9)
#define RT5625_PWR_PR0 (0x1 << 8)
#define RT5625_PWR_REF_ST (0x1 << 3)
#define RT5625_PWR_AM_ST (0x1 << 2)
#define RT5625_PWR_DAC_ST (0x1 << 1)
#define RT5625_PWR_ADC_ST (0x1)
/* Stereo DAC/Voice DAC/Stereo ADC Function Select (0x2e) */
#define RT5625_DAC_F_MASK (0x3 << 12)
#define RT5625_DAC_F_SFT 12
#define RT5625_DAC_F_DAC (0x0 << 12)
#define RT5625_DAC_F_SRC2 (0x1 << 12)
#define RT5625_DAC_F_TXDP (0x2 << 12)
#define RT5625_DAC_F_TXDC (0x3 << 12)
#define RT5625_VDAC_S_MASK (0x7 << 8)
#define RT5625_VDAC_S_SFT 8
#define RT5625_VDAC_S_VOICE (0x0 << 8)
#define RT5625_VDAC_S_SRC2 (0x1 << 8)
#define RT5625_VDAC_S_TXDP (0x2 << 8)
#define RT5625_VDAC_S_TXDC (0x3 << 8)
#define RT5625_ADCR_F_MASK (0x3 << 4)
#define RT5625_ADCR_F_SFT 4
#define RT5625_ADCR_F_ADC (0x0 << 4)
#define RT5625_ADCR_F_VADC (0x1 << 4)
#define RT5625_ADCR_F_DSP (0x2 << 4)
#define RT5625_ADCR_F_PDM (0x3 << 4)
#define RT5625_ADCL_F_MASK (0x1)
#define RT5625_ADCL_F_SFT 0
#define RT5625_ADCL_F_ADC (0x0)
#define RT5625_ADCL_F_DSP (0x1)
/* Main Serial Data Port Control (Stereo IIS) (0x34) */
#define RT5625_I2S_M_MASK (0x1 << 15)
#define RT5625_I2S_M_SFT 15
#define RT5625_I2S_M_MST (0x0 << 15)
#define RT5625_I2S_M_SLV (0x1 << 15)
#define RT5625_I2S_SAD_MASK (0x1 << 14)
#define RT5625_I2S_SAD_SFT 14
#define RT5625_I2S_SAD_DIS (0x0 << 14)
#define RT5625_I2S_SAD_EN (0x1 << 14)
#define RT5625_I2S_S_MASK (0x1 << 8)
#define RT5625_I2S_S_SFT 8
#define RT5625_I2S_S_MSCLK (0x0 << 8)
#define RT5625_I2S_S_VSCLK (0x1 << 8)
#define RT5625_I2S_BP_MASK (0x1 << 7)
#define RT5625_I2S_BP_SFT 7
#define RT5625_I2S_BP_NOR (0x0 << 7)
#define RT5625_I2S_BP_INV (0x1 << 7)
#define RT5625_I2S_LRCK_MASK (0x1 << 6)
#define RT5625_I2S_LRCK_SFT 6
#define RT5625_I2S_LRCK_NOR (0x0 << 6)
#define RT5625_I2S_LRCK_INV (0x1 << 6)
#define RT5625_I2S_DL_MASK (0x3 << 2)
#define RT5625_I2S_DL_SFT 2
#define RT5625_I2S_DL_16 (0x0 << 2)
#define RT5625_I2S_DL_20 (0x1 << 2)
#define RT5625_I2S_DL_24 (0x2 << 2)
#define RT5625_I2S_DL_8 (0x3 << 2)
#define RT5625_I2S_DF_MASK (0x3)
#define RT5625_I2S_DF_SFT 0
#define RT5625_I2S_DF_I2S (0x0)
#define RT5625_I2S_DF_LEFT (0x1)
#define RT5625_I2S_DF_PCM_A (0x2)
#define RT5625_I2S_DF_PCM_B (0x3)
/* Extend Serial Data Port Control (0x36) */
#define RT5625_PCM_F_MASK (0x1 << 15)
#define RT5625_PCM_F_SFT 15
#define RT5625_PCM_F_GPIO (0x0 << 15)
#define RT5625_PCM_F_PCM (0x1 << 15)
#define RT5625_PCM_M_MASK (0x1 << 14)
#define RT5625_PCM_M_SFT 14
#define RT5625_PCM_M_MST (0x0 << 14)
#define RT5625_PCM_M_SLV (0x1 << 14)
#define RT5625_PCM_CS_MASK (0x1 << 8)
#define RT5625_PCM_CS_SFT 8
#define RT5625_PCM_CS_SCLK (0x0 << 8)
#define RT5625_PCM_CS_VSCLK (0x1 << 8)
/* Power Management Addition 1 (0x3a) */
#define RT5625_P_DACL_MIX (0x1 << 15)
#define RT5625_P_DACL_MIX_BIT 15
#define RT5625_P_DACR_MIX (0x1 << 14)
#define RT5625_P_DACR_MIX_BIT 14
#define RT5625_P_ZCD (0x1 << 13)
#define RT5625_P_ZCD_BIT 13
#define RT5625_P_I2S (0x1 << 11)
#define RT5625_P_I2S_BIT 11
#define RT5625_P_SPK_AMP (0x1 << 10)
#define RT5625_P_SPK_AMP_BIT 10
#define RT5625_P_HPO_AMP (0x1 << 9)
#define RT5625_P_HPO_AMP_BIT 9
#define RT5625_P_HPO_ENH (0x1 << 8)
#define RT5625_P_HPO_ENH_BIT 8
#define RT5625_P_VDAC_MIX (0x1 << 7)
#define RT5625_P_VDAC_MIX_BIT 7
#define RT5625_P_SG_EN (0x1 << 6)
#define RT5625_P_SG_EN_BIT 6
#define RT5625_P_MB1_SCD (0x1 << 5)
#define RT5625_P_MB1_SCD_BIT 5
#define RT5625_P_MB2_SCD (0x1 << 4)
#define RT5625_P_MB2_SCD_BIT 4
#define RT5625_P_MB1 (0x1 << 3)
#define RT5625_P_MB1_BIT 3
#define RT5625_P_MB2 (0x1 << 2)
#define RT5625_P_MB2_BIT 2
#define RT5625_P_MAIN_BIAS (0x1 << 1)
#define RT5625_P_MAIN_BIAS_BIT 1
#define RT5625_P_DAC_REF (0x1)
#define RT5625_P_DAC_REF_BIT 0
/* Power Management Addition 2 (0x3c) */
#define RT5625_P_PLL1 (0x1 << 15)
#define RT5625_P_PLL1_BIT 15
#define RT5625_P_PLL2 (0x1 << 14)
#define RT5625_P_PLL2_BIT 14
#define RT5625_P_VREF (0x1 << 13)
#define RT5625_P_VREF_BIT 13
#define RT5625_P_OVT (0x1 << 12)
#define RT5625_P_OVT_BIT 12
#define RT5625_P_AUX_ADC (0x1 << 11)
#define RT5625_P_AUX_ADC_BIT 11
#define RT5625_P_VDAC (0x1 << 10)
#define RT5625_P_VDAC_BIT 10
#define RT5625_P_DACL (0x1 << 9)
#define RT5625_P_DACL_BIT 9
#define RT5625_P_DACR (0x1 << 8)
#define RT5625_P_DACR_BIT 8
#define RT5625_P_ADCL (0x1 << 7)
#define RT5625_P_ADCL_BIT 7
#define RT5625_P_ADCR (0x1 << 6)
#define RT5625_P_ADCR_BIT 6
#define RT5625_P_HM_L (0x1 << 5)
#define RT5625_P_HM_L_BIT 5
#define RT5625_P_HM_R (0x1 << 4)
#define RT5625_P_HM_R_BIT 4
#define RT5625_P_SM (0x1 << 3)
#define RT5625_P_SM_BIT 3
#define RT5625_P_MM (0x1 << 2)
#define RT5625_P_MM_BIT 2
#define RT5625_P_ADCL_RM (0x1 << 1)
#define RT5625_P_ADCL_RM_BIT 1
#define RT5625_P_ADCR_RM (0x1)
#define RT5625_P_ADCR_RM_BIT 0
/* Power Management Addition 3 (0x3e) */
#define RT5625_P_OSC_EN (0x1 << 15)
#define RT5625_P_OSC_EN_BIT 15
#define RT5625_P_AUX_VOL (0x1 << 14)
#define RT5625_P_AUX_VOL_BIT 14
#define RT5625_P_SPKL_VOL (0x1 << 13)
#define RT5625_P_SPKL_VOL_BIT 13
#define RT5625_P_SPKR_VOL (0x1 << 12)
#define RT5625_P_SPKR_VOL_BIT 12
#define RT5625_P_HPL_VOL (0x1 << 11)
#define RT5625_P_HPL_VOL_BIT 11
#define RT5625_P_HPR_VOL (0x1 << 10)
#define RT5625_P_HPR_VOL_BIT 10
#define RT5625_P_DSP_IF (0x1 << 9)
#define RT5625_P_DSP_IF_BIT 9
#define RT5625_P_DSP_I2C (0x1 << 8)
#define RT5625_P_DSP_I2C_BIT 8
#define RT5625_P_LV_L (0x1 << 7)
#define RT5625_P_LV_L_BIT 7
#define RT5625_P_LV_R (0x1 << 6)
#define RT5625_P_LV_R_BIT 6
#define RT5625_P_PH_VOL (0x1 << 5)
#define RT5625_P_PH_VOL_BIT 5
#define RT5625_P_PH_ADMIX (0x1 << 4)
#define RT5625_P_PH_ADMIX_BIT 4
#define RT5625_P_MIC1_VOL (0x1 << 3)
#define RT5625_P_MIC1_VOL_BIT 3
#define RT5625_P_MIC2_VOL (0x1 << 2)
#define RT5625_P_MIC2_VOL_BIT 2
#define RT5625_P_MIC1_BST (0x1 << 1)
#define RT5625_P_MIC1_BST_BIT 1
#define RT5625_P_MIC2_BST (0x1)
#define RT5625_P_MIC2_BST_BIT 0
/* General Purpose Control Register 1 (0x40) */
#define RT5625_SCLK_MASK (0x1 << 15)
#define RT5625_SCLK_SFT 15
#define RT5625_SCLK_MCLK (0x0 << 15)
#define RT5625_SCLK_PLL1 (0x1 << 15)
#define RT5625_VSCLK_MASK (0x1 << 4)
#define RT5625_VSCLK_SFT 4
#define RT5625_VSCLK_PLL2 (0x0<<4)
#define RT5625_VSCLK_EXTCLK (0x1<<4)
#define RT5625_SPK_R_MASK (0x7 << 1)
#define RT5625_SPK_R_SFT 1
#define RT5625_SPK_R_225V (0x0 << 1)
#define RT5625_SPK_R_200V (0x1 << 1)
#define RT5625_SPK_R_175V (0x2 << 1)
#define RT5625_SPK_R_150V (0x3 << 1)
#define RT5625_SPK_R_125V (0x4 << 1)
#define RT5625_SPK_R_100V (0x5 << 1)
/* General Purpose Control Register 2 (0x42) */
#define RT5625_PLL1_S_MASK (0x3 << 12)
#define RT5625_PLL1_S_SFT 12
#define RT5625_PLL1_S_MCLK (0x0 << 12)
#define RT5625_PLL1_S_BCLK (0x2 << 12)
#define RT5625_PLL1_S_VBCLK (0x3 << 12)
/* PLL2 Control (0x46) */
#define RT5625_PLL2_MASK (0x1 << 15)
#define RT5625_PLL2_DIS (0x0 << 15)
#define RT5625_PLL2_EN (0x1 << 15)
#define RT5625_PLL2_R_MASK (0x1)
#define RT5625_PLL2_R_8X (0x0)
#define RT5625_PLL2_R_16X (0x1)
/* LDO Control (0x48) */
#define RT5625_LDO_MASK (0x1 << 15)
#define RT5625_LDO_DIS (0x0 << 15)
#define RT5625_LDO_EN (0x1 << 15)
#define RT5625_LDO_VC_MASK (0xf)
#define RT5625_LDO_VC_1_55V (0xf<<0)
#define RT5625_LDO_VC_1_50V (0xe<<0)
#define RT5625_LDO_VC_1_45V (0xd<<0)
#define RT5625_LDO_VC_1_40V (0xc<<0)
#define RT5625_LDO_VC_1_35V (0xb<<0)
#define RT5625_LDO_VC_1_30V (0xa<<0)
#define RT5625_LDO_VC_1_25V (0x9<<0)
#define RT5625_LDO_VC_1_20V (0x8<<0)
#define RT5625_LDO_VC_1_15V (0x7<<0)
#define RT5625_LDO_VC_1_05V (0x6<<0)
#define RT5625_LDO_VC_1_00V (0x5<<0)
#define RT5625_LDO_VC_0_95V (0x4<<0)
#define RT5625_LDO_VC_0_90V (0x3<<0)
#define RT5625_LDO_VC_0_85V (0x2<<0)
#define RT5625_LDO_VC_0_80V (0x1<<0)
#define RT5625_LDO_VC_0_75V (0x0<<0)
/* GPIO Pin Configuration (0x4c) */
#define RT5625_GPIO_5 (0x1 << 5)
#define RT5625_GPIO_4 (0x1 << 4)
#define RT5625_GPIO_3 (0x1 << 3)
#define RT5625_GPIO_2 (0x1 << 2)
#define RT5625_GPIO_1 (0x1 << 1)
/* MISC Control (0x5e) */
#define RT5625_FAST_VREF_MASK (0x1 << 15)
#define RT5625_FAST_VREF_EN (0x0 << 15)
#define RT5625_FAST_VREF_DIS (0x1 << 15)
#define RT5625_HP_DEPOP_M2 (0x1 << 8)
#define RT5625_HP_DEPOP_M1 (0x1 << 9)
#define RT5625_HPL_MUM_DEPOP (0x1 << 7)
#define RT5625_HPR_MUM_DEPOP (0x1 << 6)
#define RT5625_MUM_DEPOP (0x1 << 5)
/* Stereo DAC Clock Control 1 (0x60) */
#define RT5625_BCLK_DIV1_MASK (0xf << 12)
#define RT5625_BCLK_DIV1_1 (0x0 << 12)
#define RT5625_BCLK_DIV1_2 (0x1 << 12)
#define RT5625_BCLK_DIV1_3 (0x2 << 12)
#define RT5625_BCLK_DIV1_4 (0x3 << 12)
#define RT5625_BCLK_DIV1_5 (0x4 << 12)
#define RT5625_BCLK_DIV1_6 (0x5 << 12)
#define RT5625_BCLK_DIV1_7 (0x6 << 12)
#define RT5625_BCLK_DIV1_8 (0x7 << 12)
#define RT5625_BCLK_DIV1_9 (0x8 << 12)
#define RT5625_BCLK_DIV1_10 (0x9 << 12)
#define RT5625_BCLK_DIV1_11 (0xa << 12)
#define RT5625_BCLK_DIV1_12 (0xb << 12)
#define RT5625_BCLK_DIV1_13 (0xc << 12)
#define RT5625_BCLK_DIV1_14 (0xd << 12)
#define RT5625_BCLK_DIV1_15 (0xe << 12)
#define RT5625_BCLK_DIV1_16 (0xf << 12)
#define RT5625_BCLK_DIV2_MASK (0x7 << 8)
#define RT5625_BCLK_DIV2_2 (0x0 << 8)
#define RT5625_BCLK_DIV2_4 (0x1 << 8)
#define RT5625_BCLK_DIV2_8 (0x2 << 8)
#define RT5625_BCLK_DIV2_16 (0x3 << 8)
#define RT5625_BCLK_DIV2_32 (0x4 << 8)
#define RT5625_AD_LRCK_DIV1_MASK (0xf << 4)
#define RT5625_AD_LRCK_DIV1_1 (0x0 << 4)
#define RT5625_AD_LRCK_DIV1_2 (0x1 << 4)
#define RT5625_AD_LRCK_DIV1_3 (0x2 << 4)
#define RT5625_AD_LRCK_DIV1_4 (0x3 << 4)
#define RT5625_AD_LRCK_DIV1_5 (0x4 << 4)
#define RT5625_AD_LRCK_DIV1_6 (0x5 << 4)
#define RT5625_AD_LRCK_DIV1_7 (0x6 << 4)
#define RT5625_AD_LRCK_DIV1_8 (0x7 << 4)
#define RT5625_AD_LRCK_DIV1_9 (0x8 << 4)
#define RT5625_AD_LRCK_DIV1_10 (0x9 << 4)
#define RT5625_AD_LRCK_DIV1_11 (0xa << 4)
#define RT5625_AD_LRCK_DIV1_12 (0xb << 4)
#define RT5625_AD_LRCK_DIV1_13 (0xc << 4)
#define RT5625_AD_LRCK_DIV1_14 (0xd << 4)
#define RT5625_AD_LRCK_DIV1_15 (0xe << 4)
#define RT5625_AD_LRCK_DIV1_16 (0xf << 4)
#define RT5625_AD_LRCK_DIV2_MASK (0x7 << 1)
#define RT5625_AD_LRCK_DIV2_2 (0x0 << 1)
#define RT5625_AD_LRCK_DIV2_4 (0x1 << 1)
#define RT5625_AD_LRCK_DIV2_8 (0x2 << 1)
#define RT5625_AD_LRCK_DIV2_16 (0x3 << 1)
#define RT5625_AD_LRCK_DIV2_32 (0x4 << 1)
#define RT5625_DA_LRCK_DIV_MASK (1)
#define RT5625_DA_LRCK_DIV_32 (0)
#define RT5625_DA_LRCK_DIV_64 (1)
/* Stereo DAC Clock Control 2 (0x62) */
#define RT5625_DF_DIV1_MASK (0xF << 12)
#define RT5625_DF_DIV1_1 (0x0 << 12)
#define RT5625_DF_DIV1_2 (0x1 << 12)
#define RT5625_DF_DIV1_3 (0x2 << 12)
#define RT5625_DF_DIV1_4 (0x3 << 12)
#define RT5625_DF_DIV1_5 (0x4 << 12)
#define RT5625_DF_DIV1_6 (0x5 << 12)
#define RT5625_DF_DIV1_7 (0x6 << 12)
#define RT5625_DF_DIV1_8 (0x7 << 12)
#define RT5625_DF_DIV1_9 (0x8 << 12)
#define RT5625_DF_DIV1_10 (0x9 << 12)
#define RT5625_DF_DIV1_11 (0xA << 12)
#define RT5625_DF_DIV1_12 (0xB << 12)
#define RT5625_DF_DIV1_13 (0xC << 12)
#define RT5625_DF_DIV1_14 (0xD << 12)
#define RT5625_DF_DIV1_15 (0xE << 12)
#define RT5625_DF_DIV1_16 (0xF << 12)
#define RT5625_DF_DIV2_MASK (0x7 << 9)
#define RT5625_DF_DIV2_2 (0x0 << 9)
#define RT5625_DF_DIV2_4 (0x1 << 9)
#define RT5625_DF_DIV2_8 (0x2 << 9)
#define RT5625_DF_DIV2_16 (0x3 << 9)
#define RT5625_DF_DIV2_32 (0x4 << 9)
#define RT5625_AF_DIV1_MASK (0xF << 4)
#define RT5625_AF_DIV1_1 (0x0 << 4)
#define RT5625_AF_DIV1_2 (0x1 << 4)
#define RT5625_AF_DIV1_3 (0x2 << 4)
#define RT5625_AF_DIV1_4 (0x3 << 4)
#define RT5625_AF_DIV1_5 (0x4 << 4)
#define RT5625_AF_DIV1_6 (0x5 << 4)
#define RT5625_AF_DIV1_7 (0x6 << 4)
#define RT5625_AF_DIV1_8 (0x7 << 4)
#define RT5625_AF_DIV1_9 (0x8 << 4)
#define RT5625_AF_DIV1_10 (0x9 << 4)
#define RT5625_AF_DIV1_11 (0xA << 4)
#define RT5625_AF_DIV1_12 (0xB << 4)
#define RT5625_AF_DIV1_13 (0xC << 4)
#define RT5625_AF_DIV1_14 (0xD << 4)
#define RT5625_AF_DIV1_15 (0xE << 4)
#define RT5625_AF_DIV1_16 (0xF << 4)
#define RT5625_AF_DIV2_MASK (0x7 << 1)
#define RT5625_AF_DIV2_1 (0x0 << 1)
#define RT5625_AF_DIV2_2 (0x1 << 1)
#define RT5625_AF_DIV2_4 (0x2 << 1)
#define RT5625_AF_DIV2_8 (0x3 << 1)
#define RT5625_AF_DIV2_16 (0x4 << 1)
#define RT5625_AF_DIV2_32 (0x5 << 1)
/* Voice DAC PCM Clock Control 1 (0x64) */
#define RT5625_VBCLK_DIV1_MASK (0xF << 12)
#define RT5625_VBCLK_DIV1_1 (0x0 << 12)
#define RT5625_VBCLK_DIV1_2 (0x1 << 12)
#define RT5625_VBCLK_DIV1_3 (0x2 << 12)
#define RT5625_VBCLK_DIV1_4 (0x3 << 12)
#define RT5625_VBCLK_DIV1_5 (0x4 << 12)
#define RT5625_VBCLK_DIV1_6 (0x5 << 12)
#define RT5625_VBCLK_DIV1_7 (0x6 << 12)
#define RT5625_VBCLK_DIV1_8 (0x7 << 12)
#define RT5625_VBCLK_DIV1_9 (0x8 << 12)
#define RT5625_VBCLK_DIV1_10 (0x9 << 12)
#define RT5625_VBCLK_DIV1_11 (0xA << 12)
#define RT5625_VBCLK_DIV1_12 (0xB << 12)
#define RT5625_VBCLK_DIV1_13 (0xC << 12)
#define RT5625_VBCLK_DIV1_14 (0xD << 12)
#define RT5625_VBCLK_DIV1_15 (0xE << 12)
#define RT5625_VBCLK_DIV1_16 (0xF << 12)
#define RT5625_VBCLK_DIV2_MASK (0x7 << 8)
#define RT5625_VBCLK_DIV2_2 (0x0 << 8)
#define RT5625_VBCLK_DIV2_4 (0x1 << 8)
#define RT5625_VBCLK_DIV2_8 (0x2 << 8)
#define RT5625_VBCLK_DIV2_16 (0x3 << 8)
#define RT5625_VBCLK_DIV2_32 (0x4 << 8)
#define RT5625_AD_VLRCK_DIV1_MASK (0xF << 4)
#define RT5625_AD_VLRCK_DIV1_1 (0x0 << 4)
#define RT5625_AD_VLRCK_DIV1_2 (0x1 << 4)
#define RT5625_AD_VLRCK_DIV1_3 (0x2 << 4)
#define RT5625_AD_VLRCK_DIV1_4 (0x3 << 4)
#define RT5625_AD_VLRCK_DIV1_5 (0x4 << 4)
#define RT5625_AD_VLRCK_DIV1_6 (0x5 << 4)
#define RT5625_AD_VLRCK_DIV1_7 (0x6 << 4)
#define RT5625_AD_VLRCK_DIV1_8 (0x7 << 4)
#define RT5625_AD_VLRCK_DIV1_9 (0x8 << 4)
#define RT5625_AD_VLRCK_DIV1_10 (0x9 << 4)
#define RT5625_AD_VLRCK_DIV1_11 (0xA << 4)
#define RT5625_AD_VLRCK_DIV1_12 (0xB << 4)
#define RT5625_AD_VLRCK_DIV1_13 (0xC << 4)
#define RT5625_AD_VLRCK_DIV1_14 (0xD << 4)
#define RT5625_AD_VLRCK_DIV1_15 (0xE << 4)
#define RT5625_AD_VLRCK_DIV1_16 (0xF << 4)
#define RT5625_AD_VLRCK_DIV2_MASK (0x7 << 1)
#define RT5625_AD_VLRCK_DIV2_2 (0x0 << 1)
#define RT5625_AD_VLRCK_DIV2_4 (0x1 << 1)
#define RT5625_AD_VLRCK_DIV2_8 (0x2 << 1)
#define RT5625_AD_VLRCK_DIV2_16 (0x3 << 1)
#define RT5625_AD_VLRCK_DIV2_32 (0x4 << 1)
#define RT5625_DA_VLRCK_DIV_MASK (1)
#define RT5625_DA_VLRCK_DIV_32 (0)
#define RT5625_DA_VLRCK_DIV_64 (1)
/* Psedueo Stereo & Spatial Effect Block Control (0x68) */
#define RT5625_SP_CTRL_EN (0x1 << 15)
#define RT5625_APF_EN (0x1 << 14)
#define RT5625_PS_EN (0x1 << 13)
#define RT5625_STO_EXP_EN (0x1 << 12)
#define RT5625_SP_3D_G1_MASK (0x3 << 10)
#define RT5625_SP_3D_G1_1_0 (0x0 << 10)
#define RT5625_SP_3D_G1_1_5 (0x1 << 10)
#define RT5625_SP_3D_G1_2_0 (0x2 << 10)
#define RT5625_SP_3D_R1_MASK (0x3 << 8)
#define RT5625_SP_3D_R1_0_0 (0x0 << 8)
#define RT5625_SP_3D_R1_0_66 (0x1 << 8)
#define RT5625_SP_3D_R1_1_0 (0x2 << 8)
#define RT5625_SP_3D_G2_MASK (0x3 << 6)
#define RT5625_SP_3D_G2_1_0 (0x0 << 6)
#define RT5625_SP_3D_G2_1_5 (0x1 << 6)
#define RT5625_SP_3D_G2_2_0 (0x2 << 6)
#define RT5625_SP_3D_R2_MASK (0x3 << 4)
#define RT5625_SP_3D_R2_0_0 (0x0 << 4)
#define RT5625_SP_3D_R2_0_66 (0x1 << 4)
#define RT5625_SP_3D_R2_1_0 (0x2 << 4)
#define RT5625_APF_MASK (0x3)
#define RT5625_APF_48K (0x3)
#define RT5625_APF_44_1K (0x2)
#define RT5625_APF_32K (0x1)
/* EQ Control and Status /ADC HPF Control (0x6E) */
#define RT5625_EN_HW_EQ_BLK (0x1 << 15)
#define RT5625_EQ_SRC_DAC (0x0 << 14)
#define RT5625_EQ_SRC_ADC (0x1 << 14)
#define RT5625_EQ_CHG_EN (0x1 << 7)
#define RT5625_EN_HW_EQ_HPF (0x1 << 4)
#define RT5625_EN_HW_EQ_BP3 (0x1 << 3)
#define RT5625_EN_HW_EQ_BP2 (0x1 << 2)
#define RT5625_EN_HW_EQ_BP1 (0x1 << 1)
#define RT5625_EN_HW_EQ_LPF (0x1 << 0)
/* VoDSP Register Command (0x74) */
#define RT5625_DSP_BUSY_MASK (0x1 << 15)
#define RT5625_DSP_DS_MASK (0x1 << 14)
#define RT5625_DSP_DS_VODSP (0x0 << 14)
#define RT5625_DSP_DS_REG72 (0x1 << 14)
#define RT5625_DSP_CLK_MASK (0x3 << 12)
#define RT5625_DSP_CLK_12_288M (0x0 << 12)
#define RT5625_DSP_CLK_6_144M (0x1 << 12)
#define RT5625_DSP_CLK_3_072M (0x2 << 12)
#define RT5625_DSP_CLK_2_048M (0x3 << 12)
#define RT5625_DSP_R_EN (0x1 << 9)
#define RT5625_DSP_W_EN (0x1 << 8)
#define RT5625_DSP_CMD_MASK (0xff)
#define RT5625_DSP_CMD_SFT 0
#define RT5625_DSP_CMD_MW (0x3B) /* Memory Write */
#define RT5625_DSP_CMD_MR (0x37) /* Memory Read */
#define RT5625_DSP_CMD_RR (0x60) /* Register Read */
#define RT5625_DSP_CMD_RW (0x68) /* Register Write */
/* Index(0x20) for Auto Volume Control */
#define RT5625_AVC_CH_MASK (0x1 << 7)
#define RT5625_AVC_CH_L_CH (0x0 << 7)
#define RT5625_AVC_CH_R_CH (0x1 << 7)
#define RT5625_AVC_GAIN_EN (0x1 << 15)
enum {
RT5625_AIF1,
RT5625_AIF2,
};
/* System Clock Source */
enum {
RT5625_SCLK_S_MCLK,
RT5625_SCLK_S_PLL,
};
enum pll_sel {
RT5625_PLL_MCLK = 0,
RT5625_PLL_MCLK_TO_VSYSCLK,
RT5625_PLL_BCLK,
RT5625_PLL_VBCLK,
};
enum {
RT5625_AEC_DIS,
RT5625_AEC_EN,
};
//#ifdef RT5625_F_SMT_PHO
enum {
RT5625_PLL_DIS,
RT5625_PLL_112896_225792,
RT5625_PLL_112896_24576,
};
//#endif
typedef struct {
unsigned short index;
unsigned short value;
} rt5625_dsp_reg;
#endif

179
sound/soc/codecs/rt_codec_ioctl.c
View File

@@ -1,179 +0,0 @@
/*
* rt_codec_ioctl.h -- RT56XX ALSA SoC audio driver IO control
*
* Copyright 2012 Realtek Microelectronics
* Author: Bard <bardliao@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/spi/spi.h>
#include <sound/soc.h>
#include "rt_codec_ioctl.h"
static struct rt_codec_ops rt_codec_ioctl_ops;
#if defined(CONFIG_SND_HWDEP) || defined(CONFIG_SND_HWDEP_MODULE)
#define RT_CE_CODEC_HWDEP_NAME "rt_codec hwdep "
static int rt_codec_hwdep_open(struct snd_hwdep *hw, struct file *file)
{
struct snd_soc_codec *codec = hw->private_data;
dev_dbg(codec->dev, "%s()\n", __func__);
return 0;
}
static int rt_codec_hwdep_release(struct snd_hwdep *hw, struct file *file)
{
struct snd_soc_codec *codec = hw->private_data;
dev_dbg(codec->dev, "%s()\n", __func__);
return 0;
}
static int rt_codec_hwdep_ioctl_common(struct snd_hwdep *hw,
struct file *file, unsigned int cmd, unsigned long arg)
{
struct snd_soc_codec *codec = hw->private_data;
struct rt_codec_cmd __user *_rt_codec = (struct rt_codec_cmd *)arg;
struct rt_codec_cmd rt_codec;
int *buf, *p;
if (copy_from_user(&rt_codec, _rt_codec, sizeof(rt_codec))) {
dev_err(codec->dev,"copy_from_user faild\n");
return -EFAULT;
}
dev_dbg(codec->dev, "%s(): rt_codec.number=%zu, cmd=%d\n",
__func__, rt_codec.number, cmd);
buf = kmalloc(sizeof(*buf) * rt_codec.number, GFP_KERNEL);
if (buf == NULL)
return -ENOMEM;
if (copy_from_user(buf, rt_codec.buf, sizeof(*buf) * rt_codec.number)) {
goto err;
}
switch (cmd) {
case RT_READ_CODEC_REG_IOCTL:
for (p = buf; p < buf + rt_codec.number / 2; p++) {
*(p + rt_codec.number / 2) = snd_soc_read(codec, *p);
}
if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * rt_codec.number))
goto err;
break;
case RT_WRITE_CODEC_REG_IOCTL:
for (p = buf; p < buf + rt_codec.number / 2; p++)
snd_soc_write(codec, *p, *(p + rt_codec.number / 2));
break;
case RT_READ_CODEC_INDEX_IOCTL:
if (NULL == rt_codec_ioctl_ops.index_read)
goto err;
for (p = buf; p < buf + rt_codec.number / 2; p++)
*(p+rt_codec.number/2) = rt_codec_ioctl_ops.index_read(
codec, *p);
if (copy_to_user(rt_codec.buf, buf,
sizeof(*buf) * rt_codec.number))
goto err;
break;
case RT_WRITE_CODEC_INDEX_IOCTL:
if (NULL == rt_codec_ioctl_ops.index_write)
goto err;
for (p = buf; p < buf + rt_codec.number / 2; p++)
rt_codec_ioctl_ops.index_write(codec, *p,
*(p+rt_codec.number/2));
break;
default:
if (NULL == rt_codec_ioctl_ops.ioctl_common)
goto err;
rt_codec_ioctl_ops.ioctl_common(hw, file, cmd, arg);
break;
}
kfree(buf);
return 0;
err:
kfree(buf);
return -EFAULT;
}
static int rt_codec_codec_dump_reg(struct snd_hwdep *hw,
struct file *file, unsigned long arg)
{
struct snd_soc_codec *codec = hw->private_data;
struct rt_codec_cmd __user *_rt_codec =(struct rt_codec_cmd *)arg;
struct rt_codec_cmd rt_codec;
int i, *buf, number = codec->driver->reg_cache_size;
dev_dbg(codec->dev, "enter %s, number = %d\n", __func__, number);
if (copy_from_user(&rt_codec, _rt_codec, sizeof(rt_codec)))
return -EFAULT;
buf = kmalloc(sizeof(*buf) * number, GFP_KERNEL);
if (buf == NULL)
return -ENOMEM;
for (i = 0; i < number/2; i++) {
buf[i] = i << 1;
buf[i + number / 2] = codec->read(codec, buf[i]);
}
if (copy_to_user(rt_codec.buf, buf, sizeof(*buf) * i))
goto err;
rt_codec.number = number;
if (copy_to_user(_rt_codec, &rt_codec, sizeof(rt_codec)))
goto err;
kfree(buf);
return 0;
err:
kfree(buf);
return -EFAULT;
}
static int rt_codec_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
unsigned int cmd, unsigned long arg)
{
switch (cmd) {
case RT_READ_ALL_CODEC_REG_IOCTL:
return rt_codec_codec_dump_reg(hw, file, arg);
default:
return rt_codec_hwdep_ioctl_common(hw, file, cmd, arg);
}
return 0;
}
int realtek_ce_init_hwdep(struct snd_soc_codec *codec)
{
struct snd_hwdep *hw;
struct snd_card *card = codec->card->snd_card;
int err;
dev_dbg(codec->dev, "enter %s\n", __func__);
if ((err = snd_hwdep_new(card, RT_CE_CODEC_HWDEP_NAME, 0, &hw)) < 0)
return err;
strcpy(hw->name, RT_CE_CODEC_HWDEP_NAME);
hw->private_data = codec;
hw->ops.open = rt_codec_hwdep_open;
hw->ops.release = rt_codec_hwdep_release;
hw->ops.ioctl = rt_codec_hwdep_ioctl;
return 0;
}
EXPORT_SYMBOL_GPL(realtek_ce_init_hwdep);
#endif
struct rt_codec_ops *rt_codec_get_ioctl_ops(void)
{
return &rt_codec_ioctl_ops;
}
EXPORT_SYMBOL_GPL(rt_codec_get_ioctl_ops);

78
sound/soc/codecs/rt_codec_ioctl.h
View File

@@ -1,78 +0,0 @@
/*
* rt_codec_ioctl.h -- RT56XX ALSA SoC audio driver IO control
*
* Copyright 2012 Realtek Microelectronics
* Author: Bard <bardliao@realtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RT56XX_IOCTL_H__
#define __RT56XX_IOCTL_H__
#include <sound/hwdep.h>
#include <linux/ioctl.h>
struct rt_codec_cmd {
size_t number;
int __user *buf;
};
struct rt_codec_ops {
int (*index_write)(struct snd_soc_codec *codec,
unsigned int reg, unsigned int value);
unsigned int (*index_read)(struct snd_soc_codec *codec,
unsigned int reg);
int (*index_update_bits)(struct snd_soc_codec *codec,
unsigned int reg, unsigned int mask, unsigned int value);
int (*ioctl_common)(struct snd_hwdep *hw, struct file *file,
unsigned int cmd, unsigned long arg);
};
enum {
RT_READ_CODEC_REG_IOCTL = _IOR('R', 0x01, struct rt_codec_cmd),
RT_WRITE_CODEC_REG_IOCTL = _IOW('R', 0x01, struct rt_codec_cmd),
RT_READ_ALL_CODEC_REG_IOCTL = _IOR('R', 0x02, struct rt_codec_cmd),
RT_READ_CODEC_INDEX_IOCTL = _IOR('R', 0x03, struct rt_codec_cmd),
RT_WRITE_CODEC_INDEX_IOCTL = _IOW('R', 0x03, struct rt_codec_cmd),
RT_READ_CODEC_DSP_IOCTL = _IOR('R', 0x04, struct rt_codec_cmd),
RT_WRITE_CODEC_DSP_IOCTL = _IOW('R', 0x04, struct rt_codec_cmd),
RT_SET_CODEC_HWEQ_IOCTL = _IOW('R', 0x05, struct rt_codec_cmd),
RT_GET_CODEC_HWEQ_IOCTL = _IOR('R', 0x05, struct rt_codec_cmd),
RT_SET_CODEC_SPK_VOL_IOCTL = _IOW('R', 0x06, struct rt_codec_cmd),
RT_GET_CODEC_SPK_VOL_IOCTL = _IOR('R', 0x06, struct rt_codec_cmd),
RT_SET_CODEC_MIC_GAIN_IOCTL = _IOW('R', 0x07, struct rt_codec_cmd),
RT_GET_CODEC_MIC_GAIN_IOCTL = _IOR('R', 0x07, struct rt_codec_cmd),
RT_SET_CODEC_3D_SPK_IOCTL = _IOW('R', 0x08, struct rt_codec_cmd),
RT_GET_CODEC_3D_SPK_IOCTL = _IOR('R', 0x08, struct rt_codec_cmd),
RT_SET_CODEC_MP3PLUS_IOCTL = _IOW('R', 0x09, struct rt_codec_cmd),
RT_GET_CODEC_MP3PLUS_IOCTL = _IOR('R', 0x09, struct rt_codec_cmd),
RT_SET_CODEC_3D_HEADPHONE_IOCTL = _IOW('R', 0x0a, struct rt_codec_cmd),
RT_GET_CODEC_3D_HEADPHONE_IOCTL = _IOR('R', 0x0a, struct rt_codec_cmd),
RT_SET_CODEC_BASS_BACK_IOCTL = _IOW('R', 0x0b, struct rt_codec_cmd),
RT_GET_CODEC_BASS_BACK_IOCTL = _IOR('R', 0x0b, struct rt_codec_cmd),
RT_SET_CODEC_DIPOLE_SPK_IOCTL = _IOW('R', 0x0c, struct rt_codec_cmd),
RT_GET_CODEC_DIPOLE_SPK_IOCTL = _IOR('R', 0x0c, struct rt_codec_cmd),
RT_SET_CODEC_DRC_AGC_ENABLE_IOCTL = _IOW('R', 0x0d, struct rt_codec_cmd),
RT_GET_CODEC_DRC_AGC_ENABLE_IOCTL = _IOR('R', 0x0d, struct rt_codec_cmd),
RT_SET_CODEC_DSP_MODE_IOCTL = _IOW('R', 0x0e, struct rt_codec_cmd),
RT_GET_CODEC_DSP_MODE_IOCTL = _IOR('R', 0x0e, struct rt_codec_cmd),
RT_SET_CODEC_WNR_ENABLE_IOCTL = _IOW('R', 0x0f, struct rt_codec_cmd),
RT_GET_CODEC_WNR_ENABLE_IOCTL = _IOR('R', 0x0f, struct rt_codec_cmd),
RT_SET_CODEC_DRC_AGC_PAR_IOCTL = _IOW('R', 0x10, struct rt_codec_cmd),
RT_GET_CODEC_DRC_AGC_PAR_IOCTL = _IOR('R', 0x10, struct rt_codec_cmd),
RT_SET_CODEC_DIGI_BOOST_GAIN_IOCTL = _IOW('R', 0x11, struct rt_codec_cmd),
RT_GET_CODEC_DIGI_BOOST_GAIN_IOCTL = _IOR('R', 0x11, struct rt_codec_cmd),
RT_SET_CODEC_NOISE_GATE_IOCTL = _IOW('R', 0x12, struct rt_codec_cmd),
RT_GET_CODEC_NOISE_GATE_IOCTL = _IOR('R', 0x12, struct rt_codec_cmd),
RT_SET_CODEC_DRC_AGC_COMP_IOCTL = _IOW('R', 0x13, struct rt_codec_cmd),
RT_GET_CODEC_DRC_AGC_COMP_IOCTL = _IOR('R', 0x13, struct rt_codec_cmd),
RT_GET_CODEC_ID = _IOR('R', 0x30, struct rt_codec_cmd),
};
int realtek_ce_init_hwdep(struct snd_soc_codec *codec);
struct rt_codec_ops *rt_codec_get_ioctl_ops(void);
#endif /* __RT56XX_IOCTL_H__ */

307
sound/soc/codecs/tc358749x.c
View File

@@ -1,307 +0,0 @@
/*
* tc358749x.c TC358749XBG ALSA SoC audio codec driver
*
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
* Author: Roy <luoxiaotan@rock-chips.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.*
*
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/of_gpio.h>
#include <linux/regmap.h>
#include <sound/soc.h>
#include "tc358749x.h"
static int snd_tc358749x_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *codec_dai)
{
struct snd_soc_codec *codec = codec_dai->codec;
unsigned int fs;
switch (params_rate(params)) {
case 32000:
fs = FS_32000;
break;
case 44100:
fs = FS_44100;
break;
case 48000:
fs = FS_48000;
break;
case 88200:
fs = FS_88200;
break;
case 96000:
fs = FS_96000;
break;
case 176400:
fs = FS_176400;
break;
case 192000:
fs = FS_192000;
break;
default:
dev_err(codec->dev, "Enter:%s, %d, Error rate=%d\n",
__func__, __LINE__, params_rate(params));
return -EINVAL;
}
snd_soc_update_bits(codec, TC358749X_FS_SET, FS_SET_MASK, fs);
return 0;
}
static int snd_tc358749x_mute(struct snd_soc_dai *dai, int mute)
{
struct snd_soc_codec *codec = dai->codec;
if (mute)
snd_soc_update_bits(codec, TC358749X_FORCE_MUTE,
FORCE_DMUTE_MASK, MUTE);
else
snd_soc_update_bits(codec, TC358749X_FORCE_MUTE,
FORCE_DMUTE_MASK, !MUTE);
return 0;
}
static const struct snd_soc_dai_ops tc358749x_dai_ops = {
.hw_params = snd_tc358749x_dai_hw_params,
.digital_mute = snd_tc358749x_mute,
};
static struct snd_soc_dai_driver tc358749x_dai = {
.name = "tc358749x-audio",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
},
.capture = {
.stream_name = "Capture",
.channels_min = 2,
.channels_max = 8,
.rates = SNDRV_PCM_RATE_32000 |
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
.formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
},
.ops = &tc358749x_dai_ops,
};
static int tc358749x_probe(struct snd_soc_codec *codec)
{
snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
return 0;
}
static int tc358749_set_bias_level(struct snd_soc_codec *codec,
enum snd_soc_bias_level level)
{
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
snd_soc_update_bits(codec, TC358749X_FORCE_MUTE,
FORCE_DMUTE_MASK, !MUTE);
break;
case SND_SOC_BIAS_STANDBY:
break;
case SND_SOC_BIAS_OFF:
snd_soc_update_bits(codec, TC358749X_FORCE_MUTE,
FORCE_DMUTE_MASK, MUTE);
break;
}
return 0;
}
static struct snd_soc_codec_driver soc_codec_dev_tc358749x = {
.probe = tc358749x_probe,
.set_bias_level = tc358749_set_bias_level,
};
static bool tc358749x_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case TC358749X_FORCE_MUTE:
case TC358749X_FS_SET:
return true;
default:
return false;
}
}
static const struct reg_default tc358749x_reg_defaults[] = {
{ TC358749X_FORCE_MUTE, 0xb1 },
{ TC358749X_FS_SET, 0x00 },
};
const struct regmap_config tc358749x_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.max_register = TC358749X_FS_SET,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = tc358749x_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(tc358749x_reg_defaults),
.readable_reg = tc358749x_readable_register,
};
static const struct i2c_device_id tc358749x_i2c_id[] = {
{ "tc358749x", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tc358749x_i2c_id);
static int tc358749x_parse_dts(struct i2c_client *i2c,
struct tc358749x_priv *tc358749x)
{
int ret = 0;
struct device *dev = &i2c->dev;
tc358749x->gpio_power18 = devm_gpiod_get_optional(dev, "power18",
GPIOD_OUT_LOW);
tc358749x->gpio_power = devm_gpiod_get_optional(dev, "power",
GPIOD_OUT_LOW);
if (IS_ERR(tc358749x->gpio_power)) {
ret = PTR_ERR(tc358749x->gpio_power);
dev_err(&i2c->dev, "Unable to claim gpio \"power\".\n");
return ret;
}
tc358749x->gpio_power33 = devm_gpiod_get_optional(dev, "power33",
GPIOD_OUT_LOW);
tc358749x->gpio_int = devm_gpiod_get_optional(dev, "int",
GPIOD_OUT_LOW);
if (IS_ERR(tc358749x->gpio_int)) {
ret = PTR_ERR(tc358749x->gpio_int);
dev_err(&i2c->dev, "Unable to claim gpio \"int\".\n");
return ret;
}
tc358749x->gpio_reset = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(tc358749x->gpio_reset)) {
ret = PTR_ERR(tc358749x->gpio_reset);
dev_err(&i2c->dev, "Unable to claim gpio \"reset\".\n");
return ret;
}
tc358749x->gpio_csi_ctl = devm_gpiod_get_optional(dev, "csi-ctl",
GPIOD_OUT_LOW);
if (IS_ERR(tc358749x->gpio_csi_ctl)) {
ret = PTR_ERR(tc358749x->gpio_csi_ctl);
dev_err(&i2c->dev, "Unable to claim gpio \"csi-ctl\".\n");
}
tc358749x->gpio_stanby = devm_gpiod_get_optional(dev, "stanby",
GPIOD_OUT_LOW);
if (IS_ERR(tc358749x->gpio_stanby)) {
ret = PTR_ERR(tc358749x->gpio_stanby);
dev_err(&i2c->dev, "Unable to claim gpio \"stanby\".\n");
return ret;
}
if (IS_ERR(tc358749x->gpio_power18)) {
ret = PTR_ERR(tc358749x->gpio_power18);
dev_err(&i2c->dev, "Unable to claim gpio \"power18\".\n");
} else {
gpiod_direction_output(tc358749x->gpio_power18, 1);
}
if (IS_ERR(tc358749x->gpio_power33)) {
ret = PTR_ERR(tc358749x->gpio_power33);
dev_err(&i2c->dev, "Unable to claim gpio \"power33\".\n");
} else {
gpiod_direction_output(tc358749x->gpio_power33, 1);
}
gpiod_direction_output(tc358749x->gpio_power, 1);
gpiod_direction_output(tc358749x->gpio_stanby, 1);
gpiod_direction_output(tc358749x->gpio_reset, 1);
/* Wait 10ms tc358749x lock I2C Slave address */
usleep_range(10000, 11000);
/* after I2C address has been lock and set it input */
gpiod_direction_input(tc358749x->gpio_int);
return 0;
}
static int tc358749x_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct tc358749x_priv *tc358749x;
int ret;
tc358749x = devm_kzalloc(&i2c->dev, sizeof(*tc358749x),
GFP_KERNEL);
if (!tc358749x)
return -ENOMEM;
i2c_set_clientdata(i2c, tc358749x);
tc358749x_parse_dts(i2c, tc358749x);
tc358749x->regmap = devm_regmap_init_i2c(i2c, &tc358749x_regmap_config);
if (IS_ERR(tc358749x->regmap)) {
ret = PTR_ERR(tc358749x->regmap);
dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
return ret;
}
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_tc358749x,
&tc358749x_dai, 1);
dev_info(&i2c->dev, "%s success\n", __func__);
return ret;
}
static int tc358749x_i2c_remove(struct i2c_client *i2c)
{
snd_soc_unregister_codec(&i2c->dev);
return 0;
}
static struct i2c_driver tc358749x_i2c_driver = {
.driver = {
.name = "tc358749x",
},
.probe = tc358749x_i2c_probe,
.remove = tc358749x_i2c_remove,
.id_table = tc358749x_i2c_id,
};
module_i2c_driver(tc358749x_i2c_driver);
MODULE_AUTHOR("Roy <luoxiaotan@rock-chips.com>");
MODULE_DESCRIPTION("TC358749X HDMI Audio RX ASoC Interface");
MODULE_LICENSE("GPL");