shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-05 18:41:58 +09:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: rockchip: rv1126b: add clk_cpll_div10 assigned clk rate

Browse Source 
Change-Id: I2fdedc4ebd266082ac09514c5749f509f5a9cb2b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2025-06-09 16:22:48 +08:00
committed by Tao Huang
parent d804f23988
commit dc6b7b1715
1 changed files with 4 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/rockchip/rv1126b.dtsi
View File

@@ -940,7 +940,8 @@
<&cru CLK_UART_FRAC0>, <&cru CLK_UART_FRAC1>,
<&cru CLK_CM_FRAC0>, <&cru CLK_CM_FRAC1>,
<&cru CLK_CM_FRAC2>, <&cru CLK_AUDIO_FRAC0>,
<&cru CLK_AUDIO_FRAC1>;
<&cru CLK_AUDIO_FRAC1>, <&cru CLK_AISP_PLL>,
<&cru CLK_CPLL_DIV10>;
assigned-clock-rates =
<1188000000>, <1000000000>,
<786432000>, <786432000>,
@@ -950,7 +951,8 @@
<96000000>, <128000000>,
<18432000>, <500000000>,
<32768000>, <45158400>,
<49152000>;
<49152000>, <393216000>,
<98304000>;
};
grf: syscon@20100000 {