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dv: add tm2 interface [1/1]

Browse Source 
PD#SWPL-6338

Problem:
need to add dv interface in tm2

Solution:
choose dv in UI and play films, observe the video and
graphic

Verify:
ab301 verify ok

Change-Id: I5d85b195254a16bcc9046d258728bd41d8a809d5
Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
This commit is contained in:
Yi Zhou
2019-03-14 16:05:59 +08:00
committed by Chris KIM
parent c21b2a4a94
commit dc9760e4be
4 changed files with 897 additions and 673 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1415
drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.c
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File diff suppressed because it is too large Load Diff

1
drivers/amlogic/media/enhancement/amdolby_vision/amdolby_vision.h
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@@ -526,6 +526,7 @@ enum cpuID_e {
_CPU_MAJOR_ID_GXM,
_CPU_MAJOR_ID_TXLX,
_CPU_MAJOR_ID_G12,
_CPU_MAJOR_ID_TM2,
_CPU_MAJOR_ID_UNKNOWN,
};

149
drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h
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@@ -18,78 +18,101 @@
#ifndef VPP_DOLBYVISION_REGS_H
#define VPP_DOLBYVISION_REGS_H
#define DOLBY_CORE1_REG_START 0x3300
#define DOLBY_CORE1_CLKGATE_CTRL 0x33f2
#define DOLBY_CORE1_SWAP_CTRL0 0x33f3
#define DOLBY_CORE1_SWAP_CTRL1 0x33f4
#define DOLBY_CORE1_SWAP_CTRL2 0x33f5
#define DOLBY_CORE1_SWAP_CTRL3 0x33f6
#define DOLBY_CORE1_SWAP_CTRL4 0x33f7
#define DOLBY_CORE1_SWAP_CTRL5 0x33f8
#define DOLBY_CORE1_DMA_CTRL 0x33f9
#define DOLBY_CORE1_DMA_STATUS 0x33fa
#define DOLBY_CORE1_STATUS0 0x33fb
#define DOLBY_CORE1_STATUS1 0x33fc
#define DOLBY_CORE1_STATUS2 0x33fd
#define DOLBY_CORE1_STATUS3 0x33fe
#define DOLBY_CORE1_DMA_PORT 0x33ff
#define CORE1_OFFSET (0x1UL << 24)
#define CORE1_1_OFFSET (0x1UL << 25)
#define CORE2A_OFFSET (0x1UL << 26)
#define CORE3_OFFSET (0x1UL << 27)
#define CORETV_OFFSET (0x1UL << 28)
#define DOLBY_CORE2A_REG_START 0x3400
#define DOLBY_CORE2A_CTRL 0x3401
#define DOLBY_CORE2A_CLKGATE_CTRL 0x3432
#define DOLBY_CORE2A_SWAP_CTRL0 0x3433
#define DOLBY_CORE2A_SWAP_CTRL1 0x3434
#define DOLBY_CORE2A_SWAP_CTRL2 0x3435
#define DOLBY_CORE2A_SWAP_CTRL3 0x3436
#define DOLBY_CORE2A_SWAP_CTRL4 0x3437
#define DOLBY_CORE2A_SWAP_CTRL5 0x3438
#define DOLBY_CORE2A_DMA_CTRL 0x3439
#define DOLBY_CORE2A_DMA_STATUS 0x343a
#define DOLBY_CORE2A_STATUS0 0x343b
#define DOLBY_CORE2A_STATUS1 0x343c
#define DOLBY_CORE2A_STATUS2 0x343d
#define DOLBY_CORE2A_STATUS3 0x343e
#define DOLBY_CORE2A_DMA_PORT 0x343f
#define DOLBY_CORE1_REG_START (0x00 + CORE1_OFFSET)
#define DOLBY_CORE1_CLKGATE_CTRL (0xf2 + CORE1_OFFSET)
#define DOLBY_CORE1_SWAP_CTRL0 (0xf3 + CORE1_OFFSET)
#define DOLBY_CORE1_SWAP_CTRL1 (0xf4 + CORE1_OFFSET)
#define DOLBY_CORE1_SWAP_CTRL2 (0xf5 + CORE1_OFFSET)
#define DOLBY_CORE1_SWAP_CTRL3 (0xf6 + CORE1_OFFSET)
#define DOLBY_CORE1_SWAP_CTRL4 (0xf7 + CORE1_OFFSET)
#define DOLBY_CORE1_SWAP_CTRL5 (0xf8 + CORE1_OFFSET)
#define DOLBY_CORE1_DMA_CTRL (0xf9 + CORE1_OFFSET)
#define DOLBY_CORE1_DMA_STATUS (0xfa + CORE1_OFFSET)
#define DOLBY_CORE1_STATUS0 (0xfb + CORE1_OFFSET)
#define DOLBY_CORE1_STATUS1 (0xfc + CORE1_OFFSET)
#define DOLBY_CORE1_STATUS2 (0xfd + CORE1_OFFSET)
#define DOLBY_CORE1_STATUS3 (0xfe + CORE1_OFFSET)
#define DOLBY_CORE1_DMA_PORT (0xff + CORE1_OFFSET)
#define DOLBY_CORE3_REG_START 0x3600
#define DOLBY_CORE3_CLKGATE_CTRL 0x36f0
#define DOLBY_CORE3_SWAP_CTRL0 0x36f1
#define DOLBY_CORE3_SWAP_CTRL1 0x36f2
#define DOLBY_CORE3_SWAP_CTRL2 0x36f3
#define DOLBY_CORE3_SWAP_CTRL3 0x36f4
#define DOLBY_CORE3_SWAP_CTRL4 0x36f5
#define DOLBY_CORE3_SWAP_CTRL5 0x36f6
#define DOLBY_CORE3_SWAP_CTRL6 0x36f7
#define DOLBY_CORE3_DIAG_CTRL 0x36f8
#define DOLBY_CORE1_1_REG_START (0x00 + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_CLKGATE_CTRL (0xf2 + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_SWAP_CTRL0 (0xf3 + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_SWAP_CTRL1 (0xf4 + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_SWAP_CTRL2 (0xf5 + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_SWAP_CTRL3 (0xf6 + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_SWAP_CTRL4 (0xf7 + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_SWAP_CTRL5 (0xf8 + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_DMA_CTRL (0xf9 + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_DMA_STATUS (0xfa + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_STATUS0 (0xfb + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_STATUS1 (0xfc + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_STATUS2 (0xfd + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_STATUS3 (0xfe + CORE1_1_OFFSET)
#define DOLBY_CORE1_1_DMA_PORT (0xff + CORE1_1_OFFSET)
#define DOLBY_CORE3_CRC_CTRL 0x36fb
#define DOLBY_CORE3_INPUT_CSC_CRC 0x36fc
#define DOLBY_CORE3_OUTPUT_CSC_CRC 0x36fd
#define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d
#define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d
#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd
#define DOLBY_CORE2A_REG_START (0x00 + CORE2A_OFFSET)
#define DOLBY_CORE2A_CTRL (0x01 + CORE2A_OFFSET)
#define DOLBY_CORE2A_CLKGATE_CTRL (0x32 + CORE2A_OFFSET)
#define DOLBY_CORE2A_SWAP_CTRL0 (0x33 + CORE2A_OFFSET)
#define DOLBY_CORE2A_SWAP_CTRL1 (0x34 + CORE2A_OFFSET)
#define DOLBY_CORE2A_SWAP_CTRL2 (0x35 + CORE2A_OFFSET)
#define DOLBY_CORE2A_SWAP_CTRL3 (0x36 + CORE2A_OFFSET)
#define DOLBY_CORE2A_SWAP_CTRL4 (0x37 + CORE2A_OFFSET)
#define DOLBY_CORE2A_SWAP_CTRL5 (0x38 + CORE2A_OFFSET)
#define DOLBY_CORE2A_DMA_CTRL (0x39 + CORE2A_OFFSET)
#define DOLBY_CORE2A_DMA_STATUS (0x3a + CORE2A_OFFSET)
#define DOLBY_CORE2A_STATUS0 (0x3b + CORE2A_OFFSET)
#define DOLBY_CORE2A_STATUS1 (0x3c + CORE2A_OFFSET)
#define DOLBY_CORE2A_STATUS2 (0x3d + CORE2A_OFFSET)
#define DOLBY_CORE2A_STATUS3 (0x3e + CORE2A_OFFSET)
#define DOLBY_CORE2A_DMA_PORT (0x3f + CORE2A_OFFSET)
#define DOLBY_CORE3_REG_START (0x00 + CORE3_OFFSET)
#define DOLBY_CORE3_CLKGATE_CTRL (0xf0 + CORE3_OFFSET)
#define DOLBY_CORE3_SWAP_CTRL0 (0xf1 + CORE3_OFFSET)
#define DOLBY_CORE3_SWAP_CTRL1 (0xf2 + CORE3_OFFSET)
#define DOLBY_CORE3_SWAP_CTRL2 (0xf3 + CORE3_OFFSET)
#define DOLBY_CORE3_SWAP_CTRL3 (0xf4 + CORE3_OFFSET)
#define DOLBY_CORE3_SWAP_CTRL4 (0xf5 + CORE3_OFFSET)
#define DOLBY_CORE3_SWAP_CTRL5 (0xf6 + CORE3_OFFSET)
#define DOLBY_CORE3_SWAP_CTRL6 (0xf7 + CORE3_OFFSET)
#define DOLBY_CORE3_DIAG_CTRL (0xf8 + CORE3_OFFSET)
#define DOLBY_CORE3_CRC_CTRL (0xfb + CORE3_OFFSET)
#define DOLBY_CORE3_INPUT_CSC_CRC (0xfc + CORE3_OFFSET)
#define DOLBY_CORE3_OUTPUT_CSC_CRC (0xfd + CORE3_OFFSET)
#define DOLBY_TV_REG_START (0x00 + CORETV_OFFSET)
#define DOLBY_TV_CLKGATE_CTRL (0xf1 + CORETV_OFFSET)
#define DOLBY_TV_SWAP_CTRL0 (0xf2 + CORETV_OFFSET)
#define DOLBY_TV_SWAP_CTRL1 (0xf3 + CORETV_OFFSET)
#define DOLBY_TV_SWAP_CTRL2 (0xf4 + CORETV_OFFSET)
#define DOLBY_TV_SWAP_CTRL3 (0xf5 + CORETV_OFFSET)
#define DOLBY_TV_SWAP_CTRL4 (0xf6 + CORETV_OFFSET)
#define DOLBY_TV_SWAP_CTRL5 (0xf7 + CORETV_OFFSET)
#define DOLBY_TV_SWAP_CTRL6 (0xf8 + CORETV_OFFSET)
#define DOLBY_TV_SWAP_CTRL7 (0xf9 + CORETV_OFFSET)
#define DOLBY_TV_AXI2DMA_CTRL0 (0xfa + CORETV_OFFSET)
#define DOLBY_TV_AXI2DMA_CTRL1 (0xfb + CORETV_OFFSET)
#define DOLBY_TV_AXI2DMA_CTRL2 (0xfc + CORETV_OFFSET)
#define DOLBY_TV_AXI2DMA_CTRL3 (0xfd + CORETV_OFFSET)
#define DOLBY_TV_STATUS0 (0xfe + CORETV_OFFSET)
#define DOLBY_TV_STATUS1 (0xff + CORETV_OFFSET)
#define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d
#define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d
#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd
#define DOLBY_PATH_CTRL 0x1a0c
#define VIU_MISC_CTRL1 0x1a07
#define VPP_DOLBY_CTRL 0x1d93
#define VIU_SW_RESET 0x1a01
#define VPU_HDMI_FMT_CTRL 0x2743
#define DOLBY_TV_REG_START 0x3300
#define DOLBY_TV_CLKGATE_CTRL 0x33f1
#define DOLBY_TV_SWAP_CTRL0 0x33f2
#define DOLBY_TV_SWAP_CTRL1 0x33f3
#define DOLBY_TV_SWAP_CTRL2 0x33f4
#define DOLBY_TV_SWAP_CTRL3 0x33f5
#define DOLBY_TV_SWAP_CTRL4 0x33f6
#define DOLBY_TV_SWAP_CTRL5 0x33f7
#define DOLBY_TV_SWAP_CTRL6 0x33f8
#define DOLBY_TV_SWAP_CTRL7 0x33f9
#define DOLBY_TV_AXI2DMA_CTRL0 0x33fa
#define DOLBY_TV_AXI2DMA_CTRL1 0x33fb
#define DOLBY_TV_AXI2DMA_CTRL2 0x33fc
#define DOLBY_TV_AXI2DMA_CTRL3 0x33fd
#define DOLBY_TV_STATUS0 0x33fe
#define DOLBY_TV_STATUS1 0x33ff
#if 0
/* core 1 display manager 24 registers */
struct dm_register_ipcore_1_s {

5
include/linux/amlogic/media/amdolbyvision/dolby_vision.h
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@@ -48,9 +48,14 @@ extern int dolby_vision_update_setting(void);
extern bool is_dolby_vision_stb_mode(void);
extern bool is_meson_g12(void);
extern bool is_meson_gxm(void);
extern bool is_meson_box(void);
extern bool is_meson_txlx(void);
extern bool is_meson_txlx_tvmode(void);
extern bool is_meson_txlx_stbmode(void);
extern bool is_meson_tm2(void);
extern bool is_meson_tm2_tvmode(void);
extern bool is_meson_tm2_stbmode(void);
extern bool is_meson_tvmode(void);
extern void tv_dolby_vision_crc_clear(int flag);
extern char *tv_dolby_vision_get_crc(u32 *len);
extern void tv_dolby_vision_insert_crc(bool print);