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arm64: dts: rockchip: rk3588: fix audio mclk configuration for spdif to dp

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The clock topology:
MCLK_SPDIF2     ----->  spdif_tx2 mclk
HCLK_SPDIF2_DP0 ----->  spdif_tx2 hclk

MCLK_SPDIF2_DP0   --|\
                    | |----- dp0 audio mclk
MCLK_I2S4_8CH_TX  --|/

MCLK_SPDIF5     ----->  spdif_tx5 mclk
HCLK_SPDIF5_DP1 ----->  spdif_tx5 hclk

MCLK_SPDIF5_DP1   --|\
                    | |----- dp1 audio mclk
MCLK_I2S8_8CH_TX  --|/

Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: I00fc9a217227079ed51984615d63116e0be56443
This commit is contained in:
Shunhua Lan
2022-01-25 19:07:37 +08:00
committed by Tao Huang
parent dab9ef540d
commit dcdf88d54d
2 changed files with 12 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm64/boot/dts/rockchip/rk3588.dtsi
View File

@@ -187,7 +187,7 @@
dmas = <&dmac1 22>;
dma-names = "tx";
clock-names = "mclk", "hclk";
clocks = <&cru MCLK_SPDIF5_DP1>, <&cru HCLK_SPDIF5_DP1>;
clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>;
assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
power-domains = <&power RK3588_PD_VO0>;
@@ -320,13 +320,16 @@
compatible = "rockchip,rk3588-dp";
reg = <0x0 0xfde60000 0x0 0x4000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>, <&hclk_vo0>;
clock-names = "apb", "aux", "hclk";
clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>,
<&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_SPDIF5_DP1>,
<&hclk_vo0>;
clock-names = "apb", "aux", "i2s", "spdif", "hclk";
assigned-clocks = <&cru CLK_AUX16M_1>;
assigned-clock-rates = <16000000>;
resets = <&cru SRST_DP1>;
phys = <&usbdp_phy1_dp>;
power-domains = <&power RK3588_PD_VO0>;
#sound-dai-cells = <1>;
status = "disabled";
ports {

9
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@@ -3134,7 +3134,7 @@
dmas = <&dmac1 6>;
dma-names = "tx";
clock-names = "mclk", "hclk";
clocks = <&cru MCLK_SPDIF2_DP0>, <&cru HCLK_SPDIF2_DP0>;
clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>;
assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
power-domains = <&power RK3588_PD_VO0>;
@@ -3312,13 +3312,16 @@
compatible = "rockchip,rk3588-dp";
reg = <0x0 0xfde50000 0x0 0x4000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, <&hclk_vo0>;
clock-names = "apb", "aux", "hclk";
clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>,
<&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_SPDIF2_DP0>,
<&hclk_vo0>;
clock-names = "apb", "aux", "i2s", "spdif", "hclk";
assigned-clocks = <&cru CLK_AUX16M_0>;
assigned-clock-rates = <16000000>;
resets = <&cru SRST_DP0>;
phys = <&usbdp_phy0_dp>;
power-domains = <&power RK3588_PD_VO0>;
#sound-dai-cells = <1>;
status = "disabled";
ports {