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irqchip: add a new gpio IRQ driver to support double-edge detection [1/1]
PD#SWPL-922 Problem: the existing gpio IRQ driver(porting from the upstream) does not double-edge detection Solution: add a new gpio IRQ driver to support the double-edge detection, the new driver is with different software structure but compatible with functions of the existing driver Verify: test pass on s400 Change-Id: Id69dd0b4459eef20a6755947c7d95a24d7b17fa9 Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
This commit is contained in:
Xingyu Chen
@@ -14281,6 +14281,7 @@ F: sound/soc/amlogic/meson/dmic.h
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AMLOGIC GPIO IRQ
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M: Xingyu Chen <xingyu.chen@amlogic.com>
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F: drivers/amlogic/irqchip/*
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F: drivers/amlogic/irqchip/irq-meson-gpio-double-edge.c
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F: Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
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AMLOGIC PINCTRL DRIVER
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@@ -1 +1,2 @@
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obj-$(CONFIG_AMLOGIC_GPIO_IRQ) += irq-meson-gpio.o
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obj-$(CONFIG_AMLOGIC_GPIO_IRQ) += irq-meson-gpio.o \
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irq-meson-gpio-double-edge.o
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489
drivers/amlogic/irqchip/irq-meson-gpio-double-edge.c
Normal file
489
drivers/amlogic/irqchip/irq-meson-gpio-double-edge.c
Normal file
@@ -0,0 +1,489 @@
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/*
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* drivers/amlogic/irqchip/irq-meson-gpio-double-edge.c
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*
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* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/of_address.h>
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#include <linux/of.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqchip.h>
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#ifndef NO_IRQ
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#define NO_IRQ ((unsigned int)(-1))
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#endif
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#define DRIVER_NAME "GPIO-INTC"
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#define MESON_GPIO_BIND_PARENT_IRQ_NUM_MAX 2
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#define REG_EDGE_POL 0x0
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#define REG_PIN_03_SEL 0x4
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#define REG_PIN_47_SEL 0x8
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#define REG_FILTER_SEL 0xc
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#define REG_EDGE_POL_MASK(x) (BIT(x) | BIT(16 + x))
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#define REG_EDGE_SET(x) BIT(x)
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#define REG_POL_SET(x) BIT(16+x)
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/**
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* struct gpio_parent_irq - describe the parent irq for gpio
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*
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* @virq: virtual interrupt number of parent irq
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* @owner: hwirq for gpio
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*/
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struct gpio_parent_irq {
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int virq;
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unsigned int owner;
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};
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struct meson_gpio_irq_data {
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unsigned int nr_hwirq;
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};
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struct meson_gpio_intc {
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unsigned char nr_gicirq;
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spinlock_t lock;
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void __iomem *base;
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struct irq_domain *irqdomain;
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struct gpio_parent_irq *parent_irqs;
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const struct meson_gpio_irq_data *data;
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};
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static const struct meson_gpio_irq_data meson8_data = {
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.nr_hwirq = 134,
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};
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static const struct meson_gpio_irq_data meson8b_data = {
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.nr_hwirq = 119,
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};
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static const struct meson_gpio_irq_data gxbb_data = {
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.nr_hwirq = 133,
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};
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static const struct meson_gpio_irq_data gxl_data = {
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.nr_hwirq = 110,
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};
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static const struct meson_gpio_irq_data axg_data = {
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.nr_hwirq = 100,
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};
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static const struct meson_gpio_irq_data txlx_data = {
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.nr_hwirq = 119,
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};
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static const struct meson_gpio_irq_data g12a_data = {
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.nr_hwirq = 100,
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};
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static const struct meson_gpio_irq_data txl_data = {
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.nr_hwirq = 93,
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};
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static const struct meson_gpio_irq_data tl1_data = {
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.nr_hwirq = 102,
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};
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static const struct of_device_id meson_gpio_irq_matches[] = {
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{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_data },
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{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_data },
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{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_data },
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{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_data },
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{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_data },
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{ .compatible = "amlogic,meson-txlx-gpio-intc", .data = &txlx_data },
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{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &g12a_data },
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{ .compatible = "amlogic,meson-txl-gpio-intc", .data = &txl_data },
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{ .compatible = "amlogic,meson-tl1-gpio-intc", .data = &tl1_data },
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{ }
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};
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static void meson_reg_update_bits(void __iomem *base, unsigned int regoff,
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unsigned int mask, const unsigned int val)
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{
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unsigned int orig;
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orig = readl_relaxed(base + regoff);
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orig = orig & (~mask);
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orig |= val;
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writel_relaxed(orig, base + regoff);
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}
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static int meson_gpio_irq_find_by_parent_virq(struct irq_data *irqd)
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{
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struct irq_desc *desc = irq_data_to_desc(irqd);
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struct meson_gpio_intc *intc = irq_desc_get_handler_data(desc);
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int idx;
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for (idx = 0; idx < intc->nr_gicirq; idx++)
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if (intc->parent_irqs[idx].virq == irqd->irq)
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return idx;
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return -EINVAL;
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}
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static int meson_gpio_parent_irq_find_by_hwirq(struct irq_data *irqd,
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int *data, int dlen)
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{
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struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd);
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int nr = 0;
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int idx;
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for (idx = 0; idx < intc->nr_gicirq; idx++) {
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if (nr >= dlen)
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break;
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if (intc->parent_irqs[idx].owner == irqd->hwirq)
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data[nr++] = idx;
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}
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return nr;
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}
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/*
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* NOP functions
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*/
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static void noop(struct irq_data *irqd) { }
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static void meson_gpio_parent_irq_unmask(int virq)
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{
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struct irq_data *parent_data;
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parent_data = irq_get_irq_data(virq);
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/*enable the interrupt line of gpio in GIC controller*/
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parent_data->chip->irq_unmask(parent_data);
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}
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static void meson_gpio_parent_irq_mask(int virq)
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{
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struct irq_data *parent_data;
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parent_data = irq_get_irq_data(virq);
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/*disable the interrupt line of gpio in GIC controller*/
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parent_data->chip->irq_mask(parent_data);
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}
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static int meson_gpio_parent_irq_request(struct irq_data *irqd,
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unsigned int type)
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{
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struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd);
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struct irq_data *parent_data;
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unsigned int idx;
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for (idx = 0; idx < intc->nr_gicirq; idx++) {
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if (intc->parent_irqs[idx].owner == NO_IRQ) {
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intc->parent_irqs[idx].owner = irqd->hwirq;
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break;
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}
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}
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if (idx == intc->nr_gicirq) {
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pr_warn("%s: no more gpio irqs available\n", DRIVER_NAME);
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return -EINVAL;
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}
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parent_data = irq_get_irq_data(intc->parent_irqs[idx].virq);
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/*set trigger type of gpio in GIC controller*/
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if (type & IRQ_TYPE_EDGE_BOTH)
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parent_data->chip->irq_set_type(parent_data,
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IRQ_TYPE_EDGE_RISING);
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else
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parent_data->chip->irq_set_type(parent_data,
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IRQ_TYPE_LEVEL_HIGH);
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pr_info("%s: gpio virq[%d] connect to GIC hwirq[%ld]\n", DRIVER_NAME,
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irqd->irq, parent_data->hwirq);
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return idx;
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}
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static int meson_gpio_parent_irq_release(struct irq_data *irqd)
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{
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struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd);
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int idx[MESON_GPIO_BIND_PARENT_IRQ_NUM_MAX];
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int nr;
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nr = meson_gpio_parent_irq_find_by_hwirq(irqd, idx, ARRAY_SIZE(idx));
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while (nr--)
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intc->parent_irqs[idx[nr]].owner = NO_IRQ;
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return 0;
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}
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static void meson_gpio_irq_regs_config(struct irq_data *irqd,
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int idx, unsigned int type)
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{
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struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd);
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unsigned int val = 0;
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unsigned long flags;
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int regoff;
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int shift;
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spin_lock_irqsave(&intc->lock, flags);
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if (type & IRQ_TYPE_EDGE_BOTH)
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val |= REG_EDGE_SET(idx);
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if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))
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val |= REG_POL_SET(idx);
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meson_reg_update_bits(intc->base, REG_EDGE_POL,
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REG_EDGE_POL_MASK(idx), val);
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/*set the filter registers*/
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shift = idx << 2;
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meson_reg_update_bits(intc->base, REG_FILTER_SEL,
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0x7 << shift, 0x7 << shift);
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/*set pin select register*/
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shift = (idx << 3) % 32;
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regoff = (idx < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
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meson_reg_update_bits(intc->base, regoff,
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0xff << shift, irqd->hwirq << shift);
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spin_unlock_irqrestore(&intc->lock, flags);
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}
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static void meson_gpio_irq_enable(struct irq_data *irqd)
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{
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struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd);
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int idx[MESON_GPIO_BIND_PARENT_IRQ_NUM_MAX];
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unsigned long flags;
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int nr;
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spin_lock_irqsave(&intc->lock, flags);
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nr = meson_gpio_parent_irq_find_by_hwirq(irqd,
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idx, ARRAY_SIZE(idx));
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while (nr--)
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meson_gpio_parent_irq_unmask(intc->parent_irqs[idx[nr]].virq);
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spin_unlock_irqrestore(&intc->lock, flags);
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}
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static void meson_gpio_irq_disable(struct irq_data *irqd)
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{
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struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd);
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int idx[MESON_GPIO_BIND_PARENT_IRQ_NUM_MAX];
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unsigned long flags;
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int nr;
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spin_lock_irqsave(&intc->lock, flags);
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nr = meson_gpio_parent_irq_find_by_hwirq(irqd, idx, ARRAY_SIZE(idx));
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while (nr--)
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meson_gpio_parent_irq_mask(intc->parent_irqs[idx[nr]].virq);
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spin_unlock_irqrestore(&intc->lock, flags);
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}
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/**
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*free gpio irq when free_irq() is called, and another pin can use it again.
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*/
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static void meson_gpio_irq_shutdown(struct irq_data *irqd)
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{
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struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd);
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unsigned long flags;
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spin_lock_irqsave(&intc->lock, flags);
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meson_gpio_parent_irq_release(irqd);
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spin_unlock_irqrestore(&intc->lock, flags);
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meson_gpio_irq_disable(irqd);
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}
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static int meson_gpio_irq_type(struct irq_data *irqd, unsigned int type)
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{
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struct meson_gpio_intc *intc = irq_data_get_irq_chip_data(irqd);
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unsigned long flags;
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int nr_parent_irq;
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int idx;
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type = type & IRQ_TYPE_SENSE_MASK;
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nr_parent_irq = (type == IRQ_TYPE_EDGE_BOTH) ? 2 : 1;
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while (nr_parent_irq--) {
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if (type == IRQ_TYPE_EDGE_BOTH)
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type = IRQ_TYPE_EDGE_FALLING;
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spin_lock_irqsave(&intc->lock, flags);
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idx = meson_gpio_parent_irq_request(irqd, type);
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spin_unlock_irqrestore(&intc->lock, flags);
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if (idx < 0) {
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meson_gpio_irq_shutdown(irqd);
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return -EINVAL;
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}
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meson_gpio_irq_regs_config(irqd, idx, type);
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if (nr_parent_irq > 0)
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type = IRQ_TYPE_EDGE_RISING;
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}
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return 0;
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}
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static struct irq_chip meson_gpio_intc_chip = {
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.name = "meson-gpio-irqchip",
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.irq_enable = meson_gpio_irq_enable,
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.irq_disable = meson_gpio_irq_disable,
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.irq_set_type = meson_gpio_irq_type,
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.irq_mask = noop,
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.irq_unmask = noop,
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.irq_shutdown = meson_gpio_irq_shutdown,
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};
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static int meson_gpio_intc_domain_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hwirq)
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{
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struct meson_gpio_intc *intc = d->host_data;
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irq_set_chip_and_handler(virq,
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&meson_gpio_intc_chip, handle_simple_irq);
|
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irq_set_chip_data(virq, intc);
|
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|
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return 0;
|
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}
|
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|
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static const struct irq_domain_ops meson_gpio_intc_domain_ops = {
|
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.map = meson_gpio_intc_domain_map,
|
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.xlate = irq_domain_xlate_twocell,
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};
|
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|
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static void meson_gpio_irq_handler(struct irq_desc *desc)
|
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{
|
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struct irq_chip *chip = irq_desc_get_chip(desc);
|
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struct irq_data *parent_data = irq_desc_get_irq_data(desc);
|
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struct meson_gpio_intc *intc = irq_desc_get_handler_data(desc);
|
||||
int idx;
|
||||
|
||||
chained_irq_enter(chip, desc);
|
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|
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idx = meson_gpio_irq_find_by_parent_virq(parent_data);
|
||||
if (idx >= 0 && intc->parent_irqs[idx].owner != NO_IRQ)
|
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generic_handle_irq(irq_find_mapping(intc->irqdomain,
|
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intc->parent_irqs[idx].owner));
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static int __init meson_gpio_intc_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
{
|
||||
struct meson_gpio_intc *intc;
|
||||
const struct of_device_id *match;
|
||||
struct irq_fwspec fwspec;
|
||||
int parent_hwirq;
|
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int parent_virq;
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int ret;
|
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int idx;
|
||||
|
||||
intc = kzalloc(sizeof(struct meson_gpio_intc), GFP_KERNEL);
|
||||
if (!intc)
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return -ENOMEM;
|
||||
|
||||
match = of_match_node(meson_gpio_irq_matches, node);
|
||||
if (!match) {
|
||||
ret = -ENODEV;
|
||||
pr_err("%s: fail to match device node\n", DRIVER_NAME);
|
||||
goto alloc_err1;
|
||||
}
|
||||
intc->data = match->data;
|
||||
|
||||
ret = of_property_count_elems_of_size(node,
|
||||
"amlogic,channel-interrupts", sizeof(u32));
|
||||
if (ret <= 0) {
|
||||
pr_err("%s: fail to get the number of elements\n", DRIVER_NAME);
|
||||
ret = -EINVAL;
|
||||
goto alloc_err1;
|
||||
}
|
||||
intc->nr_gicirq = ret;
|
||||
|
||||
intc->parent_irqs = kcalloc(intc->nr_gicirq,
|
||||
sizeof(struct gpio_parent_irq), GFP_KERNEL);
|
||||
if (!intc->parent_irqs) {
|
||||
ret = -ENOMEM;
|
||||
goto alloc_err1;
|
||||
}
|
||||
|
||||
spin_lock_init(&intc->lock);
|
||||
|
||||
intc->base = of_iomap(node, 0);
|
||||
if (IS_ERR_OR_NULL(intc->base)) {
|
||||
ret = -ENOMEM;
|
||||
goto alloc_err2;
|
||||
}
|
||||
|
||||
intc->irqdomain = irq_domain_add_linear(node, intc->data->nr_hwirq,
|
||||
&meson_gpio_intc_domain_ops, intc);
|
||||
if (IS_ERR_OR_NULL(intc->irqdomain)) {
|
||||
ret = -ENOMEM;
|
||||
goto iomap_err;
|
||||
}
|
||||
|
||||
for (idx = 0; idx < intc->nr_gicirq; idx++) {
|
||||
ret = of_property_read_u32_index(node,
|
||||
"amlogic,channel-interrupts", idx,
|
||||
&parent_hwirq);
|
||||
if (ret < 0) {
|
||||
pr_err("%s: fail to read property value\n",
|
||||
DRIVER_NAME);
|
||||
goto iomap_err;
|
||||
}
|
||||
|
||||
fwspec.fwnode = of_node_to_fwnode(parent);
|
||||
fwspec.param_count = 3;
|
||||
fwspec.param[0] = 0;
|
||||
fwspec.param[1] = parent_hwirq;
|
||||
fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
|
||||
|
||||
parent_virq = irq_create_fwspec_mapping(&fwspec);
|
||||
|
||||
intc->parent_irqs[idx].virq = parent_virq;
|
||||
intc->parent_irqs[idx].owner = NO_IRQ;
|
||||
irq_set_handler_data(parent_virq, intc);
|
||||
irq_set_chained_handler(parent_virq, meson_gpio_irq_handler);
|
||||
|
||||
/*disable the interrupt line of gpio in GIC controller*/
|
||||
meson_gpio_parent_irq_mask(parent_virq);
|
||||
}
|
||||
|
||||
pr_info("%s: support to detect double-edge trigger signal\n",
|
||||
DRIVER_NAME);
|
||||
|
||||
return 0;
|
||||
|
||||
iomap_err:
|
||||
iounmap(intc->base);
|
||||
|
||||
alloc_err2:
|
||||
kfree(intc->parent_irqs);
|
||||
|
||||
alloc_err1:
|
||||
kfree(intc);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* if you want to use the Meson GPIO IRQ which support the
|
||||
* double-edge detection, please set the compatible property
|
||||
* to "amlogic,meson-gpio-intc-ext" in dts
|
||||
*/
|
||||
IRQCHIP_DECLARE(meson_gpio, "amlogic,meson-gpio-intc-ext",
|
||||
meson_gpio_intc_init);
|
||||
@@ -654,6 +654,9 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
|
||||
|
||||
pc->of_irq = of_find_compatible_node(NULL,
|
||||
NULL, "amlogic,meson-gpio-intc");
|
||||
if (!pc->of_irq)
|
||||
pc->of_irq = of_find_compatible_node(NULL,
|
||||
NULL, "amlogic,meson-gpio-intc-ext");
|
||||
|
||||
pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
|
||||
if (IS_ERR(pc->reg_mux)) {
|
||||
|
||||
Reference in New Issue
Block a user