hdmirx: update phy setting [1/1]

PD#SWPL-3512

Problem:
HDMIRX no sinal in some mainboard.

Solution:
1.fix phy pll lock bit unstable issue(foce lock);
2.modify phy bandwidth definition;
3.optimize tmds_valid judgement;

Verify:
TL1

Change-Id: Idea20a46c465b20687654f071b259ebf8a7fed4a
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>

drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h

@@ -46,7 +46,7 @@
  *
  *
  */
-#define RX_VER2 "ver.2018/12/18"
+#define RX_VER2 "ver.2018/12/20"
 
 /*print type*/
 #define	LOG_EN		0x01
@@ -373,6 +373,7 @@ struct phy_sts {
 	uint32_t pll_rate;
 	uint32_t clk_rate;
 	uint32_t phy_bw;
+	uint32_t pll_bw;
 	uint32_t cablesel;
 	ulong timestap;
 	uint32_t err_sum;

drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c

@@ -2220,7 +2220,9 @@ bool rx_clkrate_monitor(void)
 	clk_rate = rx_get_scdc_clkrate_sts();
 	if (is_clk_stable()) {
 		rx.phy.cable_clk = rx_measure_clock(MEASURE_CLK_CABLE);
+		rx.phy.tmds_clk = rx_measure_clock(MEASURE_CLK_TMDS);
 		rx.phy.phy_bw = aml_cable_clk_band(rx.phy.cable_clk, clk_rate);
+		rx.phy.pll_bw = aml_phy_pll_band(rx.phy.cable_clk, clk_rate);
 	}
 
 	if (clk_rate != rx.phy.clk_rate) {
@@ -3133,13 +3135,13 @@ void dump_edid_reg(void)
 
 int rx_debug_wr_reg(const char *buf, char *tmpbuf, int i)
 {
-	long adr = 0;
-	long value = 0;
+	uint32_t adr = 0;
+	uint32_t value = 0;
 
-	if (kstrtol(tmpbuf + 3, 16, &adr) < 0)
+	if (kstrtou32(tmpbuf + 3, 16, &adr) < 0)
 		return -EINVAL;
 	rx_pr("adr = %#x\n", adr);
-	if (kstrtol(buf + i + 1, 16, &value) < 0)
+	if (kstrtou32(buf + i + 1, 16, &value) < 0)
 		return -EINVAL;
 	rx_pr("value = %#x\n", value);
 	if (tmpbuf[1] == 'h') {
@@ -3174,11 +3176,11 @@ int rx_debug_wr_reg(const char *buf, char *tmpbuf, int i)
 
 int rx_debug_rd_reg(const char *buf, char *tmpbuf)
 {
-	long adr = 0;
-	long value = 0;
+	uint32_t adr = 0;
+	uint32_t value = 0;
 
 	if (tmpbuf[1] == 'h') {
-		if (kstrtol(tmpbuf + 3, 16, &adr) < 0)
+		if (kstrtou32(tmpbuf + 3, 16, &adr) < 0)
 			return -EINVAL;
 		if (tmpbuf[2] == 't') {
 			value = hdmirx_rd_top(adr);
@@ -3265,6 +3267,34 @@ uint32_t aml_cable_clk_band(uint32_t cableclk,
 	return bw;
 }
 
+uint32_t aml_phy_pll_band(uint32_t cableclk,
+	uint32_t clkrate)
+{
+	uint32_t bw;
+	uint32_t cab_clk = cableclk;
+
+	if (clkrate)
+		cab_clk = cableclk << 2;
+
+	/* 1:10 */
+	if (cab_clk < (35*MHz))
+		bw = pll_frq_band_0;
+	else if (cab_clk < (77*MHz))
+		bw = pll_frq_band_1;
+	else if (cab_clk < (155*MHz))
+		bw = pll_frq_band_2;
+	else if (cab_clk < (300*MHz))
+		bw = pll_frq_band_3;
+	else if (cab_clk < (600*MHz))
+		bw = pll_frq_band_4;
+	else {
+		bw = pll_frq_band_2;
+		rx_pr("phy err: bw clk=%d\n", cableclk);
+	}
+
+	return bw;
+}
+
 void aml_phy_switch_port(void)
 {
 	uint32_t data32;
@@ -3513,7 +3543,7 @@ void aml_phy_pll_setting(void)
 	uint32_t M, N;
 	uint32_t od, od_div;
 	uint32_t od2, od2_div;
-	uint32_t bw = rx.phy.phy_bw;
+	uint32_t bw = rx.phy.pll_bw;
 	uint32_t vco_clk;
 	uint32_t apll_out;
 	uint32_t aud_pll_out;
@@ -3560,7 +3590,8 @@ void aml_phy_pll_setting(void)
 	udelay(2);
 	wr_reg_hhi(HHI_HDMIRX_APLL_CNTL0, data|0x14000000);
 	udelay(60);
-	wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x00003018);
+	/* bit'5: force lock bit'2: improve ldo voltage */
+	wr_reg_hhi(HHI_HDMIRX_APLL_CNTL2, 0x0000303c);
 	/* common block release reset */
 	data = rd_reg_hhi(HHI_HDMIRX_PHY_MISC_CNTL0);
 	data &= ~(0x7 << 7);
@@ -3628,24 +3659,47 @@ unsigned int aml_phy_pll_lock(void)
 		return false;
 }
 
+bool is_tmds_clk_stable(void)
+{
+	bool ret = true;
+	uint32_t cableclk;
+
+	if (rx.phy.clk_rate)
+		cableclk = rx.phy.cable_clk * 4;
+	else
+		cableclk = rx.phy.cable_clk;
+
+	if (abs(cableclk - rx.phy.tmds_clk) > 5 * MHz) {
+		if (log_level & VIDEO_LOG)
+			rx_pr("cableclk=%d,tmdsclk=%d\n",
+				cableclk/MHz, rx.phy.tmds_clk/MHz);
+		ret = false;
+	} else
+		ret = true;
+
+	return ret;
+}
+
 unsigned int aml_phy_tmds_valid(void)
 {
 	unsigned int tmds_valid;
+	unsigned int tmdsclk_valid;
 	unsigned int sqofclk;
-	unsigned int pll_lock;
+	/* unsigned int pll_lock; */
 	unsigned int tmds_align;
 
 	tmds_valid = hdmirx_rd_dwc(DWC_HDMI_PLL_LCK_STS) & 0x01;
 	sqofclk = hdmirx_rd_top(TOP_MISC_STAT0) & 0x1;
-	pll_lock = rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0) & 0x80000000;
+	/*pll_lock = rd_reg_hhi(HHI_HDMIRX_APLL_CNTL0) & 0x80000000;*/
+	tmdsclk_valid = is_tmds_clk_stable();
 	tmds_align = hdmirx_rd_top(TOP_TMDS_ALIGN_STAT) & 0x3f000000;
-	if (tmds_valid && sqofclk && pll_lock &&
+	if (tmds_valid && sqofclk && tmdsclk_valid &&
 		(tmds_align == 0x3f000000))
 		return true;
 	else {
 		if (log_level & VIDEO_LOG) {
-			rx_pr("tmds:%x,sqo:%x,lock:%x,align:%x\n",
-				tmds_valid, sqofclk, pll_lock, tmds_align);
+			rx_pr("tmds:%x,sqo:%x,tmdsclk_valid:%x,align:%x\n",
+				tmds_valid, sqofclk, tmdsclk_valid, tmds_align);
 			rx_pr("cable clk0:%d\n",
 				rx_measure_clock(MEASURE_CLK_CABLE));
 			rx_pr("cable clk1:%d\n",

drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.h

@@ -1269,6 +1269,8 @@ extern void aml_phy_init(void);
 extern void aml_phy_pw_onoff(uint32_t onoff);
 extern uint32_t aml_cable_clk_band(uint32_t cableclk,
 	uint32_t clkrate);
+extern uint32_t aml_phy_pll_band(uint32_t cableclk,
+	uint32_t clkrate);
 extern void aml_phy_switch_port(void);
 extern void aml_phy_bw_switch(void);
 extern unsigned int aml_phy_pll_lock(void);

drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_pktinfo.c

@@ -336,7 +336,7 @@ void rx_debug_pktinfo(char input[][20])
 {
 	uint32_t sts = 0;
 	uint32_t enable = 0;
-	long res = 0;
+	uint32_t res = 0;
 
 	if (strncmp(input[1], "debugfifo", 9) == 0) {
 		/*open all pkt interrupt source for debug*/
@@ -367,7 +367,7 @@ void rx_debug_pktinfo(char input[][20])
 		rx_pkt_status();
 	else if (strncmp(input[1], "dump", 7) == 0) {
 		/*check input type*/
-		if (kstrtol(input[2], 16, &res) < 0)
+		if (kstrtou32(input[2], 16, &res) < 0)
 			rx_pr("error input:fmt is 0xValue\n");
 		rx_pkt_dump(res);
 	} else if (strncmp(input[1], "irqdisable", 10) == 0) {
@@ -440,7 +440,7 @@ void rx_debug_pktinfo(char input[][20])
 		/*hdmirx_irq_open()*/
 	} else if (strncmp(input[1], "fifopkten", 9) == 0) {
 		/*check input*/
-		if (kstrtol(input[2], 16, &res) < 0)
+		if (kstrtou32(input[2], 16, &res) < 0)
 			return;
 		rx_pr("pkt ctl disable:0x%x", res);
 		/*check pkt enable ctl bit*/
@@ -455,7 +455,7 @@ void rx_debug_pktinfo(char input[][20])
 		hdmirx_wr_dwc(DWC_PDEC_CTRL, enable);
 	} else if (strncmp(input[1], "fifopktdis", 10) == 0) {
 		/*check input*/
-		if (kstrtol(input[2], 16, &res) < 0)
+		if (kstrtou32(input[2], 16, &res) < 0)
 			return;
 		rx_pr("pkt ctl disable:0x%x", res);
 		/*check pkt enable ctl bit*/
@@ -470,14 +470,14 @@ void rx_debug_pktinfo(char input[][20])
 		hdmirx_wr_dwc(DWC_PDEC_CTRL, enable);
 	} else if (strncmp(input[1], "contentchk", 10) == 0) {
 		/*check input*/
-		if (kstrtol(input[2], 16, &res) < 0) {
+		if (kstrtou32(input[2], 16, &res) < 0) {
 			rx_pr("error input:fmt is 0xXX\n");
 			return;
 		}
 		rx_pkt_content_chk_en(res);
 	} else if (strncmp(input[1], "pdfifopri", 9) == 0) {
 		/*check input*/
-		if (kstrtol(input[2], 16, &res) < 0) {
+		if (kstrtou32(input[2], 16, &res) < 0) {
 			rx_pr("error input:fmt is 0xXX\n");
 			return;
 		}

drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c

@@ -1313,6 +1313,7 @@ void fsm_restart(void)
 	rx.phy.cable_clk = 0;
 	rx.phy.pll_rate = 0;
 	rx.phy.phy_bw = 0;
+	rx.phy.pll_bw = 0;
 	rx_pr("force_fsm_init\n");
 }
 
@@ -1451,7 +1452,7 @@ int rx_set_global_variable(const char *buf, int size)
 {
 	char tmpbuf[60];
 	int i = 0;
-	long value = 0;
+	uint32_t value = 0;
 	int ret = 0;
 	int index = 1;
 
@@ -1472,9 +1473,9 @@ int rx_set_global_variable(const char *buf, int size)
 			break;
 	}
 	if ((buf[i] == '0') && ((buf[i + 1] == 'x') || (buf[i + 1] == 'X')))
-		ret = kstrtol(buf + i + 2, 16, &value);
+		ret = kstrtou32(buf + i + 2, 16, &value);
 	else
-		ret = kstrtol(buf + i, 10, &value);
+		ret = kstrtou32(buf + i, 10, &value);
 	/*rx_pr("tmpbuf: %s value: %#x index:%#x\n", tmpbuf, value, index);*/
 
 	if (ret != 0)
@@ -2649,7 +2650,7 @@ int hdmirx_debug(const char *buf, int size)
 {
 	char tmpbuf[128];
 	int i = 0;
-	long value = 0;
+	uint32_t value = 0;
 
 	char input[5][20];
 	char *const delim = " ";
@@ -2720,7 +2721,7 @@ int hdmirx_debug(const char *buf, int size)
 		else
 			dump_state(RX_DUMP_ALL);
 	} else if (strncmp(tmpbuf, "pause", 5) == 0) {
-		if (kstrtol(tmpbuf + 5, 10, &value) < 0)
+		if (kstrtou32(tmpbuf + 5, 10, &value) < 0)
 			return -EINVAL;
 		rx_pr("%s\n", value ? "pause" : "enable");
 		sm_pause = value;
@@ -2790,7 +2791,7 @@ int hdmirx_debug(const char *buf, int size)
 	} else if (strncmp(input[0], "tmdscapture", 11) == 0) {
 		rx_tmds_data_capture();
 	} else if (strncmp(input[0], "tmdscnt", 7) == 0) {
-		if (kstrtol(input[1], 16, &value) < 0)
+		if (kstrtou32(input[1], 16, &value) < 0)
 			rx_pr("error input Value\n");
 		rx_pr("set pkt cnt:0x%x\n", value);
 		rx.empbuff.tmdspktcnt = value;