shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: rockchip: rk3308: Set max parent rate of dclk_vop_frac for rk3308b

Browse Source 
The max parent rate of dclk_vop_frac is improved to 800MHz on rk3308b.

Change-Id: Ie36120ac7048fc4c983547539a6bce34d737529d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2018-11-14 15:51:16 +08:00
committed by Tao Huang
parent 31307243fa
commit ddbda6c6df
1 changed files with 20 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/clk/rockchip/clk-rk3308.c
View File

@@ -460,10 +460,6 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS,
RK3308_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(9), 0,
RK3308_CLKGATE_CON(1), 7, GFLAGS,
&rk3308_dclk_vop_fracmux, 0),
GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
RK3308_CLKGATE_CON(1), 8, GFLAGS),
@@ -911,6 +907,20 @@ static struct rockchip_clk_branch rk3308_clk_branches[] __initdata = {
GATE(PCLK_OWIRE, "pclk_owire", "pclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(7), 15, GFLAGS),
};
static struct rockchip_clk_branch rk3308_dclk_vop_frac[] __initdata = {
COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(9), 0,
RK3308_CLKGATE_CON(1), 7, GFLAGS,
&rk3308_dclk_vop_fracmux, RK3308_VOP_FRAC_MAX_PRATE),
};
static struct rockchip_clk_branch rk3308b_dclk_vop_frac[] __initdata = {
COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
RK3308_CLKSEL_CON(9), 0,
RK3308_CLKGATE_CON(1), 7, GFLAGS,
&rk3308_dclk_vop_fracmux, RK3308B_VOP_FRAC_MAX_PRATE),
};
static void __init rk3308_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
@@ -936,6 +946,12 @@ static void __init rk3308_clk_init(struct device_node *np)
RK3308_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rk3308_clk_branches,
ARRAY_SIZE(rk3308_clk_branches));
if (soc_is_rk3308b())
rockchip_clk_register_branches(ctx, rk3308b_dclk_vop_frac,
ARRAY_SIZE(rk3308b_dclk_vop_frac));
else
rockchip_clk_register_branches(ctx, rk3308_dclk_vop_frac,
ARRAY_SIZE(rk3308_dclk_vop_frac));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
3, clks[PLL_APLL], clks[PLL_VPLL0],