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Merge tag 'ux500-dev-for-armsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/soc

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Some two collected patches simplifying some Ux500
stuff.

* tag 'ux500-dev-for-armsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
  ARM: ux500: remove duplicated include from cpu-db8500.c
  ARM: ux500: simplify secondary boot

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2017-01-16 22:26:42 -08:00
parent 53f56d6e23 f3c0559634
commit ddcb0a762b
2 changed files with 19 additions and 27 deletions
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1
arch/arm/mach-ux500/cpu-db8500.c
View File

@@ -12,7 +12,6 @@
#include <linux/init.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>

45
arch/arm/mach-ux500/platsmp.c
View File

@@ -31,10 +31,14 @@
#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
static void wakeup_secondary(void)
static void __iomem *backupram;
static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
static void __iomem *backupram;
static void __iomem *scu_base;
unsigned int ncores;
int i;
np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
if (!np) {
@@ -48,29 +52,6 @@ static void wakeup_secondary(void)
return;
}
/*
* write the address of secondary startup into the backup ram register
* at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
* backup ram register at offset 0x1FF0, which is what boot rom code
* is waiting for. This will wake up the secondary core from WFE.
*/
writel(virt_to_phys(secondary_startup),
backupram + UX500_CPU1_JUMPADDR_OFFSET);
writel(0xA1FEED01,
backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
/* make sure write buffer is drained */
mb();
iounmap(backupram);
}
static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
static void __iomem *scu_base;
unsigned int ncores;
int i;
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
if (!np) {
pr_err("No SCU base address\n");
@@ -92,7 +73,19 @@ static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
wakeup_secondary();
/*
* write the address of secondary startup into the backup ram register
* at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
* backup ram register at offset 0x1FF0, which is what boot rom code
* is waiting for. This will wake up the secondary core from WFE.
*/
writel(virt_to_phys(secondary_startup),
backupram + UX500_CPU1_JUMPADDR_OFFSET);
writel(0xA1FEED01,
backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
/* make sure write buffer is drained */
mb();
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
return 0;
}