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camera:support rk3188,use new iomux.

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This commit is contained in:
zyc
2013-01-16 16:12:54 +08:00
parent 4344d7abcb
commit de07f0593f
4 changed files with 91 additions and 633 deletions
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66
arch/arm/mach-rk30/board-rk3066b-sdk-camera.c Normal file → Executable file
View File

@@ -151,41 +151,61 @@
#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
static void rk_cif_power(int on)
static void rk_cif_power(struct rk29camera_gpio_res *res,int on)
{
struct regulator *ldo_18,*ldo_28;
struct regulator *ldo_18,*ldo_28;
int camera_power = res->gpio_power;
int camera_ioflag = res->gpio_flag;
int camera_io_init = res->gpio_init;
ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
printk("get cif ldo failed!\n");
printk("get cif ldo failed!\n");
return;
}
if(on == 0){
regulator_disable(ldo_28);
regulator_put(ldo_28);
regulator_disable(ldo_18);
regulator_put(ldo_18);
mdelay(500);
}
else{
regulator_set_voltage(ldo_28, 2800000, 2800000);
regulator_enable(ldo_28);
// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
regulator_put(ldo_28);
}
if(on == 0){
while(regulator_is_enabled(ldo_28)>0)
regulator_disable(ldo_28);
regulator_put(ldo_28);
while(regulator_is_enabled(ldo_18)>0)
regulator_disable(ldo_18);
regulator_put(ldo_18);
mdelay(10);
if (camera_power != INVALID_GPIO) {
if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
// dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
}
}
}
else{
regulator_set_voltage(ldo_28, 2800000, 2800000);
regulator_enable(ldo_28);
// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
regulator_put(ldo_28);
regulator_set_voltage(ldo_18, 1800000, 1800000);
// regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo_18);
// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
regulator_put(ldo_18);
}
regulator_set_voltage(ldo_18, 1800000, 1800000);
// regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo_18);
// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
regulator_put(ldo_18);
if (camera_power != INVALID_GPIO) {
if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
//dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
mdelay(10);
}
}
}
}
#if CONFIG_SENSOR_POWER_IOCTL_USR
static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
{
//#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
rk_cif_power(on);
rk_cif_power(res,on);
return 0;
}
#endif

80
arch/arm/mach-rk30/board-rk3168-tb-camera.c Normal file → Executable file
View File

@@ -151,59 +151,65 @@
#define CONFIG_SENSOR_POWERDOWN_IOCTL_USR 0
#define CONFIG_SENSOR_FLASH_IOCTL_USR 0
static void rk_cif_power(int on)
static void rk_cif_power(struct rk29camera_gpio_res *res,int on)
{
struct regulator *ldo_18,*ldo_28;
struct regulator *ldo_18,*ldo_28;
int camera_power = res->gpio_power;
int camera_ioflag = res->gpio_flag;
int camera_io_init = res->gpio_init;
ldo_28 = regulator_get(NULL, "ldo7"); // vcc28_cif
ldo_18 = regulator_get(NULL, "ldo1"); // vcc18_cif
if (ldo_28 == NULL || IS_ERR(ldo_28) || ldo_18 == NULL || IS_ERR(ldo_18)){
printk("get cif ldo failed!\n");
printk("get cif ldo failed!\n");
return;
}
if(on == 0){
regulator_disable(ldo_28);
regulator_put(ldo_28);
regulator_disable(ldo_18);
regulator_put(ldo_18);
mdelay(500);
}
else{
regulator_set_voltage(ldo_28, 2800000, 2800000);
regulator_enable(ldo_28);
// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
regulator_put(ldo_28);
}
if(on == 0){
while(regulator_is_enabled(ldo_28)>0)
regulator_disable(ldo_28);
regulator_put(ldo_28);
while(regulator_is_enabled(ldo_18)>0)
regulator_disable(ldo_18);
regulator_put(ldo_18);
mdelay(10);
if (camera_power != INVALID_GPIO) {
if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
gpio_set_value(camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
// dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, (((~camera_ioflag)&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
}
}
}
else{
regulator_set_voltage(ldo_28, 2800000, 2800000);
regulator_enable(ldo_28);
// printk("%s set ldo7 vcc28_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_28));
regulator_put(ldo_28);
regulator_set_voltage(ldo_18, 1800000, 1800000);
// regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo_18);
// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
regulator_put(ldo_18);
}
regulator_set_voltage(ldo_18, 1800000, 1800000);
// regulator_set_suspend_voltage(ldo, 1800000);
regulator_enable(ldo_18);
// printk("%s set ldo1 vcc18_cif=%dmV end\n", __func__, regulator_get_voltage(ldo_18));
regulator_put(ldo_18);
if (camera_power != INVALID_GPIO) {
if (camera_io_init & RK29_CAM_POWERACTIVE_MASK) {
gpio_set_value(camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
//dprintk("%s..%s..PowerPin=%d ..PinLevel = %x \n",__FUNCTION__,res->dev_name, camera_power, ((camera_ioflag&RK29_CAM_POWERACTIVE_MASK)>>RK29_CAM_POWERACTIVE_BITPOS));
mdelay(10);
}
}
}
}
#if CONFIG_SENSOR_POWER_IOCTL_USR
static int sensor_power_usr_cb (struct rk29camera_gpio_res *res,int on)
{
//#error "CONFIG_SENSOR_POWER_IOCTL_USR is 1, sensor_power_usr_cb function must be writed!!";
rk_cif_power(on);
rk_cif_power(res,on);
return 0;
}
#endif
#if CONFIG_SENSOR_RESET_IOCTL_USR
static int sensor_reset_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_RESET_IOCTL_USR is 1, sensor_reset_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_POWERDOWN_IOCTL_USR
static int sensor_powerdown_usr_cb (struct rk29camera_gpio_res *res,int on)
{
#error "CONFIG_SENSOR_POWERDOWN_IOCTL_USR is 1, sensor_powerdown_usr_cb function must be writed!!";
}
#endif
#if CONFIG_SENSOR_FLASH_IOCTL_USR
static int sensor_flash_usr_cb (struct rk29camera_gpio_res *res,int on)
{

571
drivers/media/video/rk30_camera.c
View File

@@ -14,575 +14,8 @@
static int rk_sensor_iomux(int pin)
{
#if defined(CONFIG_ARCH_RK3066B)
switch (pin)
{
case RK30_PIN0_PA0:
case RK30_PIN0_PA1:
case RK30_PIN0_PA2:
case RK30_PIN0_PA3:
case RK30_PIN0_PA4:
case RK30_PIN0_PA5:
case RK30_PIN0_PA6:
case RK30_PIN0_PA7:
case RK30_PIN0_PB0:
case RK30_PIN0_PB1:
case RK30_PIN0_PB2:
case RK30_PIN0_PB3:
case RK30_PIN0_PB4:
case RK30_PIN0_PB5:
case RK30_PIN0_PB6:
case RK30_PIN0_PB7:
case RK30_PIN0_PC0:
{
rk30_mux_api_set(GPIO0C0_FLASHDATA8_NAME,0);
break;
}
case RK30_PIN0_PC1:
{
rk30_mux_api_set(GPIO0C1_FLASHDATA9_NAME,0);
break;
}
case RK30_PIN0_PC2:
{
rk30_mux_api_set(GPIO0C2_FLASHDATA10_NAME,0);
break;
}
case RK30_PIN0_PC3:
{
rk30_mux_api_set(GPIO0C3_FLASHDATA11_NAME,0);
break;
}
case RK30_PIN0_PC4:
{
rk30_mux_api_set(GPIO0C4_FLASHDATA12_NAME,0);
break;
}
case RK30_PIN0_PC5:
{
rk30_mux_api_set(GPIO0C5_FLASHDATA13_NAME,0);
break;
}
case RK30_PIN0_PC6:
{
rk30_mux_api_set(GPIO0C6_FLASHDATA14_NAME,0);
break;
}
case RK30_PIN0_PC7:
{
rk30_mux_api_set(GPIO0C7_FLASHDATA15_NAME,0);
break;
}
case RK30_PIN0_PD0:
{
rk30_mux_api_set(GPIO0D0_FLASHDQS_EMMCCLKOUT_NAME,0);
break;
}
case RK30_PIN0_PD1:
{
rk30_mux_api_set(GPIO0D1_FLASHCSN1_NAME,0);
break;
}
case RK30_PIN0_PD2:
{
rk30_mux_api_set(GPIO0D2_FLASHCSN2_EMMCCMD_NAME,0);
break;
}
case RK30_PIN0_PD3:
{
rk30_mux_api_set(GPIO0D3_FLASHCSN3_EMMCRSTNOUT_NAME,0);
break;
}
case RK30_PIN0_PD4:
{
rk30_mux_api_set(GPIO0D4_SPI1RXD_NAME,0);
break;
}
case RK30_PIN0_PD5:
{
rk30_mux_api_set(GPIO0D5_SPI1TXD_NAME,0);
break;
}
case RK30_PIN0_PD6:
{
rk30_mux_api_set(GPIO0D6_SPI1CLK_NAME,0);
break;
}
case RK30_PIN0_PD7:
{
rk30_mux_api_set(GPIO0D7_SPI1CSN0_NAME,0);
break;
}
case RK30_PIN1_PA0:
{
rk30_mux_api_set(GPIO1A0_UART0SIN_NAME,0);
break;
}
case RK30_PIN1_PA1:
{
rk30_mux_api_set(GPIO1A1_UART0SOUT_NAME,0);
break;
}
case RK30_PIN1_PA2:
{
rk30_mux_api_set(GPIO1A2_UART0CTSN_NAME,0);
break;
}
case RK30_PIN1_PA3:
{
rk30_mux_api_set(GPIO1A3_UART0RTSN_NAME,0);
break;
}
case RK30_PIN1_PA4:
{
rk30_mux_api_set(GPIO1A4_UART1SIN_SPI0RXD_NAME,0);
break;
}
case RK30_PIN1_PA5:
{
rk30_mux_api_set(GPIO1A5_UART1SOUT_SPI0TXD_NAME,0);
break;
}
case RK30_PIN1_PA6:
{
rk30_mux_api_set(GPIO1A6_UART1CTSN_SPI0CLK_NAME,0);
break;
}
case RK30_PIN1_PA7:
{
rk30_mux_api_set(GPIO1A7_UART1RTSN_SPI0CSN0_NAME,0);
break;
}
case RK30_PIN1_PB0:
{
rk30_mux_api_set(GPIO1B0_UART2SIN_JTAGTDI_NAME,0);
break;
}
case RK30_PIN1_PB1:
{
rk30_mux_api_set(GPIO1B1_UART2SOUT_JTAGTDO_NAME,0);
break;
}
case RK30_PIN1_PB2:
{
rk30_mux_api_set(GPIO1B2_UART3SIN_GPSMAG_NAME,0);
break;
}
case RK30_PIN1_PB3:
{
rk30_mux_api_set(GPIO1B3_UART3SOUT_GPSSIG_NAME,0);
break;
}
case RK30_PIN1_PB4:
{
rk30_mux_api_set(GPIO1B4_UART3CTSN_GPSRFCLK_NAME,0);
break;
}
case RK30_PIN1_PB5:
{
rk30_mux_api_set(GPIO1B5_UART3RTSN_NAME,0);
break;
}
case RK30_PIN1_PB6:
{
rk30_mux_api_set(GPIO1B6_SPDIFTX_SPI1CSN1_NAME,0);
break;
}
case RK30_PIN1_PB7:
{
rk30_mux_api_set(GPIO1B7_SPI0CSN1_NAME,0);
break;
}
case RK30_PIN1_PC0:
{
rk30_mux_api_set(GPIO1C0_I2SCLK_NAME,0);
break;
}
case RK30_PIN1_PC1:
{
rk30_mux_api_set(GPIO1C1_I2SSCLK_NAME,0);
break;
}
case RK30_PIN1_PC2:
{
rk30_mux_api_set(GPIO1C2_I2SLRCLKRX_NAME,0);
break;
}
case RK30_PIN1_PC3:
{
rk30_mux_api_set(GPIO1C3_I2SLRCLKTX_NAME,0);
break;
}
case RK30_PIN1_PC4:
{
rk30_mux_api_set(GPIO1C4_I2SSDI_NAME,0);
break;
}
case RK30_PIN1_PC5:
case RK30_PIN1_PC6:
case RK30_PIN1_PC7:
break;
case RK30_PIN1_PD0:
{
rk30_mux_api_set(GPIO1D0_I2C0SDA_NAME,0);
break;
}
case RK30_PIN1_PD1:
{
rk30_mux_api_set(GPIO1D1_I2C0SCL_NAME,0);
break;
}
case RK30_PIN1_PD2:
{
rk30_mux_api_set(GPIO1D2_I2C1SDA_NAME,0);
break;
}
case RK30_PIN1_PD3:
{
rk30_mux_api_set(GPIO1D3_I2C1SCL_NAME,0);
break;
}
case RK30_PIN1_PD4:
{
rk30_mux_api_set(GPIO1D4_I2C2SDA_NAME,0);
break;
}
case RK30_PIN1_PD5:
{
rk30_mux_api_set(GPIO1D5_I2C2SCL_NAME,0);
break;
}
case RK30_PIN1_PD6:
{
rk30_mux_api_set(GPIO1D6_I2C4SDA_NAME,0);
break;
}
case RK30_PIN1_PD7:
{
rk30_mux_api_set(GPIO1D7_I2C4SCL_NAME,0);
break;
}
case RK30_PIN2_PA0:
{
rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME,0);
break;
}
case RK30_PIN2_PA1:
{
rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME,0);
break;
}
case RK30_PIN2_PA2:
{
rk30_mux_api_set(GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME,0);
break;
}
case RK30_PIN2_PA3:
{
rk30_mux_api_set(GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME,0);
break;
}
case RK30_PIN2_PA4:
{
rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME,0);
break;
}
case RK30_PIN2_PA5:
{
rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME,0);
break;
}
case RK30_PIN2_PA6:
{
rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME,0);
break;
}
case RK30_PIN2_PA7:
{
rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME,0);
break;
}
case RK30_PIN2_PB0:
{
rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME,0);
break;
}
case RK30_PIN2_PB1:
{
rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME,0);
break;
}
case RK30_PIN2_PB2:
{
rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME,0);
break;
}
case RK30_PIN2_PB3:
{
rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME,0);
break;
}
case RK30_PIN2_PB4:
{
rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME,0);
break;
}
case RK30_PIN2_PB5:
{
rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME,0);
break;
}
case RK30_PIN2_PB6:
{
rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME,0);
break;
}
case RK30_PIN2_PB7:
{
rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME,0);
break;
}
case RK30_PIN2_PC0:
{
rk30_mux_api_set(GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME,0);
break;
}
case RK30_PIN2_PC1:
{
rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME,0);
break;
}
case RK30_PIN2_PC2:
{
rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCADDR2_NAME,0);
break;
}
case RK30_PIN2_PC3:
{
rk29_mux_api_set(GPIO2C3_LCDC1DATA19_SMCADDR3_NAME,0);
break;
}
case RK30_PIN2_PC4:
{
rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SMCADDR4_NAME,0);
break;
}
case RK30_PIN2_PC5:
{
rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SMCADDR5_NAME,0);
break;
}
case RK30_PIN2_PC6:
{
rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SMCADDR6_NAME,0);
break;
}
case RK30_PIN2_PC7:
{
rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SMCADDR7_NAME,0);
break;
}
case RK30_PIN2_PD0:
{
rk30_mux_api_set(GPIO2D0_LCDC1DCLK_SMCCSN0_NAME,0);
break;
}
case RK30_PIN2_PD1:
{
rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME,0);
break;
}
case RK30_PIN2_PD2:
{
rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_SMCOEN_NAME,0);
break;
}
case RK30_PIN2_PD3:
{
rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_SMCADVN_NAME,0);
break;
}
case RK30_PIN2_PD4:
{
rk30_mux_api_set(GPIO2D4_SMCBLSN0_NAME,0);
break;
}
case RK30_PIN2_PD5:
{
rk30_mux_api_set(GPIO2D5_SMCBLSN1_NAME,0);
break;
}
case RK30_PIN2_PD6:
{
rk30_mux_api_set(GPIO2D6_SMCCSN1_NAME,0);
break;
}
case RK30_PIN2_PD7:
{
rk30_mux_api_set(GPIO2D7_TESTCLOCKOUT_NAME,0);
break;
}
case RK30_PIN3_PA0:
{
rk30_mux_api_set(GPIO3A0_SDMMC0RSTNOUT_NAME,0);
break;
}
case RK30_PIN3_PA1:
{
rk30_mux_api_set(GPIO3A1_SDMMC0PWREN_NAME,0);
break;
}
case RK30_PIN3_PA2:
{
rk30_mux_api_set(GPIO3A2_SDMMC0CLKOUT_NAME,0);
break;
}
case RK30_PIN3_PA3:
{
rk30_mux_api_set(GPIO3A3_SDMMC0CMD_NAME,0);
break;
}
case RK30_PIN3_PA4:
{
rk30_mux_api_set(GPIO3A4_SDMMC0DATA0_NAME,0);
break;
}
case RK30_PIN3_PA5:
{
rk30_mux_api_set(GPIO3A5_SDMMC0DATA1_NAME,0);
break;
}
case RK30_PIN3_PA6:
{
rk30_mux_api_set(GPIO3A6_SDMMC0DATA2_NAME,0);
break;
}
case RK30_PIN3_PA7:
{
rk30_mux_api_set(GPIO3A7_SDMMC0DATA3_NAME,0);
break;
}
case RK30_PIN3_PB0:
{
rk30_mux_api_set(GPIO3B0_SDMMC0DETECTN_NAME,0);
break;
}
case RK30_PIN3_PB1:
{
rk30_mux_api_set(GPIO3B1_SDMMC0WRITEPRT_NAME,0);
break;
}
case RK30_PIN3_PB2:
break;
case RK30_PIN3_PB3:
{
rk30_mux_api_set(GPIO3B3_CIFCLKOUT_NAME,0);
break;
}
case RK30_PIN3_PB4:
{
rk30_mux_api_set(GPIO3B4_CIFDATA0_HSADCDATA8_NAME,0);
break;
}
case RK30_PIN3_PB5:
{
rk30_mux_api_set(GPIO3B5_CIFDATA1_HSADCDATA9_NAME,0);
break;
}
case RK30_PIN3_PB6:
{
rk30_mux_api_set(GPIO3B6_CIFDATA10_I2C3SDA_NAME,0);
break;
}
case RK30_PIN3_PB7:
{
rk30_mux_api_set(GPIO3B7_CIFDATA11_I2C3SCL_NAME,0);
break;
}
case RK30_PIN3_PC0:
{
rk30_mux_api_set(GPIO3C0_SDMMC1CMD_RMIITXEN_NAME,0);
break;
}
case RK30_PIN3_PC1:
{
rk30_mux_api_set(GPIO3C1_SDMMC1DATA0_RMIITXD1_NAME,0);
break;
}
case RK30_PIN3_PC2:
{
rk30_mux_api_set(GPIO3C2_SDMMC1DATA1_RMIITXD0_NAME,0);
break;
}
case RK30_PIN3_PC3:
{
rk30_mux_api_set(GPIO3C3_SDMMC1DATA2_RMIIRXD0_NAME,0);
break;
}
case RK30_PIN3_PC4:
{
rk30_mux_api_set(GPIO3C4_SDMMC1DATA3_RMIIRXD1_NAME,0);
break;
}
case RK30_PIN3_PC5:
{
rk30_mux_api_set(GPIO3C5_SDMMC1CLKOUT_RMIICLKOUT_RMIICLKIN_NAME,0);
break;
}
case RK30_PIN3_PC6:
{
rk30_mux_api_set(GPIO3C6_SDMMC1DETECTN_RMIIRXERR_NAME,0);
break;
}
case RK30_PIN3_PC7:
{
rk30_mux_api_set(GPIO3C7_SDMMC1WRITEPRT_RMIICRS_NAME,0);
break;
}
case RK30_PIN3_PD0:
{
rk30_mux_api_set(GPIO3D0_SDMMC1PWREN_MIIMD_NAME,0);
break;
}
case RK30_PIN3_PD1:
{
rk30_mux_api_set(GPIO3D1_SDMMC1BACKENDPWR_MIIMDCLK_NAME,0);
break;
}
case RK30_PIN3_PD2:
{
rk30_mux_api_set(GPIO3D2_SDMMC1INTN_NAME,0);
break;
}
case RK30_PIN3_PD3:
{
rk30_mux_api_set(GPIO3D3_PWM0_NAME,0);
break;
}
case RK30_PIN3_PD4:
{
rk30_mux_api_set(GPIO3D4_PWM1_JTAGTRSTN_NAME,0);
break;
}
case RK30_PIN3_PD5:
{
rk30_mux_api_set(GPIO3D5_PWM2_JTAGTCK_OTGDRVVBUS_NAME,0);
break;
}
case RK30_PIN3_PD6:
{
rk30_mux_api_set(GPIO3D6_PWM3_JTAGTMS_HOSTDRVVBUS_NAME,0);
break;
}
case RK30_PIN3_PD7:
break;
default:
{
printk("Pin=%d isn't RK GPIO, Please init it's iomux yourself!",pin);
break;
}
}
#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
iomux_set(pin);
#elif defined(CONFIG_ARCH_RK30)
switch (pin)
{

7
drivers/media/video/rk30_camera_oneframe.c
View File

@@ -9,7 +9,7 @@
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK30)
#if defined(CONFIG_ARCH_RK2928) || defined(CONFIG_ARCH_RK30) ||defined(CONFIG_ARCH_RK3188)
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
@@ -179,7 +179,7 @@ module_param(debug, int, S_IRUGO|S_IWUSR);
#define mask_cru_reg(addr, msk, val) write_cru_reg(addr,(val)|((~(msk))&read_cru_reg(addr)))
#endif
#if defined(CONFIG_ARCH_RK3066B)
#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
//GRF_IO_CON3 0x100
#define CIF_DRIVER_STRENGTH_2MA (0x00 << 12)
#define CIF_DRIVER_STRENGTH_4MA (0x01 << 12)
@@ -2883,11 +2883,10 @@ static struct soc_camera_host_ops rk_soc_camera_host_ops =
.set_ctrl = rk_camera_set_ctrl,
.controls = rk_camera_controls,
.num_controls = ARRAY_SIZE(rk_camera_controls)
};
static void rk_camera_cif_iomux(int cif_index)
{
#if defined(CONFIG_ARCH_RK3066B)
#if defined(CONFIG_ARCH_RK3066B) || defined(CONFIG_ARCH_RK3188)
switch(cif_index){
case 0:
iomux_set(CIF0_CLKOUT);