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media: rockchip: vpss: bring up fix some error

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1. online ch2 scl register misuse ch1 scl register
2. add pic size solve flip iommu error
3. init add sel online mode 2
4. add RKVPSS_CFG_GEN_UPD

Signed-off-by: Mingwei Yan <mingwei.yan@rock-chips.com>
Change-Id: Ic6270832a1d38b17d1d140ff02e21332e697cb19
This commit is contained in:
Mingwei Yan
2024-03-06 10:28:22 +08:00
committed by Tao Huang
parent d3d1ad5ae4
commit de11635f6d
4 changed files with 73 additions and 38 deletions
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3
drivers/media/platform/rockchip/vpss/hw.c
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@@ -522,6 +522,9 @@ void rkvpss_soft_reset(struct rkvpss_hw_dev *hw)
rkvpss_hw_write(hw, RKVPSS_VPSS_CTRL, RKVPSS_ACK_FRM_PRO_DIS);
rkvpss_hw_write(hw, RKVPSS_VPSS_IRQ_CFG, 0x3fff);
rkvpss_hw_write(hw, RKVPSS_MI_IMSC, 0xd0000000);
rkvpss_hw_set_bits(hw, RKVPSS_VPSS_ONLINE, RKVPSS_ONLINE_MODE_MASK,
RKVPSS_ISP2VPSS_ONLINE2);
rkvpss_hw_write(hw, RKVPSS_VPSS_UPDATE, RKVPSS_CFG_FORCE_UPD);
}
int rkvpss_get_zme_tap_coe_index(int ratio)

86
drivers/media/platform/rockchip/vpss/stream.c
View File

@@ -255,39 +255,39 @@ static struct stream_config scl2_config = {
.v_size_shd = RKVPSS_CROP1_2_V_SIZE_SHD,
},
.scale = {
.ctrl = RKVPSS_SCALE1_CTRL,
.update = RKVPSS_SCALE1_UPDATE,
.src_size = RKVPSS_SCALE1_SRC_SIZE,
.dst_size = RKVPSS_SCALE1_DST_SIZE,
.hy_fac = RKVPSS_SCALE1_HY_FAC,
.hc_fac = RKVPSS_SCALE1_HC_FAC,
.vy_fac = RKVPSS_SCALE1_VY_FAC,
.vc_fac = RKVPSS_SCALE1_VC_FAC,
.hy_offs = RKVPSS_SCALE1_HY_OFFS,
.hc_offs = RKVPSS_SCALE1_HC_OFFS,
.vy_offs = RKVPSS_SCALE1_VY_OFFS,
.vc_offs = RKVPSS_SCALE1_VC_OFFS,
.hy_size = RKVPSS_SCALE1_HY_SIZE,
.hc_size = RKVPSS_SCALE1_HC_SIZE,
.hy_offs_mi = RKVPSS_SCALE1_HY_OFFS_MI,
.hc_offs_mi = RKVPSS_SCALE1_HC_OFFS_MI,
.in_crop_offs = RKVPSS_SCALE1_IN_CROP_OFFSET,
.ctrl_shd = RKVPSS_SCALE1_CTRL_SHD,
.src_size_shd = RKVPSS_SCALE1_SRC_SIZE_SHD,
.dst_size_shd = RKVPSS_SCALE1_DST_SIZE_SHD,
.hy_fac_shd = RKVPSS_SCALE1_HY_FAC_SHD,
.hc_fac_shd = RKVPSS_SCALE1_HC_FAC_SHD,
.vy_fac_shd = RKVPSS_SCALE1_VY_FAC_SHD,
.vc_fac_shd = RKVPSS_SCALE1_VC_FAC_SHD,
.hy_offs_shd = RKVPSS_SCALE1_HY_OFFS_SHD,
.hc_offs_shd = RKVPSS_SCALE1_HC_OFFS_SHD,
.vy_offs_shd = RKVPSS_SCALE1_VY_OFFS_SHD,
.vc_offs_shd = RKVPSS_SCALE1_VC_OFFS_SHD,
.hy_size_shd = RKVPSS_SCALE1_HY_SIZE_SHD,
.hc_size_shd = RKVPSS_SCALE1_HC_SIZE_SHD,
.hy_offs_mi_shd = RKVPSS_SCALE1_HY_OFFS_MI_SHD,
.hc_offs_mi_shd = RKVPSS_SCALE1_HC_OFFS_MI_SHD,
.in_crop_offs_shd = RKVPSS_SCALE1_IN_CROP_OFFSET_SHD,
.ctrl = RKVPSS_SCALE2_CTRL,
.update = RKVPSS_SCALE2_UPDATE,
.src_size = RKVPSS_SCALE2_SRC_SIZE,
.dst_size = RKVPSS_SCALE2_DST_SIZE,
.hy_fac = RKVPSS_SCALE2_HY_FAC,
.hc_fac = RKVPSS_SCALE2_HC_FAC,
.vy_fac = RKVPSS_SCALE2_VY_FAC,
.vc_fac = RKVPSS_SCALE2_VC_FAC,
.hy_offs = RKVPSS_SCALE2_HY_OFFS,
.hc_offs = RKVPSS_SCALE2_HC_OFFS,
.vy_offs = RKVPSS_SCALE2_VY_OFFS,
.vc_offs = RKVPSS_SCALE2_VC_OFFS,
.hy_size = RKVPSS_SCALE2_HY_SIZE,
.hc_size = RKVPSS_SCALE2_HC_SIZE,
.hy_offs_mi = RKVPSS_SCALE2_HY_OFFS_MI,
.hc_offs_mi = RKVPSS_SCALE2_HC_OFFS_MI,
.in_crop_offs = RKVPSS_SCALE2_IN_CROP_OFFSET,
.ctrl_shd = RKVPSS_SCALE2_CTRL_SHD,
.src_size_shd = RKVPSS_SCALE2_SRC_SIZE_SHD,
.dst_size_shd = RKVPSS_SCALE2_DST_SIZE_SHD,
.hy_fac_shd = RKVPSS_SCALE2_HY_FAC_SHD,
.hc_fac_shd = RKVPSS_SCALE2_HC_FAC_SHD,
.vy_fac_shd = RKVPSS_SCALE2_VY_FAC_SHD,
.vc_fac_shd = RKVPSS_SCALE2_VC_FAC_SHD,
.hy_offs_shd = RKVPSS_SCALE2_HY_OFFS_SHD,
.hc_offs_shd = RKVPSS_SCALE2_HC_OFFS_SHD,
.vy_offs_shd = RKVPSS_SCALE2_VY_OFFS_SHD,
.vc_offs_shd = RKVPSS_SCALE2_VC_OFFS_SHD,
.hy_size_shd = RKVPSS_SCALE2_HY_SIZE_SHD,
.hc_size_shd = RKVPSS_SCALE2_HC_SIZE_SHD,
.hy_offs_mi_shd = RKVPSS_SCALE2_HY_OFFS_MI_SHD,
.hc_offs_mi_shd = RKVPSS_SCALE2_HC_OFFS_MI_SHD,
.in_crop_offs_shd = RKVPSS_SCALE2_IN_CROP_OFFSET_SHD,
},
.mi = {
.ctrl = RKVPSS_MI_CHN2_WR_CTRL,
@@ -461,7 +461,19 @@ static void scl_config_mi(struct rkvpss_stream *stream)
reg = stream->config->mi.stride;
rkvpss_write(dev, reg, val);
val *= out_fmt->height;
switch (fmt->fourcc) {
case V4L2_PIX_FMT_RGB565:
val = out_fmt->plane_fmt[0].bytesperline / 2;
break;
case V4L2_PIX_FMT_XBGR32:
val = out_fmt->plane_fmt[0].bytesperline / 4;
break;
default:
val = out_fmt->plane_fmt[0].bytesperline;
break;
}
val = val * out_fmt->height;
reg = stream->config->mi.y_pic_size;
rkvpss_write(dev, reg, val);
@@ -516,7 +528,8 @@ static void scl_enable_mi(struct rkvpss_stream *stream)
if (!dev->hw_dev->is_ofl_cmsc)
val |= RKVPSS_ISP2VPSS_ONLINE2_CMSC_EN;
rkvpss_set_bits(dev, RKVPSS_VPSS_ONLINE, mask, val);
rkvpss_write(dev, RKVPSS_VPSS_UPDATE, RKVPSS_ONLINE2_CHN_FORCE_UPD);
val = RKVPSS_ONLINE2_CHN_FORCE_UPD | RKVPSS_CFG_GEN_UPD;
rkvpss_write(dev, RKVPSS_VPSS_UPDATE, val);
}
static void scl_disable_mi(struct rkvpss_stream *stream)
@@ -542,7 +555,8 @@ static void scl_disable_mi(struct rkvpss_stream *stream)
}
rkvpss_clear_bits(dev, RKVPSS_VPSS_ONLINE, val);
rkvpss_write(dev, RKVPSS_VPSS_UPDATE, RKVPSS_ONLINE2_CHN_FORCE_UPD);
val = RKVPSS_ONLINE2_CHN_FORCE_UPD | RKVPSS_CFG_GEN_UPD;
rkvpss_write(dev, RKVPSS_VPSS_UPDATE, val);
}
static struct streams_ops scl_stream_ops = {

2
drivers/media/platform/rockchip/vpss/vpss.c
View File

@@ -162,7 +162,7 @@ static int rkvpss_sd_s_stream(struct v4l2_subdev *sd, int on)
rkvpss_cmsc_config(dev, true);
rkvpss_write(dev, RKVPSS_VPSS_ONLINE2_SIZE, h << 16 | w);
val = RKVPSS_CFG_FORCE_UPD | RKVPSS_CFG_GEN_UPD | RKVPSS_MIR_GEN_UPD;
val = RKVPSS_CFG_GEN_UPD | RKVPSS_MIR_GEN_UPD;
if (!dev->hw_dev->is_ofl_cmsc)
val |= RKVPSS_MIR_FORCE_UPD;
rkvpss_write(dev, RKVPSS_VPSS_UPDATE, val);

20
drivers/media/platform/rockchip/vpss/vpss_offline.c
View File

@@ -202,6 +202,7 @@ static int internal_buf_alloc(struct file *file, struct rkvpss_buf_info *info)
buf->mem = mem;
buf->alloc = true;
buf->dev_id = info->dev_id;
ops->prepare(buf->mem);
mutex_lock(&hw->dev_lock);
list_add_tail(&buf->list, &ofl->list);
mutex_unlock(&hw->dev_lock);
@@ -849,8 +850,24 @@ static int rkvpss_ofl_run(struct file *file, struct rkvpss_frame_cfg *cfg)
val = out_ch[i].ctrl;
rkvpss_hw_write(hw, reg + i * 0x100, val);
if (cfg->output[i].flip)
if (cfg->output[i].flip) {
flip_en |= RKVPSS_MI_CHN_V_FLIP(i);
switch (cfg->output[i].format) {
case V4L2_PIX_FMT_RGB565:
val = cfg->output[i].stride / 2;
break;
case V4L2_PIX_FMT_XBGR32:
val = cfg->output[i].stride / 4;
break;
default:
val = cfg->output[i].stride;
break;
}
val = val * h;
reg = RKVPSS_MI_CHN0_WR_Y_PIC_SIZE;
rkvpss_hw_write(hw, reg + i * 0x100, val);
}
mi_update |= (RKVPSS_MI_CHN0_FORCE_UPD << i);
}
rkvpss_hw_write(hw, RKVPSS_CROP0_CTRL, crop_en);
@@ -898,6 +915,7 @@ static int rkvpss_ofl_run(struct file *file, struct rkvpss_frame_cfg *cfg)
v4l2_info(&ofl->v4l2_dev,
"%s end, time:%lldus\n", __func__, us);
}
return ret;
free_buf:
for (i -= 1; i >= 0; i--) {