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Merge commit 'abd61db9d69e17126436259705e58fd6cc74a8f5'

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* commit 'abd61db9d69e17126436259705e58fd6cc74a8f5':
  edac: rockchip: add edac driver
  arm64: dts: rockchip: rk3562: Add arm_pmu label
  media: rockchip: vicap: fixes rv1126/rk3568 bt1120/bt656 buffer timestamp
  ARM: configs: rockchip: Update rv1106-tb-nofastae.config
  media: rockchip: isp: support unite mode for isp32
  PCI: rockchip: dw: Save and restore PCIE_CLIENT_INTR_MASK_LEGACY in PM
  ARM: dts: rockchip: rv1106-thunder-boot: set rkvenc clock to 410000000
  rpmsg: rockchip_test: add new device id for mcu
  arm64: dts: rockchip: rk3562-amp: change rpmsg shared memory address
  arm64: dts: rockchip: rk3562-amp: set mailbox txpoll to 1 ms
  ARM: dts: rockchip: add rv1106g-evb2-v12-nofastae-spi-nor
  ARM: dts: rockchip: add rv1106g-evb2-v12-nofastae-emmc
  ARM: dts: rockchip: Add rv1106 nofastae dtsi
  ARM: configs: rockchip: Add rv1106-tb-nofastae.config
  ASoC: codecs: Add tda7803 amplifier driver support
  clk: rockchip: rk3568: Add protect clocks
  drm/bridge: dw-hdmi-qp: Don't read edid again if edid is exist

Change-Id: I2db1ef5fd1c89b634bf2500e25f479568cf1c60e
This commit is contained in:
Tao Huang
2023-09-11 10:39:48 +08:00
parent 7bbab4044b abd61db9d6
commit dead21504e
47 changed files with 3511 additions and 1706 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/Makefile
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@@ -1148,6 +1148,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1106g-evb2-v10.dtb \
rv1106g-evb2-v10-dual-camera.dtb \
rv1106g-evb2-v11-emmc.dtb \
rv1106g-evb2-v12-nofastae-emmc.dtb \
rv1106g-evb2-v12-nofastae-spi-nor.dtb \
rv1106g-evb2-v12-wakeup.dtb \
rv1106g-smart-door-lock-rmsl-v10.dtb \
rv1106g-smart-door-lock-rmsl-v12.dtb \

31
arch/arm/boot/dts/rv1106-tb-nofastae-emmc.dtsi Normal file
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@@ -0,0 +1,31 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include "rv1106-tb-nofastae.dtsi"
/ {
reserved-memory {
mmc_ecsd: mmc@3f000 {
reg = <0x3f000 0x00001000>;
};
mmc_idmac: mmc@100000 {
reg = <0x00100000 0x00100000>;
};
};
thunder_boot_mmc: thunder-boot-mmc {
compatible = "rockchip,thunder-boot-mmc";
reg = <0xffa90000 0x4000>;
memory-region-src = <&ramdisk_c>;
memory-region-dst = <&ramdisk_r>;
memory-region-idmac = <&mmc_idmac>;
};
};
&emmc {
memory-region-ecsd = <&mmc_ecsd>;
post-power-on-delay-ms = <0>;
};

19
arch/arm/boot/dts/rv1106-tb-nofastae-spi-nor.dtsi Normal file
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@@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include "rv1106-tb-nofastae.dtsi"
/ {
thunder_boot_spi_nor: thunder-boot-spi-nor {
compatible = "rockchip,thunder-boot-sfc";
reg = <0xffac0000 0x4000>;
memory-region-src = <&ramdisk_c>;
memory-region-dst = <&ramdisk_r>;
};
};
&emmc {
status = "disabled";
};

35
arch/arm/boot/dts/rv1106-tb-nofastae.dtsi Normal file
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@@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/ {
memory: memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
ramdisk: ramdisk {
compatible = "rockchip,ramdisk";
memory-region = <&ramdisk_r>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
ramdisk_r: ramdisk_r {
reg = <0x800000 (10 * 0x00100000)>;
};
ramdisk_c: ramdisk_c {
reg = <0x1200000 (5 * 0x00100000)>;
};
};
};
&hw_decompress {
status = "okay";
memory-region = <&ramdisk_c>;
};

5
arch/arm/boot/dts/rv1106-thunder-boot.dtsi
View File

@@ -98,3 +98,8 @@
&rkisp_vir0 {
memory-region-thunderboot = <&rkisp_thunderboot>;
};
&rkvenc {
assigned-clocks = <&cru CLK_CORE_VEPU>;
assigned-clock-rates = <410000000>;
};

134
arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-emmc.dts Normal file
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@@ -0,0 +1,134 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106.dtsi"
#include "rv1106-evb-v10.dtsi"
#include "rv1106-evb-cam.dtsi"
#include "rv1106-tb-nofastae-emmc.dtsi"
/ {
model = "Rockchip RV1106G EVB2 V12 Board";
compatible = "rockchip,rv1106g-evb2-v12", "rockchip,rv1106";
chosen {
bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc3v3_sd: vcc3v3-sd {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
regulator-name = "vcc3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwren>;
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&fiq_debugger {
rockchip,baudrate = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
};
&pinctrl {
sdmmc {
/omit-if-no-ref/
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm10 {
status = "okay";
};
&pwm11 {
status = "okay";
};
&ramdisk_r {
reg = <0x800000 (20 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x1C00000 (10 * 0x00100000)>;
};
&sdio {
max-frequency = <50000000>;
bus-width = <1>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
rockchip,default-sample-phase = <90>;
no-sd;
no-mmc;
supports-sdio;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
status = "okay";
};
&sdmmc {
max-frequency = <200000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "normal", "idle";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
vmmc-supply = <&vcc3v3_sd>;
status = "okay";
};
&sfc {
assigned-clocks = <&cru SCLK_SFC>;
assigned-clock-rates = <125000000>;
status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <125000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&usbdrd_dwc3 {
dr_mode = "peripheral";
};

134
arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-spi-nor.dts Normal file
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@@ -0,0 +1,134 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106.dtsi"
#include "rv1106-evb-v10.dtsi"
#include "rv1106-evb-cam.dtsi"
#include "rv1106-tb-nofastae-spi-nor.dtsi"
/ {
model = "Rockchip RV1106G EVB2 V12 Board";
compatible = "rockchip,rv1106g-evb2-v12", "rockchip,rv1106";
chosen {
bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc3v3_sd: vcc3v3-sd {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
regulator-name = "vcc3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwren>;
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&fiq_debugger {
rockchip,baudrate = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
};
&pinctrl {
sdmmc {
/omit-if-no-ref/
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm10 {
status = "okay";
};
&pwm11 {
status = "okay";
};
&ramdisk_r {
reg = <0x800000 (10 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x1200000 (5 * 0x00100000)>;
};
&sdio {
max-frequency = <50000000>;
bus-width = <1>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
rockchip,default-sample-phase = <90>;
no-sd;
no-mmc;
supports-sdio;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
status = "okay";
};
&sdmmc {
max-frequency = <200000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "normal", "idle";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
vmmc-supply = <&vcc3v3_sd>;
status = "okay";
};
&sfc {
assigned-clocks = <&cru SCLK_SFC>;
assigned-clock-rates = <125000000>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <125000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&usbdrd_dwc3 {
dr_mode = "peripheral";
};

421
arch/arm/configs/rv1106-tb-nofastae.config Normal file
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@@ -0,0 +1,421 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_CRC16=m
CONFIG_CRYPTO=y
CONFIG_DAX=y
CONFIG_EROFS_FS=y
# CONFIG_ETHERNET is not set
CONFIG_EXT4_FS=m
CONFIG_FILE_LOCKING=y
CONFIG_JFFS2_FS=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_XZ is not set
CONFIG_LIBCRC32C=y
CONFIG_MAILBOX=y
# CONFIG_MDIO_DEVICE is not set
CONFIG_MMC=y
CONFIG_MSDOS_FS=m
CONFIG_MSDOS_PARTITION=y
CONFIG_MTD_BLOCK=m
CONFIG_NLS_CODEPAGE_936=m
# CONFIG_PHYLIB is not set
CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y
CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER=y
CONFIG_ROCKCHIP_DVBM=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_ROCKCHIP_MULTI_RGA=y
CONFIG_ROCKCHIP_RAMDISK=y
CONFIG_ROCKCHIP_RGA_PROC_FS=y
CONFIG_ROCKCHIP_THUNDER_BOOT=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=m
# CONFIG_SLUB_SYSFS is not set
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
CONFIG_SND_SOC_RV1106=m
CONFIG_SPI=y
CONFIG_VFAT_FS=m
CONFIG_VIDEO_ROCKCHIP_CIF=y
CONFIG_VIDEO_ROCKCHIP_ISP=y
CONFIG_VIDEO_SC230AI=y
CONFIG_VIDEO_SC301IOT=y
CONFIG_VIDEO_SC3338=y
# CONFIG_AD2S1200 is not set
# CONFIG_AD2S1210 is not set
# CONFIG_AD2S90 is not set
# CONFIG_AD5360 is not set
# CONFIG_AD5421 is not set
# CONFIG_AD5449 is not set
# CONFIG_AD5504 is not set
# CONFIG_AD5592R is not set
# CONFIG_AD5624R_SPI is not set
# CONFIG_AD5686_SPI is not set
# CONFIG_AD5755 is not set
# CONFIG_AD5758 is not set
# CONFIG_AD5761 is not set
# CONFIG_AD5764 is not set
# CONFIG_AD5770R is not set
# CONFIG_AD5791 is not set
# CONFIG_AD7124 is not set
# CONFIG_AD7192 is not set
# CONFIG_AD7266 is not set
# CONFIG_AD7280 is not set
# CONFIG_AD7292 is not set
# CONFIG_AD7298 is not set
# CONFIG_AD7303 is not set
# CONFIG_AD7476 is not set
# CONFIG_AD7606_IFACE_SPI is not set
# CONFIG_AD7766 is not set
# CONFIG_AD7768_1 is not set
# CONFIG_AD7780 is not set
# CONFIG_AD7791 is not set
# CONFIG_AD7793 is not set
# CONFIG_AD7816 is not set
# CONFIG_AD7887 is not set
# CONFIG_AD7923 is not set
# CONFIG_AD7949 is not set
# CONFIG_AD8366 is not set
# CONFIG_AD8801 is not set
# CONFIG_AD9523 is not set
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# CONFIG_ADF4350 is not set
# CONFIG_ADF4371 is not set
# CONFIG_ADIS16080 is not set
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16201 is not set
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16209 is not set
# CONFIG_ADIS16240 is not set
# CONFIG_ADIS16260 is not set
# CONFIG_ADIS16400 is not set
# CONFIG_ADIS16460 is not set
# CONFIG_ADIS16475 is not set
# CONFIG_ADIS16480 is not set
# CONFIG_ADXL345_SPI is not set
# CONFIG_ADXL372_SPI is not set
# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_ALTERA_MBOX is not set
# CONFIG_ARM_CRYPTO is not set
# CONFIG_ARM_MHU is not set
# CONFIG_ARM_SCMI_PROTOCOL is not set
# CONFIG_ARM_SCPI_PROTOCOL is not set
# CONFIG_AS3935 is not set
# CONFIG_BMA220 is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_ADIANTUM is not set
# CONFIG_CRYPTO_AEGIS128 is not set
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_AES_TI is not set
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_BLAKE2B is not set
# CONFIG_CRYPTO_BLAKE2S is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_CFB is not set
# CONFIG_CRYPTO_CHACHA20 is not set
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_CMAC is not set
# CONFIG_CRYPTO_CRC32 is not set
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRCT10DIF is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_CURVE25519 is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_DH is not set
# CONFIG_CRYPTO_DRBG_MENU is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_ECDH is not set
# CONFIG_CRYPTO_ECHAINIV is not set
# CONFIG_CRYPTO_ECRDSA is not set
# CONFIG_CRYPTO_ESSIV is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_GHASH is not set
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_HW is not set
# CONFIG_CRYPTO_JITTERENTROPY is not set
# CONFIG_CRYPTO_KEYWRAP is not set
# CONFIG_CRYPTO_LIB_CHACHA is not set
# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_LZ4 is not set
# CONFIG_CRYPTO_LZ4HC is not set
# CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_MANAGER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_POLY1305 is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_RSA is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SEQIV is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_SM2 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_STREEBOG is not set
# CONFIG_CRYPTO_TEST is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_USER is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_VMAC is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_XXHASH is not set
# CONFIG_CRYPTO_ZSTD is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EROFS_FS_DEBUG is not set
# CONFIG_EROFS_FS_XATTR is not set
# CONFIG_EROFS_FS_ZIP is not set
# CONFIG_EXT4_DEBUG is not set
# CONFIG_EXT4_FS_POSIX_ACL is not set
# CONFIG_EXT4_FS_SECURITY is not set
CONFIG_EXT4_USE_FOR_EXT2=y
# CONFIG_EZX_PCAP is not set
CONFIG_FAT_DEFAULT_CODEPAGE=936
CONFIG_FAT_DEFAULT_IOCHARSET="cp936"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_FAT_FS=m
CONFIG_FS_DAX=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=m
# CONFIG_FXOS8700_SPI is not set
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# CONFIG_HI8435 is not set
# CONFIG_IIO_SSP_SENSORHUB is not set
# CONFIG_INITCALL_ASYNC is not set
# CONFIG_INITRAMFS_FORCE is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INITRD_ASYNC=y
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_MPU6050_SPI is not set
CONFIG_JBD2=m
# CONFIG_JBD2_DEBUG is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_LZO is not set
# CONFIG_JFFS2_RTIME is not set
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_JFFS2_SUMMARY is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_LIB_MEMNEQ=y
# CONFIG_LTC1660 is not set
# CONFIG_LTC2496 is not set
# CONFIG_LTC2632 is not set
# CONFIG_LTC2983 is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_MANDATORY_FILE_LOCKING=y
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
# CONFIG_MAX1241 is not set
# CONFIG_MAX31856 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3911 is not set
# CONFIG_MCP41010 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4922 is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_RK806_SPI is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_BLOCK=m
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_MMC_CQHCI is not set
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_DW=m
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
CONFIG_MMC_DW_PLTFM=m
CONFIG_MMC_DW_ROCKCHIP=m
# CONFIG_MMC_HSQ is not set
# CONFIG_MMC_MTK is not set
CONFIG_MMC_QUEUE_DEPTH=1
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_TEST is not set
# CONFIG_MMC_USDHI6ROL0 is not set
# CONFIG_MOXTET is not set
# CONFIG_MPL115_SPI is not set
CONFIG_MTD_BLKDEVS=m
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_SPI_NAND is not set
CONFIG_MTD_SPI_NOR=m
CONFIG_MTD_SPI_NOR_MISC=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_PI433 is not set
# CONFIG_PL320_MBOX is not set
# CONFIG_PLATFORM_MHU is not set
# CONFIG_PWRSEQ_EMMC is not set
# CONFIG_PWRSEQ_SIMPLE is not set
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_GZIP is not set
# CONFIG_RD_LZ4 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_ZSTD is not set
CONFIG_REGMAP_SPI=y
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_ROCKCHIP_MBOX is not set
# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set
CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=m
CONFIG_ROCKCHIP_RGA_DEBUGGER=y
CONFIG_ROCKCHIP_THUNDER_BOOT_MMC=y
# CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE is not set
CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_MCP795 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RX6110 is not set
# CONFIG_SCA3000 is not set
# CONFIG_SDIO_UART is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_ES8328_SPI is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SPI is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AMD is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_DEBUG is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_LOOPBACK_TEST is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_MUX is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_ROCKCHIP is not set
CONFIG_SPI_ROCKCHIP_SFC=y
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_SLAVE is not set
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS124S08 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8344 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC7311 is not set
# CONFIG_TI_DAC7612 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_VIDEO_GS1662 is not set
# CONFIG_VIDEO_ROCKCHIP_PREISP is not set
# CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP is not set
# CONFIG_VIDEO_S5C73M3 is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

13
arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
View File

@@ -17,13 +17,13 @@
status = "okay";
};
rpmsg: rpmsg@a0000000 {
rpmsg: rpmsg@7c00000 {
compatible = "rockchip,rk3562-rpmsg";
mbox-names = "rpmsg-rx", "rpmsg-tx";
mboxes = <&mailbox 0 &mailbox 3>;
rockchip,vdev-nums = <1>;
rockchip,link-id = <0x04>;
reg = <0x0 0xa0000000 0x0 0x20000>;
reg = <0x0 0x7c00000 0x0 0x20000>;
memory-region = <&rpmsg_dma_reserved>;
status = "okay";
@@ -40,19 +40,20 @@
no-map;
};
rpmsg_reserved: rpmsg@a0000000 {
reg = <0x0 0xa0000000 0x0 0x400000>;
rpmsg_reserved: rpmsg@7c00000 {
reg = <0x0 0x07c00000 0x0 0x400000>;
no-map;
};
rpmsg_dma_reserved: rpmsg-dma@a0400000 {
rpmsg_dma_reserved: rpmsg-dma@8000000 {
compatible = "shared-dma-pool";
reg = <0x0 0xa0400000 0x0 0x100000>;
reg = <0x0 0x08000000 0x0 0x100000>;
no-map;
};
};
};
&mailbox {
rockchip,txpoll-period-ms = <1>;
status = "okay";
};

2
arch/arm64/boot/dts/rockchip/rk3562.dtsi
View File

@@ -352,7 +352,7 @@
};
};
arm-pmu {
arm_pmu: arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,

12
drivers/clk/rockchip/clk-rk3568.c
View File

@@ -1624,6 +1624,16 @@ static void rk3568_dump_cru(void)
}
}
static int protect_clocks[] = {
ACLK_VO,
HCLK_VO,
ACLK_VOP,
HCLK_VOP,
DCLK_VOP0,
DCLK_VOP1,
DCLK_VOP2,
};
static void __init rk3568_pmu_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
@@ -1701,6 +1711,8 @@ static void __init rk3568_clk_init(struct device_node *np)
if (!rk_dump_cru)
rk_dump_cru = rk3568_dump_cru;
rockchip_clk_protect(ctx, protect_clocks, ARRAY_SIZE(protect_clocks));
}
CLK_OF_DECLARE(rk3568_cru, "rockchip,rk3568-cru", rk3568_clk_init);

7
drivers/edac/Kconfig
View File

@@ -541,4 +541,11 @@ config EDAC_DMC520
Support for error detection and correction on the
SoCs with ARM DMC-520 DRAM controller.
config EDAC_ROCKCHIP
tristate "Rockchip DDR ECC"
depends on ARCH_ROCKCHIP && HAVE_ARM_SMCCC
help
Support for error detection and correction on the
rockchip family of SOCs.
endif # EDAC

1
drivers/edac/Makefile
View File

@@ -84,3 +84,4 @@ obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o
obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o
obj-$(CONFIG_EDAC_BLUEFIELD) += bluefield_edac.o
obj-$(CONFIG_EDAC_DMC520) += dmc520_edac.o
obj-$(CONFIG_EDAC_ROCKCHIP) += rockchip_edac.o

358
drivers/edac/rockchip_edac.c Normal file
View File

@@ -0,0 +1,358 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include <linux/edac.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rockchip/rockchip_sip.h>
#include <soc/rockchip/rockchip_sip.h>
#include "edac_module.h"
#define MAX_CS (4)
#define MAX_CH (1)
#define RK_EDAC_MOD "1"
/* ECCCADDR0 */
#define ECC_CORR_RANK_SHIFT (24)
#define ECC_CORR_RANK_MASK (0x3)
#define ECC_CORR_ROW_MASK (0x3ffff)
/* ECCCADDR1 */
#define ECC_CORR_CID_SHIFT (28)
#define ECC_CORR_CID_MASK (0x3)
#define ECC_CORR_BG_SHIFT (24)
#define ECC_CORR_BG_MASK (0x3)
#define ECC_CORR_BANK_SHIFT (16)
#define ECC_CORR_BANK_MASK (0x7)
#define ECC_CORR_COL_MASK (0xfff)
/* ECCUADDR0 */
#define ECC_UNCORR_RANK_SHIFT (24)
#define ECC_UNCORR_RANK_MASK (0x3)
#define ECC_UNCORR_ROW_MASK (0x3ffff)
/* ECCUADDR1 */
#define ECC_UNCORR_CID_SHIFT (28)
#define ECC_UNCORR_CID_MASK (0x3)
#define ECC_UNCORR_BG_SHIFT (24)
#define ECC_UNCORR_BG_MASK (0x3)
#define ECC_UNCORR_BANK_SHIFT (16)
#define ECC_UNCORR_BANK_MASK (0x7)
#define ECC_UNCORR_COL_MASK (0xfff)
/**
* struct ddr_ecc_error_info - DDR ECC error log information
* @err_cnt: error count
* @rank: Rank number
* @row: Row number
* @chip_id: Chip id number
* @bank_group: Bank Group number
* @bank: Bank number
* @col: Column number
* @bitpos: Bit position
*/
struct ddr_ecc_error_info {
u32 err_cnt;
u32 rank;
u32 row;
u32 chip_id;
u32 bank_group;
u32 bank;
u32 col;
u32 bitpos;
};
/**
* struct ddr_ecc_status - DDR ECC status information to report
* @ceinfo: Correctable error log information
* @ueinfo: Uncorrectable error log information
*/
struct ddr_ecc_status {
struct ddr_ecc_error_info ceinfo;
struct ddr_ecc_error_info ueinfo;
};
/**
* struct rk_edac_priv - RK DDR memory controller private instance data
* @name: EDAC name
* @stat: DDR ECC status information
* @ce_cnt: Correctable Error count
* @ue_cnt: Uncorrectable Error count
* @irq_ce: Corrected interrupt number
* @irq_ue: Uncorrected interrupt number
*/
struct rk_edac_priv {
char *name;
struct ddr_ecc_status stat;
u32 ce_cnt;
u32 ue_cnt;
int irq_ce;
int irq_ue;
};
static struct ddr_ecc_status *ddr_edac_info;
static inline void opstate_init_int(void)
{
switch (edac_op_state) {
case EDAC_OPSTATE_POLL:
case EDAC_OPSTATE_INT:
break;
default:
edac_op_state = EDAC_OPSTATE_INT;
break;
}
}
static void rockchip_edac_handle_ce_error(struct mem_ctl_info *mci,
struct ddr_ecc_status *p)
{
struct ddr_ecc_error_info *pinf;
if (p->ceinfo.err_cnt) {
pinf = &p->ceinfo;
edac_mc_printk(mci, KERN_ERR,
"DDR ECC CE error: CS%d, Row 0x%x, Bg 0x%x, Bk 0x%x, Col 0x%x bit 0x%x\n",
pinf->rank, pinf->row, pinf->bank_group,
pinf->bank, pinf->col,
pinf->bitpos);
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
p->ceinfo.err_cnt, 0, 0, 0, 0, 0, -1,
mci->ctl_name, "");
}
}
static void rockchip_edac_handle_ue_error(struct mem_ctl_info *mci,
struct ddr_ecc_status *p)
{
struct ddr_ecc_error_info *pinf;
if (p->ueinfo.err_cnt) {
pinf = &p->ueinfo;
edac_mc_printk(mci, KERN_ERR,
"DDR ECC UE error: CS%d, Row 0x%x, Bg 0x%x, Bk 0x%x, Col 0x%x\n",
pinf->rank, pinf->row,
pinf->bank_group, pinf->bank, pinf->col);
edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
p->ueinfo.err_cnt, 0, 0, 0, 0, 0, -1,
mci->ctl_name, "");
}
}
static int rockchip_edac_get_error_info(struct mem_ctl_info *mci)
{
struct arm_smccc_res res;
res = sip_smc_dram(SHARE_PAGE_TYPE_DDRECC, 0,
ROCKCHIP_SIP_CONFIG_DRAM_ECC);
if ((res.a0) || (res.a1)) {
edac_mc_printk(mci, KERN_ERR, "ROCKCHIP_SIP_CONFIG_DRAM_ECC not support: 0x%lx\n",
res.a0);
return -ENXIO;
}
return 0;
}
static void rockchip_edac_check(struct mem_ctl_info *mci)
{
struct rk_edac_priv *priv = mci->pvt_info;
int ret;
ret = rockchip_edac_get_error_info(mci);
if (ret)
return;
priv->ce_cnt += ddr_edac_info->ceinfo.err_cnt;
priv->ue_cnt += ddr_edac_info->ceinfo.err_cnt;
rockchip_edac_handle_ce_error(mci, ddr_edac_info);
rockchip_edac_handle_ue_error(mci, ddr_edac_info);
}
static irqreturn_t rockchip_edac_mc_ce_isr(int irq, void *dev_id)
{
struct mem_ctl_info *mci = dev_id;
struct rk_edac_priv *priv = mci->pvt_info;
int ret;
ret = rockchip_edac_get_error_info(mci);
if (ret)
return IRQ_NONE;
priv->ce_cnt += ddr_edac_info->ceinfo.err_cnt;
rockchip_edac_handle_ce_error(mci, ddr_edac_info);
return IRQ_HANDLED;
}
static irqreturn_t rockchip_edac_mc_ue_isr(int irq, void *dev_id)
{
struct mem_ctl_info *mci = dev_id;
struct rk_edac_priv *priv = mci->pvt_info;
int ret;
ret = rockchip_edac_get_error_info(mci);
if (ret)
return IRQ_NONE;
priv->ue_cnt += ddr_edac_info->ueinfo.err_cnt;
rockchip_edac_handle_ue_error(mci, ddr_edac_info);
return IRQ_HANDLED;
}
static int rockchip_edac_mc_init(struct mem_ctl_info *mci,
struct platform_device *pdev)
{
struct rk_edac_priv *priv = mci->pvt_info;
struct arm_smccc_res res;
int ret;
mci->pdev = &pdev->dev;
dev_set_drvdata(mci->pdev, mci);
mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4;
mci->edac_ctl_cap = EDAC_FLAG_SECDED;
mci->scrub_cap = SCRUB_NONE;
mci->scrub_mode = SCRUB_NONE;
mci->edac_cap = EDAC_FLAG_SECDED;
mci->ctl_name = priv->name;
mci->dev_name = priv->name;
mci->mod_name = RK_EDAC_MOD;
if (edac_op_state == EDAC_OPSTATE_POLL)
mci->edac_check = rockchip_edac_check;
mci->ctl_page_to_phys = NULL;
res = sip_smc_request_share_mem(1, SHARE_PAGE_TYPE_DDRECC);
if (res.a0 != 0) {
dev_err(&pdev->dev, "no ATF memory for init, ret 0x%lx\n", res.a0);
return -ENOMEM;
}
ddr_edac_info = (struct ddr_ecc_status *)res.a1;
memset(ddr_edac_info, 0, sizeof(struct ddr_ecc_status));
ret = rockchip_edac_get_error_info(mci);
if (ret)
return ret;
return 0;
}
static int rockchip_edac_probe(struct platform_device *pdev)
{
struct mem_ctl_info *mci;
struct edac_mc_layer layers[2];
struct rk_edac_priv *priv;
int ret;
opstate_init_int();
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
layers[0].size = MAX_CS;
layers[0].is_virt_csrow = true;
layers[1].type = EDAC_MC_LAYER_CHANNEL;
layers[1].size = MAX_CH;
layers[1].is_virt_csrow = false;
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
sizeof(struct rk_edac_priv));
if (!mci) {
edac_printk(KERN_ERR, EDAC_MC,
"Failed memory allocation for mc instance\n");
return -ENOMEM;
}
priv = mci->pvt_info;
priv->name = "rk_edac_ecc";
ret = rockchip_edac_mc_init(mci, pdev);
if (ret) {
edac_printk(KERN_ERR, EDAC_MC,
"Failed to initialize instance\n");
goto free_edac_mc;
}
ret = edac_mc_add_mc(mci);
if (ret) {
edac_printk(KERN_ERR, EDAC_MC,
"Failed edac_mc_add_mc()\n");
goto free_edac_mc;
}
if (edac_op_state == EDAC_OPSTATE_INT) {
/* register interrupts */
priv->irq_ce = platform_get_irq_byname(pdev, "ce");
ret = devm_request_irq(&pdev->dev, priv->irq_ce,
rockchip_edac_mc_ce_isr,
0,
"[EDAC] MC err", mci);
if (ret < 0) {
edac_printk(KERN_ERR, EDAC_MC,
"%s: Unable to request ce irq %d for RK EDAC\n",
__func__, priv->irq_ce);
goto del_mc;
}
edac_printk(KERN_INFO, EDAC_MC,
"acquired ce irq %d for MC\n",
priv->irq_ce);
priv->irq_ue = platform_get_irq_byname(pdev, "ue");
ret = devm_request_irq(&pdev->dev, priv->irq_ue,
rockchip_edac_mc_ue_isr,
0,
"[EDAC] MC err", mci);
if (ret < 0) {
edac_printk(KERN_ERR, EDAC_MC,
"%s: Unable to request ue irq %d for RK EDAC\n",
__func__, priv->irq_ue);
goto del_mc;
}
edac_printk(KERN_INFO, EDAC_MC,
"acquired ue irq %d for MC\n",
priv->irq_ue);
}
return 0;
del_mc:
edac_mc_del_mc(&pdev->dev);
free_edac_mc:
edac_mc_free(mci);
return -ENODEV;
}
static int rockchip_edac_remove(struct platform_device *pdev)
{
struct mem_ctl_info *mci = dev_get_drvdata(&pdev->dev);
edac_mc_del_mc(&pdev->dev);
edac_mc_free(mci);
return 0;
}
static const struct of_device_id rk_ddr_mc_err_of_match[] = {
{ .compatible = "rockchip,rk3568-edac", },
{},
};
MODULE_DEVICE_TABLE(of, rk_ddr_mc_err_of_match);
static struct platform_driver rockchip_edac_driver = {
.probe = rockchip_edac_probe,
.remove = rockchip_edac_remove,
.driver = {
.name = "rk_edac",
.of_match_table = rk_ddr_mc_err_of_match,
},
};
module_platform_driver(rockchip_edac_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("He Zhihuan <huan.he@rock-chips.com>\n");
MODULE_DESCRIPTION("ROCKCHIP EDAC kernel module");

18
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c
View File

@@ -2262,6 +2262,7 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
struct drm_display_mode *mode;
struct drm_display_info *info = &connector->display_info;
void *data = hdmi->plat_data->phy_data;
struct drm_property_blob *edid_blob_ptr = connector->edid_blob_ptr;
int i, ret = 0;
if (hdmi->plat_data->right && hdmi->plat_data->right->next_bridge) {
@@ -2283,7 +2284,17 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
return 0;
memset(metedata, 0, sizeof(*metedata));
edid = drm_get_edid(connector, hdmi->ddc);
if (edid_blob_ptr && edid_blob_ptr->length) {
edid = kmalloc(edid_blob_ptr->length, GFP_KERNEL);
if (!edid)
return -ENOMEM;
memcpy(edid, edid_blob_ptr->data, edid_blob_ptr->length);
} else {
edid = drm_get_edid(connector, hdmi->ddc);
hdmi->hdcp_caps = dw_hdmi_qp_hdcp_capable(hdmi);
}
if (edid) {
dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
edid->width_cm, edid->height_cm);
@@ -2311,8 +2322,10 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
else if (hdmi->plat_data->right)
secondary = hdmi->plat_data->right;
if (!secondary)
if (!secondary) {
kfree(edid);
return -ENOMEM;
}
secondary_data = secondary->plat_data->phy_data;
list_for_each_entry(mode, &connector->probed_modes, head)
@@ -4051,6 +4064,7 @@ void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi)
disable_irq(hdmi->earc_irq);
pinctrl_pm_select_sleep_state(dev);
drm_connector_update_edid_property(&hdmi->connector, NULL);
}
EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend);

10
drivers/media/platform/rockchip/cif/capture.c
View File

@@ -8513,7 +8513,11 @@ static void rkcif_buf_done_prepare(struct rkcif_stream *stream,
if (active_buf) {
vb_done = &active_buf->vb;
vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
if (cif_dev->chip_id < CHIP_RK3588_CIF &&
cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656)
vb_done->vb2_buf.timestamp = stream->readout.fe_timestamp;
else
vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
vb_done->sequence = stream->frame_idx - 1;
active_buf->fe_timestamp = ktime_get_ns();
if (stream->is_line_wake_up) {
@@ -8834,6 +8838,10 @@ static void rkcif_update_stream(struct rkcif_device *cif_dev,
if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
return;
}
if (cif_dev->chip_id < CHIP_RK3588_CIF &&
cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656 &&
stream->id != 0)
stream->frame_idx++;
if (!stream->is_line_wake_up && stream->dma_en & RKCIF_DMAEN_BY_VICAP)
rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0);

23
drivers/media/platform/rockchip/isp/capture.c
View File

@@ -626,7 +626,7 @@ static void restrict_rsz_resolution(struct rkisp_stream *stream,
max_rsz->width = ALIGN(DIV_ROUND_UP(input_win->width, div), 4);
max_rsz->height = DIV_ROUND_UP(input_win->height, div);
} else if (dev->hw_dev->is_unite) {
} else if (dev->hw_dev->unite) {
/* scale down only for unite mode */
max_rsz->width = min_t(int, input_win->width, cfg->max_rsz_width);
max_rsz->height = min_t(int, input_win->height, cfg->max_rsz_height);
@@ -1140,7 +1140,8 @@ static int rkisp_set_wrap_line(struct rkisp_stream *stream, struct rkisp_wrap_in
if (dev->isp_ver != ISP_V32 ||
dev->hw_dev->dev_link_num > 1 ||
!stream->ops->set_wrap) {
!stream->ops->set_wrap ||
dev->hw_dev->unite) {
v4l2_err(&dev->v4l2_dev,
"wrap only support for single sensor and mainpath\n");
return -EINVAL;
@@ -1465,7 +1466,7 @@ static struct v4l2_rect *rkisp_update_crop(struct rkisp_stream *stream,
const struct v4l2_rect *in)
{
struct rkisp_device *dev = stream->ispdev;
bool is_unite = dev->hw_dev->is_unite;
bool is_unite = !!dev->hw_dev->unite;
u32 align = is_unite ? 4 : 2;
/* Not crop for MP bayer raw data and dmatx path */
@@ -1735,17 +1736,21 @@ int rkisp_register_stream_vdevs(struct rkisp_device *dev)
st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V21;
ret = rkisp_register_stream_v21(dev);
} else if (dev->isp_ver == ISP_V30) {
st_cfg->max_rsz_width = dev->hw_dev->is_unite ?
st_cfg->max_rsz_width = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
st_cfg->max_rsz_height = dev->hw_dev->is_unite ?
st_cfg->max_rsz_height = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
ret = rkisp_register_stream_v30(dev);
} else if (dev->isp_ver == ISP_V32) {
st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32;
st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32;
st_cfg->max_rsz_width = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
st_cfg->max_rsz_height = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
st_cfg = &rkisp_sp_stream_config;
st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32;
st_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V32;
st_cfg->max_rsz_width = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
st_cfg->max_rsz_height = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
ret = rkisp_register_stream_v32(dev);
} else if (dev->isp_ver == ISP_V32_L) {
st_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V32_L;

117
drivers/media/platform/rockchip/isp/capture_v30.c
View File

@@ -332,7 +332,7 @@ static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async)
if (dcrop->width == input_win->width &&
dcrop->height == input_win->height &&
dcrop->left == 0 && dcrop->top == 0 &&
!dev->hw_dev->is_unite) {
!dev->hw_dev->unite) {
rkisp_disable_dcrop(stream, async);
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"stream %d crop disabled\n", stream->id);
@@ -472,7 +472,7 @@ static int mp_config_mi(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
bool is_unite = dev->hw_dev->is_unite;
bool is_unite = !!dev->hw_dev->unite;
u32 val, mask;
/*
@@ -480,26 +480,26 @@ static int mp_config_mi(struct rkisp_stream *stream)
* memory plane formats, so calculate the size explicitly.
*/
val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite);
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
val = out_fmt->plane_fmt[1].sizeimage;
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite);
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
val = out_fmt->plane_fmt[2].sizeimage;
rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false, is_unite);
rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);
val = is_unite ? out_fmt->width / 2 : out_fmt->width;
rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_WIDTH, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_WIDTH, val, false);
val = out_fmt->height;
rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_HEIGHT, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_PIC_HEIGHT, val, false);
val = out_fmt->plane_fmt[0].bytesperline;
rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_MP_UV_SWAP : 0;
mask = ISP3X_MI_XTD_FORMAT_MP_UV_SWAP;
rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MP_YUV_MODE;
val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -511,13 +511,13 @@ static int mp_config_mi(struct rkisp_stream *stream)
val |= ISP3X_SEPERATE_YUV_CFG;
else
val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_MP_YUV_MODE;
rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_MP_AUTOUPDATE_ENABLE |
stream->out_isp_fmt.write_format;
mask = GENMASK(19, 16) | MI_CTRL_MP_FMT_MASK;
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
mi_frame_end_int_enable(stream);
/* set up first buffer */
@@ -558,7 +558,7 @@ static int sp_config_mi(struct rkisp_stream *stream)
struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
struct ispsd_out_fmt *input_isp_fmt =
rkisp_get_ispsd_out_fmt(&dev->isp_sdev);
bool is_unite = dev->hw_dev->is_unite;
bool is_unite = !!dev->hw_dev->unite;
u32 sp_in_fmt, val, mask;
if (mbus_code_sp_in_fmt(input_isp_fmt->mbus_code,
@@ -572,26 +572,26 @@ static int sp_config_mi(struct rkisp_stream *stream)
* memory plane formats, so calculate the size explicitly.
*/
val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite);
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
val = out_fmt->plane_fmt[1].sizeimage;
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite);
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
val = out_fmt->plane_fmt[2].sizeimage;
rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false, is_unite);
rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);
val = is_unite ? out_fmt->width / 2 : out_fmt->width;
rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_WIDTH, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_WIDTH, val, false);
val = out_fmt->height;
rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_HEIGHT, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_PIC_HEIGHT, val, false);
val = stream->u.sp.y_stride;
rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false);
val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_SP_UV_SWAP : 0;
mask = ISP3X_MI_XTD_FORMAT_SP_UV_SWAP;
rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false, is_unite);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_SP_YUV_MODE;
val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -603,14 +603,14 @@ static int sp_config_mi(struct rkisp_stream *stream)
val |= ISP3X_SEPERATE_YUV_CFG;
else
val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_SP_YUV_MODE;
rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
CIF_MI_CTRL_INIT_OFFSET_EN | stream->out_isp_fmt.write_format |
sp_in_fmt | stream->out_isp_fmt.output_format |
CIF_MI_SP_AUTOUPDATE_ENABLE;
mask = GENMASK(19, 16) | MI_CTRL_SP_FMT_MASK;
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false, is_unite);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
mi_frame_end_int_enable(stream);
/* set up first buffer */
@@ -625,12 +625,12 @@ static int fbc_config_mi(struct rkisp_stream *stream)
u32 h = ALIGN(stream->out_fmt.height, 16);
u32 w = ALIGN(stream->out_fmt.width, 16);
u32 offs = ALIGN(w * h / 16, RK_MPP_ALIGN);
bool is_unite = stream->ispdev->hw_dev->is_unite;
bool is_unite = !!stream->ispdev->hw_dev->unite;
rkisp_write(stream->ispdev, ISP3X_MPFBC_HEAD_OFFSET, offs, false);
rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_WIDTH, w, false, is_unite);
rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_PAYL_WIDTH, w, false, is_unite);
rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_HEIGHT, h, false, is_unite);
rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_WIDTH, w, false);
rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_PAYL_WIDTH, w, false);
rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_VIR_HEIGHT, h, false);
if (is_unite) {
u32 left_w = (stream->out_fmt.width / 2) & ~0xf;
@@ -638,8 +638,7 @@ static int fbc_config_mi(struct rkisp_stream *stream)
rkisp_next_write(stream->ispdev, ISP3X_MPFBC_HEAD_OFFSET, offs, false);
}
rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, 0,
CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN,
false, is_unite);
CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN, false);
mi_frame_end_int_enable(stream);
/* set up first buffer */
mi_frame_end(stream, FRAME_INIT);
@@ -650,7 +649,7 @@ static int bp_config_mi(struct rkisp_stream *stream)
{
struct v4l2_pix_format_mplane *out_fmt = &stream->out_fmt;
struct rkisp_device *dev = stream->ispdev;
bool is_unite = dev->hw_dev->is_unite;
bool is_unite = dev->hw_dev->unite;
u32 val, mask;
/*
@@ -658,19 +657,19 @@ static int bp_config_mi(struct rkisp_stream *stream)
* memory plane formats, so calculate the size explicitly.
*/
val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false, is_unite);
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
val = out_fmt->plane_fmt[1].sizeimage;
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false, is_unite);
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
val = is_unite ? out_fmt->width / 2 : out_fmt->width;
rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_WIDTH, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_WIDTH, val, false);
val = out_fmt->height;
rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_HEIGHT, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_PIC_HEIGHT, val, false);
val = out_fmt->plane_fmt[0].bytesperline;
rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false);
mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_BP_YUV_MODE;
val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -680,9 +679,9 @@ static int bp_config_mi(struct rkisp_stream *stream)
val |= ISP3X_SEPERATE_YUV_CFG;
else
val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_BP_YUV_MODE;
rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false, is_unite);
rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN;
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false, is_unite);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false);
mi_frame_end_int_enable(stream);
/* set up first buffer */
mi_frame_end(stream, FRAME_INIT);
@@ -697,8 +696,7 @@ static void mp_enable_mi(struct rkisp_stream *stream)
if (isp_fmt->fmt_type == FMT_BAYER)
val = CIF_MI_CTRL_RAW_ENABLE;
rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val,
false, stream->ispdev->hw_dev->is_unite);
rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
}
static void sp_enable_mi(struct rkisp_stream *stream)
@@ -711,21 +709,18 @@ static void sp_enable_mi(struct rkisp_stream *stream)
if (fmt->fmt_type == FMT_RGB &&
dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
val |= mask;
rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL,
mask, val, false,
stream->ispdev->hw_dev->is_unite);
rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
}
static void fbc_enable_mi(struct rkisp_stream *stream)
{
u32 val, mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MPFBC_YUV_MASK |
ISP3X_MPFBC_SPARSE_MODE;
bool is_unite = stream->ispdev->hw_dev->is_unite;
/* config no effect immediately, read back is shadow, get config value from cache */
val = rkisp_read_reg_cache(stream->ispdev, ISP3X_MPFBC_CTRL) & ~mask;
val |= stream->out_isp_fmt.write_format | ISP3X_HEAD_OFFSET_EN | ISP3X_MPFBC_EN;
rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_CTRL, val, false, is_unite);
rkisp_unite_write(stream->ispdev, ISP3X_MPFBC_CTRL, val, false);
}
static void bp_enable_mi(struct rkisp_stream *stream)
@@ -733,36 +728,31 @@ static void bp_enable_mi(struct rkisp_stream *stream)
u32 val = stream->out_isp_fmt.write_format |
ISP3X_BP_ENABLE | ISP3X_BP_AUTO_UPD;
rkisp_unite_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false,
stream->ispdev->hw_dev->is_unite);
rkisp_unite_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false);
}
static void mp_disable_mi(struct rkisp_stream *stream)
{
u32 mask = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE;
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false,
stream->ispdev->hw_dev->is_unite);
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false);
}
static void sp_disable_mi(struct rkisp_stream *stream)
{
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE,
false, stream->ispdev->hw_dev->is_unite);
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false);
}
static void fbc_disable_mi(struct rkisp_stream *stream)
{
u32 mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MPFBC_EN;
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MPFBC_CTRL, mask,
false, stream->ispdev->hw_dev->is_unite);
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MPFBC_CTRL, mask, false);
}
static void bp_disable_mi(struct rkisp_stream *stream)
{
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE,
false, stream->ispdev->hw_dev->is_unite);
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, false);
}
static void update_mi(struct rkisp_stream *stream)
@@ -786,7 +776,7 @@ static void update_mi(struct rkisp_stream *stream)
rkisp_write(dev, reg, val, false);
}
if (dev->hw_dev->is_unite) {
if (dev->hw_dev->unite) {
u32 mult = stream->id != RKISP_STREAM_FBC ? 1 :
(stream->out_isp_fmt.write_format ? 32 : 24);
u32 div = stream->out_isp_fmt.fourcc == V4L2_PIX_FMT_UYVY ? 1 : 2;
@@ -818,22 +808,22 @@ static void update_mi(struct rkisp_stream *stream)
stream->dbg.frameloss++;
val = dummy_buf->dma_addr;
reg = stream->config->mi.y_base_ad_init;
rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite);
rkisp_unite_write(dev, reg, val, false);
reg = stream->config->mi.cb_base_ad_init;
rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite);
rkisp_unite_write(dev, reg, val, false);
reg = stream->config->mi.cr_base_ad_init;
if (stream->id != RKISP_STREAM_FBC && stream->id != RKISP_STREAM_BP)
rkisp_unite_write(dev, reg, val, false, dev->hw_dev->is_unite);
rkisp_unite_write(dev, reg, val, false);
}
if (stream->id != RKISP_STREAM_FBC) {
reg = stream->config->mi.y_offs_cnt_init;
rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite);
rkisp_unite_write(dev, reg, 0, false);
reg = stream->config->mi.cb_offs_cnt_init;
rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite);
rkisp_unite_write(dev, reg, 0, false);
reg = stream->config->mi.cr_offs_cnt_init;
if (stream->id != RKISP_STREAM_BP)
rkisp_unite_write(dev, reg, 0, false, dev->hw_dev->is_unite);
rkisp_unite_write(dev, reg, 0, false);
}
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
@@ -842,7 +832,7 @@ static void update_mi(struct rkisp_stream *stream)
rkisp_read(dev, stream->config->mi.y_base_ad_init, false),
rkisp_read(dev, stream->config->mi.cb_base_ad_init, false),
rkisp_read(dev, stream->config->mi.y_base_ad_shd, true));
if (dev->hw_dev->is_unite)
if (dev->hw_dev->unite)
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"%s stream:%d Y:0x%x CB:0x%x | Y_SHD:0x%x, right\n",
__func__, stream->id,
@@ -897,11 +887,10 @@ static void stream_self_update(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
u32 val, mask = ISP3X_MPSELF_UPD | ISP3X_SPSELF_UPD | ISP3X_BPSELF_UPD;
bool is_unite = dev->hw_dev->is_unite;
if (stream->id == RKISP_STREAM_FBC) {
val = ISP3X_MPFBC_FORCE_UPD;
rkisp_unite_set_bits(dev, ISP3X_MPFBC_CTRL, 0, val, false, is_unite);
rkisp_unite_set_bits(dev, ISP3X_MPFBC_CTRL, 0, val, false);
return;
}
@@ -919,7 +908,7 @@ static void stream_self_update(struct rkisp_stream *stream)
return;
}
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL2, mask, val, false, is_unite);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL2, mask, val, false);
}
static int mi_frame_start(struct rkisp_stream *stream, u32 mis)
@@ -1690,7 +1679,7 @@ void rkisp_mi_v30_isr(u32 mis_val, struct rkisp_device *dev)
struct rkisp_stream *stream;
unsigned int i;
if (dev->hw_dev->is_unite) {
if (dev->hw_dev->unite) {
u32 val = rkisp_read(dev, ISP3X_MI_RIS, true);
if (val) {

137
drivers/media/platform/rockchip/isp/capture_v32.c
View File

@@ -554,7 +554,8 @@ static int rkisp_stream_config_dcrop(struct rkisp_stream *stream, bool async)
if (dcrop->width == input_win->width &&
dcrop->height == input_win->height &&
dcrop->left == 0 && dcrop->top == 0) {
dcrop->left == 0 && dcrop->top == 0 &&
!dev->hw_dev->unite) {
rkisp_disable_dcrop(stream, async);
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"stream %d crop disabled\n", stream->id);
@@ -704,29 +705,29 @@ static int mp_config_mi(struct rkisp_stream *stream)
/* in bytes for isp32 */
if (dev->isp_ver == ISP_V32 &&
stream->out_isp_fmt.write_format != MI_CTRL_MP_WRITE_YUVINT)
rkisp_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
val /= DIV_ROUND_UP(fmt->bpp[0], 8);
/* in pixels for isp32 lite */
if (dev->isp_ver == ISP_V32_L)
rkisp_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
rkisp_unite_write(dev, ISP3X_MI_MP_WR_Y_LLENGTH, val, false);
val *= height;
rkisp_write(dev, stream->config->mi.y_pic_size, val, false);
rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false);
val = out_fmt->plane_fmt[0].bytesperline * height;
rkisp_write(dev, stream->config->mi.y_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
val = out_fmt->plane_fmt[1].sizeimage;
if (dev->cap_dev.wrap_line)
val = out_fmt->plane_fmt[0].bytesperline * height / 2;
rkisp_write(dev, stream->config->mi.cb_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
val = out_fmt->plane_fmt[2].sizeimage;
if (dev->cap_dev.wrap_line)
val = out_fmt->plane_fmt[0].bytesperline * height / 2;
rkisp_write(dev, stream->config->mi.cr_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);
val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_MP_UV_SWAP : 0;
mask = ISP3X_MI_XTD_FORMAT_MP_UV_SWAP;
rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_MP_YUV_MODE;
val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -738,24 +739,24 @@ static int mp_config_mi(struct rkisp_stream *stream)
val |= ISP3X_SEPERATE_YUV_CFG;
else
val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_MP_YUV_MODE;
rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false);
rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
val = stream->out_isp_fmt.output_format;
rkisp_write(dev, ISP32_MI_MP_WR_CTRL, val, false);
rkisp_unite_write(dev, ISP32_MI_MP_WR_CTRL, val, false);
val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_MP_AUTOUPDATE_ENABLE |
stream->out_isp_fmt.write_format;
mask = GENMASK(19, 16) | MI_CTRL_MP_FMT_MASK;
rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
mi_frame_end_int_enable(stream);
/* set up first buffer */
mi_frame_end(stream, FRAME_INIT);
rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
rkisp_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
return 0;
}
@@ -805,21 +806,21 @@ static int sp_config_mi(struct rkisp_stream *stream)
* memory plane formats, so calculate the size explicitly.
*/
val = stream->u.sp.y_stride;
rkisp_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false);
rkisp_unite_write(dev, ISP3X_MI_SP_WR_Y_LLENGTH, val, false);
val *= out_fmt->height;
rkisp_write(dev, stream->config->mi.y_pic_size, val, false);
rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false);
val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
rkisp_write(dev, stream->config->mi.y_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
val = out_fmt->plane_fmt[1].sizeimage;
rkisp_write(dev, stream->config->mi.cb_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
val = out_fmt->plane_fmt[2].sizeimage;
rkisp_write(dev, stream->config->mi.cr_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.cr_size_init, val, false);
val = stream->out_isp_fmt.uv_swap ? ISP3X_MI_XTD_FORMAT_SP_UV_SWAP : 0;
mask = ISP3X_MI_XTD_FORMAT_SP_UV_SWAP;
rkisp_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_XTD_FORMAT_CTRL, mask, val, false);
mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_SP_YUV_MODE;
val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -831,22 +832,22 @@ static int sp_config_mi(struct rkisp_stream *stream)
val |= ISP3X_SEPERATE_YUV_CFG;
else
val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_SP_YUV_MODE;
rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false);
rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
val = calc_burst_len(stream) | CIF_MI_CTRL_INIT_BASE_EN |
CIF_MI_CTRL_INIT_OFFSET_EN | stream->out_isp_fmt.write_format |
sp_in_fmt | stream->out_isp_fmt.output_format |
CIF_MI_SP_AUTOUPDATE_ENABLE;
mask = GENMASK(19, 16) | MI_CTRL_SP_FMT_MASK;
rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask, val, false);
mi_frame_end_int_enable(stream);
/* set up first buffer */
mi_frame_end(stream, FRAME_INIT);
rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
rkisp_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.cr_offs_cnt_init, 0, false);
return 0;
}
@@ -864,18 +865,18 @@ static int bp_config_mi(struct rkisp_stream *stream)
val = out_fmt->plane_fmt[0].bytesperline;
/* in bytes */
if (stream->out_isp_fmt.write_format != ISP3X_BP_FORMAT_INT)
rkisp_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false);
rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false);
val /= DIV_ROUND_UP(fmt->bpp[0], 8);
/* in pixels */
if (stream->out_isp_fmt.write_format == ISP3X_BP_FORMAT_INT)
rkisp_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false);
rkisp_unite_write(dev, ISP3X_MI_BP_WR_Y_LLENGTH, val, false);
val *= out_fmt->height;
rkisp_write(dev, stream->config->mi.y_pic_size, val, false);
rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false);
val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
rkisp_write(dev, stream->config->mi.y_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
val = out_fmt->plane_fmt[1].sizeimage;
rkisp_write(dev, stream->config->mi.cb_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
mask = ISP3X_MPFBC_FORCE_UPD | ISP3X_BP_YUV_MODE;
val = rkisp_read_reg_cache(dev, ISP3X_MPFBC_CTRL) & ~mask;
@@ -885,15 +886,15 @@ static int bp_config_mi(struct rkisp_stream *stream)
val |= ISP3X_SEPERATE_YUV_CFG;
else
val |= ISP3X_SEPERATE_YUV_CFG | ISP3X_BP_YUV_MODE;
rkisp_write(dev, ISP3X_MPFBC_CTRL, val, false);
rkisp_unite_write(dev, ISP3X_MPFBC_CTRL, val, false);
val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN;
rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false);
mi_frame_end_int_enable(stream);
/* set up first buffer */
mi_frame_end(stream, FRAME_INIT);
rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
return 0;
}
@@ -906,27 +907,27 @@ static int ds_config_mi(struct rkisp_stream *stream)
val = out_fmt->plane_fmt[0].bytesperline;
if (stream->out_isp_fmt.write_format != ISP3X_BP_FORMAT_INT)
rkisp_write(dev, stream->config->mi.length, val, false);
rkisp_unite_write(dev, stream->config->mi.length, val, false);
val /= DIV_ROUND_UP(fmt->bpp[0], 8);
if (stream->out_isp_fmt.write_format == ISP3X_BP_FORMAT_INT)
rkisp_write(dev, stream->config->mi.length, val, false);
rkisp_unite_write(dev, stream->config->mi.length, val, false);
val *= out_fmt->height;
rkisp_write(dev, stream->config->mi.y_pic_size, val, false);
rkisp_unite_write(dev, stream->config->mi.y_pic_size, val, false);
val = out_fmt->plane_fmt[0].bytesperline * out_fmt->height;
rkisp_write(dev, stream->config->mi.y_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.y_size_init, val, false);
val = out_fmt->plane_fmt[1].sizeimage;
rkisp_write(dev, stream->config->mi.cb_size_init, val, false);
rkisp_unite_write(dev, stream->config->mi.cb_size_init, val, false);
val = CIF_MI_CTRL_INIT_BASE_EN | CIF_MI_CTRL_INIT_OFFSET_EN;
rkisp_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false);
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, 0, val, false);
mi_frame_end_int_enable(stream);
mi_frame_end(stream, FRAME_INIT);
rkisp_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.y_offs_cnt_init, 0, false);
rkisp_unite_write(dev, stream->config->mi.cb_offs_cnt_init, 0, false);
return 0;
}
@@ -940,7 +941,7 @@ static void mp_enable_mi(struct rkisp_stream *stream)
if (isp_fmt->fmt_type == FMT_BAYER)
val = CIF_MI_CTRL_RAW_ENABLE;
rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
/* enable bpds path output */
if (t->streaming && !t->is_pause)
@@ -957,7 +958,7 @@ static void sp_enable_mi(struct rkisp_stream *stream)
if (fmt->fmt_type == FMT_RGB &&
dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
val |= mask;
rkisp_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
rkisp_unite_set_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, val, false);
}
static void bp_enable_mi(struct rkisp_stream *stream)
@@ -969,7 +970,7 @@ static void bp_enable_mi(struct rkisp_stream *stream)
stream->out_isp_fmt.output_format |
ISP3X_BP_ENABLE | ISP3X_BP_AUTO_UPD;
rkisp_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false);
rkisp_unite_write(stream->ispdev, ISP3X_MI_BP_WR_CTRL, val, false);
/* enable bpds path output */
if (t->streaming && !t->is_pause)
@@ -982,7 +983,7 @@ static void ds_enable_mi(struct rkisp_stream *stream)
stream->out_isp_fmt.output_format |
ISP32_DS_ENABLE | ISP32_DS_AUTO_UPD;
rkisp_write(stream->ispdev, stream->config->mi.ctrl, val, false);
rkisp_unite_write(stream->ispdev, stream->config->mi.ctrl, val, false);
}
static void mp_disable_mi(struct rkisp_stream *stream)
@@ -991,8 +992,7 @@ static void mp_disable_mi(struct rkisp_stream *stream)
struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id];
u32 mask = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE;
rkisp_set_bits(dev, 0x1814, 0, BIT(0), false);
rkisp_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false);
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, mask, false);
/* disable mpds path output */
if (!stream->is_pause && t->streaming)
@@ -1001,7 +1001,7 @@ static void mp_disable_mi(struct rkisp_stream *stream)
static void sp_disable_mi(struct rkisp_stream *stream)
{
rkisp_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false);
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_WR_CTRL, CIF_MI_CTRL_SP_ENABLE, false);
}
static void bp_disable_mi(struct rkisp_stream *stream)
@@ -1009,7 +1009,7 @@ static void bp_disable_mi(struct rkisp_stream *stream)
struct rkisp_device *dev = stream->ispdev;
struct rkisp_stream *t = &dev->cap_dev.stream[stream->conn_id];
rkisp_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, false);
rkisp_unite_clear_bits(stream->ispdev, ISP3X_MI_BP_WR_CTRL, ISP3X_BP_ENABLE, false);
/* disable bpds path output */
if (!stream->is_pause && t->streaming)
@@ -1018,7 +1018,7 @@ static void bp_disable_mi(struct rkisp_stream *stream)
static void ds_disable_mi(struct rkisp_stream *stream)
{
rkisp_clear_bits(stream->ispdev, stream->config->mi.ctrl, ISP32_DS_ENABLE, false);
rkisp_unite_clear_bits(stream->ispdev, stream->config->mi.ctrl, ISP32_DS_ENABLE, false);
}
static void update_mi(struct rkisp_stream *stream)
@@ -1048,6 +1048,25 @@ static void update_mi(struct rkisp_stream *stream)
rkisp_write(dev, reg, val, false);
}
if (dev->hw_dev->unite) {
reg = stream->config->mi.y_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_Y];
val += ((stream->out_fmt.width / 2) & ~0xf);
rkisp_next_write(dev, reg, val, false);
reg = stream->config->mi.cb_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CB];
val += ((stream->out_fmt.width / 2) & ~0xf);
rkisp_next_write(dev, reg, val, false);
if (is_cr_cfg) {
reg = stream->config->mi.cr_base_ad_init;
val = stream->next_buf->buff_addr[RKISP_PLANE_CR];
val += ((stream->out_fmt.width / 2) & ~0xf);
rkisp_next_write(dev, reg, val, false);
}
}
if (stream->is_pause) {
/* single sensor mode with pingpong buffer:
* if mi on, addr will auto update at frame end
@@ -1141,9 +1160,9 @@ static int set_mirror_flip(struct rkisp_stream *stream)
stream->is_mf_upd = false;
if (dev->cap_dev.is_mirror)
rkisp_set_bits(dev, ISP3X_ISP_CTRL0, 0, ISP32_MIR_ENABLE, false);
rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL0, 0, ISP32_MIR_ENABLE, false);
else
rkisp_clear_bits(dev, ISP3X_ISP_CTRL0, ISP32_MIR_ENABLE, false);
rkisp_unite_clear_bits(dev, ISP3X_ISP_CTRL0, ISP32_MIR_ENABLE, false);
switch (stream->id) {
case RKISP_STREAM_SP:
@@ -1169,9 +1188,9 @@ static int set_mirror_flip(struct rkisp_stream *stream)
tmp = rkisp_read_reg_cache(dev, ISP32_MI_WR_VFLIP_CTRL);
if (stream->is_flip)
rkisp_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp | val, false);
rkisp_unite_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp | val, false);
else
rkisp_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp & ~val, false);
rkisp_unite_write(dev, ISP32_MI_WR_VFLIP_CTRL, tmp & ~val, false);
return 0;
}
@@ -2268,6 +2287,12 @@ void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev)
v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
"mi isr:0x%x\n", mis_val);
if (dev->hw_dev->unite == ISP_UNITE_ONE &&
dev->unite_index == ISP_UNITE_LEFT) {
rkisp_write(dev, ISP3X_MI_ICR, mis_val, true);
goto end;
}
for (i = 0; i < RKISP_MAX_STREAM; ++i) {
stream = &dev->cap_dev.stream[i];
@@ -2310,7 +2335,7 @@ void rkisp_mi_v32_isr(u32 mis_val, struct rkisp_device *dev)
mi_frame_end(stream, FRAME_IRQ);
}
}
end:
if (mis_val & ISP3X_MI_MP_FRAME) {
stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
if (!stream->streaming)

8
drivers/media/platform/rockchip/isp/common.c
View File

@@ -6,6 +6,7 @@
#include <linux/of_platform.h>
#include <linux/slab.h>
#include "dev.h"
#include "hw.h"
#include "isp_ispp.h"
#include "regs.h"
@@ -36,6 +37,8 @@ void rkisp_next_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct
*flag = SW_REG_CACHE;
if (dev->hw_dev->is_single || is_direct) {
*flag = SW_REG_CACHE_SYNC;
if (dev->hw_dev->unite == ISP_UNITE_ONE)
return;
writel(val, dev->hw_dev->base_next_addr + reg);
}
}
@@ -166,13 +169,16 @@ void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end)
continue;
}
if (hw->unite == ISP_UNITE_ONE && dev->unite_index == ISP_UNITE_RIGHT)
val = dev->sw_base_addr + i + RKISP_ISP_SW_MAX_SIZE;
if (*flag == SW_REG_CACHE) {
if ((i == ISP3X_MAIN_RESIZE_CTRL ||
i == ISP32_BP_RESIZE_CTRL ||
i == ISP3X_SELF_RESIZE_CTRL) && *val == 0)
*val = CIF_RSZ_CTRL_CFG_UPD;
writel(*val, base + i);
if (hw->is_unite) {
if (hw->unite == ISP_UNITE_TWO) {
val = dev->sw_base_addr + i + RKISP_ISP_SW_MAX_SIZE;
if ((i == ISP3X_MAIN_RESIZE_CTRL ||
i == ISP32_BP_RESIZE_CTRL ||

26
drivers/media/platform/rockchip/isp/common.h
View File

@@ -186,32 +186,6 @@ u32 rkisp_next_read_reg_cache(struct rkisp_device *dev, u32 reg);
void rkisp_next_set_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask, u32 val);
void rkisp_next_clear_reg_cache_bits(struct rkisp_device *dev, u32 reg, u32 mask);
static inline void
rkisp_unite_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct, bool is_unite)
{
rkisp_write(dev, reg, val, is_direct);
if (is_unite)
rkisp_next_write(dev, reg, val, is_direct);
}
static inline void
rkisp_unite_set_bits(struct rkisp_device *dev, u32 reg, u32 mask,
u32 val, bool is_direct, bool is_unite)
{
rkisp_set_bits(dev, reg, mask, val, is_direct);
if (is_unite)
rkisp_next_set_bits(dev, reg, mask, val, is_direct);
}
static inline void
rkisp_unite_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask,
bool is_direct, bool is_unite)
{
rkisp_clear_bits(dev, reg, mask, is_direct);
if (is_unite)
rkisp_next_clear_bits(dev, reg, mask, is_direct);
}
void rkisp_update_regs(struct rkisp_device *dev, u32 start, u32 end);
int rkisp_alloc_buffer(struct rkisp_device *dev, struct rkisp_dummy_buffer *buf);

16
drivers/media/platform/rockchip/isp/csi.c
View File

@@ -607,8 +607,7 @@ int rkisp_csi_config_patch(struct rkisp_device *dev)
if (!dev->hw_dev->is_mi_update)
rkisp_unite_write(dev, CSI2RX_CTRL0,
SW_IBUF_OP_MODE(dev->hdr.op_mode),
true, dev->hw_dev->is_unite);
SW_IBUF_OP_MODE(dev->hdr.op_mode), true);
/* hdr merge */
switch (dev->hdr.op_mode) {
@@ -632,25 +631,22 @@ int rkisp_csi_config_patch(struct rkisp_device *dev)
return -EINVAL;
}
}
rkisp_unite_write(dev, ISP_HDRMGE_BASE, val, false, dev->hw_dev->is_unite);
rkisp_unite_write(dev, ISP_HDRMGE_BASE, val, false);
val = RAW_RD_SIZE_ERR;
if (!IS_HDR_RDBK(dev->hdr.op_mode))
val |= ISP21_MIPI_DROP_FRM;
rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT, 0, val, true, dev->hw_dev->is_unite);
rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT, 0, val, true);
}
if (IS_HDR_RDBK(dev->hdr.op_mode))
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS,
true, dev->hw_dev->is_unite);
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, true);
if (dev->isp_ver >= ISP_V30)
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS,
true, dev->hw_dev->is_unite);
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS, true);
/* line counter from isp out, default from mp out */
if (dev->isp_ver == ISP_V32_L)
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP32L_ISP2ENC_CNT_MUX,
true, dev->hw_dev->is_unite);
rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP32L_ISP2ENC_CNT_MUX, true);
dev->rdbk_cnt = -1;
dev->rdbk_cnt_x1 = -1;
dev->rdbk_cnt_x2 = -1;

13
drivers/media/platform/rockchip/isp/dev.c
View File

@@ -239,6 +239,8 @@ static int __isp_pipeline_s_isp_clk(struct rkisp_pipeline *p)
data_rate >>= 3;
end:
do_div(data_rate, 1000 * 1000);
if (hw_dev->unite == ISP_UNITE_ONE)
data_rate *= 4;
/* increase 25% margin */
data_rate += data_rate >> 2;
@@ -252,7 +254,7 @@ end:
/* set isp clock rate */
rkisp_set_clk_rate(hw_dev->clks[0], hw_dev->clk_rate_tbl[i].clk_rate * 1000000UL);
if (hw_dev->is_unite)
if (hw_dev->unite == ISP_UNITE_TWO)
rkisp_set_clk_rate(hw_dev->clks[5], hw_dev->clk_rate_tbl[i].clk_rate * 1000000UL);
/* aclk equal to core clk */
if (dev->isp_ver == ISP_V32)
@@ -840,7 +842,7 @@ static int rkisp_plat_probe(struct platform_device *pdev)
if (ret)
return ret;
if (isp_dev->hw_dev->is_unite)
if (isp_dev->hw_dev->unite)
mult = 2;
isp_dev->sw_base_addr = devm_kzalloc(dev, RKISP_ISP_SW_MAX_SIZE * mult, GFP_KERNEL);
if (!isp_dev->sw_base_addr)
@@ -852,7 +854,7 @@ static int rkisp_plat_probe(struct platform_device *pdev)
snprintf(isp_dev->media_dev.model, sizeof(isp_dev->media_dev.model),
"%s%d", DRIVER_NAME, isp_dev->dev_id);
if (!isp_dev->hw_dev->is_unite)
if (!isp_dev->hw_dev->unite)
strscpy(isp_dev->name, dev_name(dev), sizeof(isp_dev->name));
else
snprintf(isp_dev->name, sizeof(isp_dev->name),
@@ -978,6 +980,11 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev)
if (isp_dev->hw_dev->is_assigned_clk)
rkisp_clk_dbg = true;
if (isp_dev->hw_dev->unite == ISP_UNITE_ONE &&
!(isp_dev->isp_inp & INP_RAWRD2))
rkisp_rdbk_auto = true;
isp_dev->cap_dev.wait_line = rkisp_wait_line;
isp_dev->cap_dev.wrap_line = rkisp_wrap_line;
isp_dev->is_rdbk_auto = rkisp_rdbk_auto;

48
drivers/media/platform/rockchip/isp/dev.h
View File

@@ -103,6 +103,25 @@ enum rkisp_rdbk_filt {
RDBK_F_MAX
};
/* unite mode for isp to process high resolution
* ISP_UNITE_TWO: image splits left and right to two isp hardware
* ISP_UNITE_ONE: image splits left and right to single isp hardware
*/
enum {
ISP_UNITE_NONE = 0,
ISP_UNITE_TWO = 1,
ISP_UNITE_ONE = 2,
};
/* left and right index
* ISP_UNITE_LEFT: left of image to isp process
* ISP_UNITE_RIGHT: right of image to isp process
*/
enum {
ISP_UNITE_LEFT = 0,
ISP_UNITE_RIGHT = 1,
};
/*
* struct rkisp_pipeline - An ISP hardware pipeline
*
@@ -249,11 +268,40 @@ struct rkisp_device {
bool is_pre_on;
bool is_first_double;
bool is_probe_end;
bool is_frame_double;
struct rkisp_vicap_input vicap_in;
u8 multi_mode;
u8 multi_index;
u8 rawaf_irq_cnt;
u8 unite_index;
};
static inline void
rkisp_unite_write(struct rkisp_device *dev, u32 reg, u32 val, bool is_direct)
{
rkisp_write(dev, reg, val, is_direct);
if (dev->hw_dev->unite)
rkisp_next_write(dev, reg, val, is_direct);
}
static inline void
rkisp_unite_set_bits(struct rkisp_device *dev, u32 reg, u32 mask,
u32 val, bool is_direct)
{
rkisp_set_bits(dev, reg, mask, val, is_direct);
if (dev->hw_dev->unite)
rkisp_next_set_bits(dev, reg, mask, val, is_direct);
}
static inline void
rkisp_unite_clear_bits(struct rkisp_device *dev, u32 reg, u32 mask,
bool is_direct)
{
rkisp_clear_bits(dev, reg, mask, is_direct);
if (dev->hw_dev->unite)
rkisp_next_clear_bits(dev, reg, mask, is_direct);
}
#endif

20
drivers/media/platform/rockchip/isp/dmarx.c
View File

@@ -317,7 +317,6 @@ static struct streams_ops rkisp_dmarx_streams_ops = {
static int rawrd_config_mi(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
bool is_unite = dev->hw_dev->is_unite;
u32 val;
val = rkisp_read(dev, CSI2RX_DATA_IDS_1, true);
@@ -347,8 +346,8 @@ static int rawrd_config_mi(struct rkisp_stream *stream)
val |= CIF_CSI2_DT_RAW12;
}
rkisp_unite_write(dev, CSI2RX_RAW_RD_CTRL,
stream->memory << 2, false, is_unite);
rkisp_unite_write(dev, CSI2RX_DATA_IDS_1, val, false, is_unite);
stream->memory << 2, false);
rkisp_unite_write(dev, CSI2RX_DATA_IDS_1, val, false);
rkisp_rawrd_set_pic_size(dev, stream->out_fmt.width,
stream->out_fmt.height);
mi_raw_length(stream);
@@ -375,7 +374,7 @@ static void update_rawrd(struct rkisp_stream *stream)
}
val += stream->curr_buf->buff_addr[RKISP_PLANE_Y];
rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
if (dev->hw_dev->is_unite) {
if (dev->hw_dev->unite) {
u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
if (stream->memory)
@@ -463,13 +462,10 @@ static int dmarx_frame_end(struct rkisp_stream *stream)
}
dev->hdr.op_mode = dev->rd_mode;
rkisp_unite_write(dev, CSI2RX_CTRL0,
SW_IBUF_OP_MODE(dev->hdr.op_mode),
true, dev->hw_dev->is_unite);
SW_IBUF_OP_MODE(dev->hdr.op_mode), true);
rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT,
0, ISP21_MIPI_DROP_FRM,
true, dev->hw_dev->is_unite);
rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, CIF_ISP_FRAME_IN,
true, dev->hw_dev->is_unite);
0, ISP21_MIPI_DROP_FRM, true);
rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, CIF_ISP_FRAME_IN, true);
dev_info(dev->dev,
"switch online seq:%d mode:0x%x\n",
rx_buf->sequence, dev->rd_mode);
@@ -1134,7 +1130,7 @@ void rkisp_rawrd_set_pic_size(struct rkisp_device *dev,
{
struct rkisp_isp_subdev *sdev = &dev->isp_sdev;
u8 mult = sdev->in_fmt.fmt_type == FMT_YUV ? 2 : 1;
bool is_unite = dev->hw_dev->is_unite;
bool is_unite = !!dev->hw_dev->unite;
u32 w = !is_unite ? width : width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
/* rx height should equal to isp height + offset for read back mode */
@@ -1148,7 +1144,7 @@ void rkisp_rawrd_set_pic_size(struct rkisp_device *dev,
height += RKMODULE_EXTEND_LINE;
w *= mult;
rkisp_unite_write(dev, CSI2RX_RAW_RD_PIC_SIZE, height << 16 | w, false, is_unite);
rkisp_unite_write(dev, CSI2RX_RAW_RD_PIC_SIZE, height << 16 | w, false);
}
void rkisp_dmarx_get_frame(struct rkisp_device *dev, u32 *id,

72
drivers/media/platform/rockchip/isp/hw.c
View File

@@ -132,7 +132,7 @@ static void default_sw_reg_flag(struct rkisp_device *dev)
for (i = 0; i < size; i++) {
flag = dev->sw_base_addr + reg[i] + RKISP_ISP_SW_REG_SIZE;
*flag = SW_REG_CACHE;
if (dev->hw_dev->is_unite) {
if (dev->hw_dev->unite) {
flag += RKISP_ISP_SW_MAX_SIZE / 4;
*flag = SW_REG_CACHE;
}
@@ -144,7 +144,7 @@ static irqreturn_t mipi_irq_hdl(int irq, void *ctx)
struct device *dev = ctx;
struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
struct rkisp_device *isp = hw_dev->isp[hw_dev->mipi_dev_id];
void __iomem *base = !hw_dev->is_unite ?
void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ?
hw_dev->base_addr : hw_dev->base_next_addr;
ktime_t t = 0;
s64 us;
@@ -201,7 +201,7 @@ static irqreturn_t mi_irq_hdl(int irq, void *ctx)
struct device *dev = ctx;
struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id];
void __iomem *base = !hw_dev->is_unite ?
void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ?
hw_dev->base_addr : hw_dev->base_next_addr;
u32 mis_val, tx_isr = MI_RAW0_WR_FRAME | MI_RAW1_WR_FRAME |
MI_RAW2_WR_FRAME | MI_RAW3_WR_FRAME;
@@ -237,7 +237,7 @@ static irqreturn_t isp_irq_hdl(int irq, void *ctx)
struct device *dev = ctx;
struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
struct rkisp_device *isp = hw_dev->isp[hw_dev->cur_dev_id];
void __iomem *base = !hw_dev->is_unite ?
void __iomem *base = hw_dev->unite != ISP_UNITE_TWO ?
hw_dev->base_addr : hw_dev->base_next_addr;
unsigned int mis_val, mis_3a = 0;
ktime_t t = 0;
@@ -409,6 +409,9 @@ static const struct isp_clk_info rv1106_isp_clk_rate[] = {
}, {
.clk_rate = 350,
.refer_data = 3072,
}, {
.clk_rate = 440,
.refer_data = 3840,
}
};
@@ -590,7 +593,7 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
/* record clk config and recover */
iccl0 = readl(base + CIF_ICCL);
clk_ctrl0 = readl(base + CTRL_VI_ISP_CLK_CTRL);
if (dev->is_unite) {
if (dev->unite == ISP_UNITE_TWO) {
iccl1 = readl(dev->base_next_addr + CIF_ICCL);
clk_ctrl1 = readl(dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
}
@@ -600,7 +603,7 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
* isp soft reset first to protect isp reset.
*/
writel(0xffff, base + CIF_IRCL);
if (dev->is_unite)
if (dev->unite == ISP_UNITE_TWO)
writel(0xffff, dev->base_next_addr + CIF_IRCL);
udelay(10);
}
@@ -623,7 +626,7 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
writel(val, base + CIF_IRCL);
if (dev->isp_ver == ISP_V32)
rv1106_sdmmc_put_lock();
if (dev->is_unite)
if (dev->unite == ISP_UNITE_TWO)
writel(0xffff, dev->base_next_addr + CIF_IRCL);
udelay(10);
@@ -635,7 +638,7 @@ void rkisp_soft_reset(struct rkisp_hw_dev *dev, bool is_secure)
writel(iccl0, base + CIF_ICCL);
writel(clk_ctrl0, base + CTRL_VI_ISP_CLK_CTRL);
if (dev->is_unite) {
if (dev->unite == ISP_UNITE_TWO) {
writel(iccl1, dev->base_next_addr + CIF_ICCL);
writel(clk_ctrl1, dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
}
@@ -676,7 +679,7 @@ static void isp_config_clk(struct rkisp_hw_dev *dev, int on)
writel(val, dev->base_addr + CIF_ICCL);
if (dev->isp_ver == ISP_V32)
rv1106_sdmmc_put_lock();
if (dev->is_unite)
if (dev->unite == ISP_UNITE_TWO)
writel(val, dev->base_next_addr + CIF_ICCL);
if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
@@ -706,7 +709,7 @@ static void isp_config_clk(struct rkisp_hw_dev *dev, int on)
writel(val, dev->base_addr + CTRL_VI_ISP_CLK_CTRL);
if (dev->isp_ver == ISP_V32)
rv1106_sdmmc_put_lock();
if (dev->is_unite)
if (dev->unite == ISP_UNITE_TWO)
writel(val, dev->base_next_addr + CTRL_VI_ISP_CLK_CTRL);
}
}
@@ -743,7 +746,7 @@ static int enable_sys_clk(struct rkisp_hw_dev *dev)
if (!dev->is_assigned_clk) {
rate = dev->clk_rate_tbl[0].clk_rate * 1000000UL;
rkisp_set_clk_rate(dev->clks[0], rate);
if (dev->is_unite)
if (dev->unite == ISP_UNITE_TWO)
rkisp_set_clk_rate(dev->clks[5], rate);
}
rkisp_soft_reset(dev, false);
@@ -815,21 +818,11 @@ static int rkisp_hw_probe(struct platform_device *pdev)
return -ENOMEM;
match_data = match->data;
hw_dev->is_unite = match_data->unite;
dev_set_drvdata(dev, hw_dev);
hw_dev->dev = dev;
hw_dev->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
dev_info(dev, "is_thunderboot: %d\n", hw_dev->is_thunderboot);
memset(&hw_dev->max_in, 0, sizeof(hw_dev->max_in));
if (!of_property_read_u32_array(node, "max-input", &hw_dev->max_in.w, 3)) {
hw_dev->max_in.is_fix = true;
if (hw_dev->is_unite) {
hw_dev->max_in.w /= 2;
hw_dev->max_in.w += RKMOUDLE_UNITE_EXTEND_PIXEL;
}
}
dev_info(dev, "max input:%dx%d@%dfps\n",
hw_dev->max_in.w, hw_dev->max_in.h, hw_dev->max_in.fps);
hw_dev->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
if (IS_ERR(hw_dev->grf))
dev_warn(dev, "Missing rockchip,grf property\n");
@@ -876,6 +869,27 @@ static int rkisp_hw_probe(struct platform_device *pdev)
}
}
hw_dev->isp_ver = match_data->isp_ver;
if (match_data->unite) {
hw_dev->unite = ISP_UNITE_TWO;
} else if (device_property_read_bool(dev, "rockchip,unite-en")) {
hw_dev->unite = ISP_UNITE_ONE;
hw_dev->base_next_addr = hw_dev->base_addr;
} else {
hw_dev->unite = ISP_UNITE_NONE;
}
memset(&hw_dev->max_in, 0, sizeof(hw_dev->max_in));
if (!of_property_read_u32_array(node, "max-input", &hw_dev->max_in.w, 3)) {
hw_dev->max_in.is_fix = true;
if (hw_dev->unite) {
hw_dev->max_in.w /= 2;
hw_dev->max_in.w += RKMOUDLE_UNITE_EXTEND_PIXEL;
}
}
dev_info(dev, "max input:%dx%d@%dfps\n",
hw_dev->max_in.w, hw_dev->max_in.h, hw_dev->max_in.fps);
rkisp_monitor = device_property_read_bool(dev, "rockchip,restart-monitor-en");
hw_dev->mipi_irq = -1;
@@ -921,10 +935,8 @@ static int rkisp_hw_probe(struct platform_device *pdev)
hw_dev->dev_link_num = 0;
hw_dev->cur_dev_id = 0;
hw_dev->mipi_dev_id = 0;
hw_dev->pre_dev_id = 0;
hw_dev->pre_dev_id = -1;
hw_dev->is_multi_overflow = false;
hw_dev->isp_ver = match_data->isp_ver;
hw_dev->is_unite = match_data->unite;
mutex_init(&hw_dev->dev_lock);
spin_lock_init(&hw_dev->rdbk_lock);
atomic_set(&hw_dev->refcnt, 0);
@@ -974,7 +986,7 @@ static void rkisp_hw_shutdown(struct platform_device *pdev)
hw_dev->is_shutdown = true;
if (pm_runtime_active(&pdev->dev)) {
writel(0xffff, hw_dev->base_addr + CIF_IRCL);
if (hw_dev->is_unite)
if (hw_dev->unite == ISP_UNITE_TWO)
writel(0xffff, hw_dev->base_next_addr + CIF_IRCL);
}
dev_info(&pdev->dev, "%s\n", __func__);
@@ -1014,7 +1026,7 @@ void rkisp_hw_enum_isp_size(struct rkisp_hw_dev *hw_dev)
hw_dev->is_single = false;
w = isp->isp_sdev.in_crop.width;
h = isp->isp_sdev.in_crop.height;
if (hw_dev->is_unite)
if (hw_dev->unite)
w = w / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
hw_dev->isp_size[i].w = w;
hw_dev->isp_size[i].h = h;
@@ -1026,6 +1038,8 @@ void rkisp_hw_enum_isp_size(struct rkisp_hw_dev *hw_dev)
hw_dev->max_in.h = h;
}
}
if (hw_dev->unite == ISP_UNITE_ONE)
hw_dev->is_single = false;
for (i = 0; i < hw_dev->dev_num; i++) {
isp = hw_dev->isp[i];
if (!isp || (isp && !isp->is_hw_link))
@@ -1039,7 +1053,7 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev)
struct rkisp_hw_dev *hw_dev = dev_get_drvdata(dev);
void __iomem *base = hw_dev->base_addr;
struct rkisp_device *isp;
int mult = hw_dev->is_unite ? 2 : 1;
int mult = hw_dev->unite ? 2 : 1;
int ret, i;
void *buf;
@@ -1055,7 +1069,7 @@ static int __maybe_unused rkisp_runtime_resume(struct device *dev)
buf = isp->sw_base_addr;
memset(buf, 0, RKISP_ISP_SW_MAX_SIZE * mult);
memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);
if (hw_dev->is_unite) {
if (hw_dev->unite) {
buf += RKISP_ISP_SW_MAX_SIZE;
base = hw_dev->base_next_addr;
memcpy_fromio(buf, base, RKISP_ISP_SW_REG_SIZE);

2
drivers/media/platform/rockchip/isp/hw.h
View File

@@ -89,6 +89,7 @@ struct rkisp_hw_dev {
struct rkisp_monitor monitor;
u64 iq_feature;
int buf_init_cnt;
u32 unite;
bool is_feature_on;
bool is_dma_contig;
bool is_dma_sg_ops;
@@ -99,7 +100,6 @@ struct rkisp_hw_dev {
bool is_thunderboot;
bool is_buf_init;
bool is_shutdown;
bool is_unite;
bool is_multi_overflow;
bool is_runing;
bool is_frm_buf;

28
drivers/media/platform/rockchip/isp/isp_params.c
View File

@@ -146,11 +146,12 @@ static void rkisp_params_vb2_buf_queue(struct vb2_buffer *vb)
struct rkisp_buffer *params_buf = to_rkisp_buffer(vbuf);
struct vb2_queue *vq = vb->vb2_queue;
struct rkisp_isp_params_vdev *params_vdev = vq->drv_priv;
struct rkisp_device *dev = params_vdev->dev;
void *first_param;
unsigned long flags;
unsigned int cur_frame_id = -1;
cur_frame_id = atomic_read(&params_vdev->dev->isp_sdev.frm_sync_seq) - 1;
cur_frame_id = atomic_read(&dev->isp_sdev.frm_sync_seq) - 1;
if (params_vdev->first_params) {
first_param = vb2_plane_vaddr(vb, 0);
params_vdev->ops->save_first_param(params_vdev, first_param);
@@ -159,16 +160,22 @@ static void rkisp_params_vb2_buf_queue(struct vb2_buffer *vb)
vb2_buffer_done(&params_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
params_vdev->first_params = false;
wake_up(&params_vdev->dev->sync_onoff);
if (params_vdev->dev->is_first_double) {
dev_info(params_vdev->dev->dev, "first params for fast\n");
params_vdev->dev->is_first_double = false;
rkisp_trigger_read_back(params_vdev->dev, false, false, false);
if (dev->is_first_double) {
dev_info(dev->dev, "first params for fast\n");
dev->is_first_double = false;
dev->sw_rd_cnt = 0;
if (dev->hw_dev->unite == ISP_UNITE_ONE) {
dev->unite_index = ISP_UNITE_LEFT;
dev->sw_rd_cnt += dev->hw_dev->is_multi_overflow ? 3 : 1;
}
params_vdev->rdbk_times = dev->sw_rd_cnt + 1;
rkisp_trigger_read_back(dev, false, false, false);
}
dev_info(params_vdev->dev->dev, "first params buf queue\n");
dev_info(dev->dev, "first params buf queue\n");
return;
}
if (params_vdev->dev->procfs.mode &
if (dev->procfs.mode &
(RKISP_PROCFS_FIL_AIQ | RKISP_PROCFS_FIL_SW)) {
vb2_buffer_done(&params_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
return;
@@ -208,9 +215,7 @@ static void rkisp_params_vb2_stop_streaming(struct vb2_queue *vq)
break;
}
if (buf)
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
buf = NULL;
vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
}
if (params_vdev->cur_buf) {
@@ -406,8 +411,7 @@ void rkisp_params_first_cfg(struct rkisp_isp_params_vdev *params_vdev,
stream->out_isp_fmt.fmt_type == FMT_RGB)
rkisp_unite_set_bits(dev, ISP3X_MI_WR_CTRL, mask,
quantization == V4L2_QUANTIZATION_FULL_RANGE ?
mask : 0,
false, dev->hw_dev->is_unite);
mask : 0, false);
dev->isp_sdev.quantization = quantization;
}
}

2331
drivers/media/platform/rockchip/isp/isp_params_v32.c
View File

File diff suppressed because it is too large Load Diff

158
drivers/media/platform/rockchip/isp/isp_params_v32.h
View File

@@ -29,169 +29,171 @@
struct rkisp_isp_params_vdev;
struct rkisp_isp_params_ops_v32 {
void (*dpcc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_dpcc_cfg *arg);
const struct isp2x_dpcc_cfg *arg, u32 id);
void (*dpcc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*bls_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_bls_cfg *arg);
const struct isp32_bls_cfg *arg, u32 id);
void (*bls_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*sdg_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_sdg_cfg *arg);
const struct isp2x_sdg_cfg *arg, u32 id);
void (*sdg_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*lsc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_lsc_cfg *arg);
const struct isp3x_lsc_cfg *arg, u32 id);
void (*lsc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*awbgain_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_awb_gain_cfg *arg);
const struct isp32_awb_gain_cfg *arg, u32 id);
void (*awbgain_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*debayer_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_debayer_cfg *arg);
const struct isp32_debayer_cfg *arg, u32 id);
void (*debayer_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*ccm_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_ccm_cfg *arg);
const struct isp32_ccm_cfg *arg, u32 id);
void (*ccm_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*goc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_gammaout_cfg *arg);
const struct isp3x_gammaout_cfg *arg, u32 id);
void (*goc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*cproc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_cproc_cfg *arg);
const struct isp2x_cproc_cfg *arg, u32 id);
void (*cproc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*ie_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_ie_cfg *arg);
const struct isp2x_ie_cfg *arg, u32 id);
void (*ie_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*rawaf_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_rawaf_meas_cfg *arg);
const struct isp32_rawaf_meas_cfg *arg, u32 id);
void (*rawaf_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*rawae0_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawaelite_meas_cfg *arg);
const struct isp2x_rawaelite_meas_cfg *arg, u32 id);
void (*rawae0_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*rawae1_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawaebig_meas_cfg *arg);
const struct isp2x_rawaebig_meas_cfg *arg, u32 id);
void (*rawae1_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*rawae2_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawaebig_meas_cfg *arg);
const struct isp2x_rawaebig_meas_cfg *arg, u32 id);
void (*rawae2_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*rawae3_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawaebig_meas_cfg *arg);
const struct isp2x_rawaebig_meas_cfg *arg, u32 id);
void (*rawae3_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*rawawb_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_rawawb_meas_cfg *arg);
const struct isp32_rawawb_meas_cfg *arg, u32 id);
void (*rawawb_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*rawhst0_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawhistlite_cfg *arg);
const struct isp2x_rawhistlite_cfg *arg, u32 id);
void (*rawhst0_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*rawhst1_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawhistbig_cfg *arg);
const struct isp2x_rawhistbig_cfg *arg, u32 id);
void (*rawhst1_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*rawhst2_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawhistbig_cfg *arg);
const struct isp2x_rawhistbig_cfg *arg, u32 id);
void (*rawhst2_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*rawhst3_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_rawhistbig_cfg *arg);
const struct isp2x_rawhistbig_cfg *arg, u32 id);
void (*rawhst3_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*hdrdrc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_drc_cfg *arg,
enum rkisp_params_type type);
enum rkisp_params_type type, u32 id);
void (*hdrdrc_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*hdrmge_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_hdrmge_cfg *arg,
enum rkisp_params_type type);
enum rkisp_params_type type, u32 id);
void (*hdrmge_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*gic_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp21_gic_cfg *arg);
const struct isp21_gic_cfg *arg, u32 id);
void (*gic_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*dhaz_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_dhaz_cfg *arg);
const struct isp32_dhaz_cfg *arg, u32 id);
void (*dhaz_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*isp3dlut_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp2x_3dlut_cfg *arg);
const struct isp2x_3dlut_cfg *arg, u32 id);
void (*isp3dlut_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*ldch_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_ldch_cfg *arg);
const struct isp32_ldch_cfg *arg, u32 id);
void (*ldch_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*ynr_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_ynr_cfg *arg);
const struct isp32_ynr_cfg *arg, u32 id);
void (*ynr_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*cnr_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_cnr_cfg *arg);
const struct isp32_cnr_cfg *arg, u32 id);
void (*cnr_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*sharp_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_sharp_cfg *arg);
const struct isp32_sharp_cfg *arg, u32 id);
void (*sharp_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*baynr_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_baynr_cfg *arg);
const struct isp32_baynr_cfg *arg, u32 id);
void (*baynr_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*bay3d_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_bay3d_cfg *arg);
const struct isp32_bay3d_cfg *arg, u32 id);
void (*bay3d_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*gain_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp3x_gain_cfg *arg);
const struct isp3x_gain_cfg *arg, u32 id);
void (*gain_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*cac_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_cac_cfg *arg);
const struct isp32_cac_cfg *arg, u32 id);
void (*cac_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
void (*csm_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp21_csm_cfg *arg);
const struct isp21_csm_cfg *arg, u32 id);
void (*cgc_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp21_cgc_cfg *arg);
const struct isp21_cgc_cfg *arg, u32 id);
void (*vsm_config)(struct rkisp_isp_params_vdev *params_vdev,
const struct isp32_vsm_cfg *arg);
const struct isp32_vsm_cfg *arg, u32 id);
void (*vsm_enable)(struct rkisp_isp_params_vdev *params_vdev,
bool en);
bool en, u32 id);
};
struct rkisp_isp_params_val_v32 {
struct tasklet_struct lsc_tasklet;
struct rkisp_dummy_buffer buf_3dlut[ISP32_3DLUT_BUF_NUM];
u32 buf_3dlut_idx;
struct rkisp_dummy_buffer buf_3dlut[ISP3_UNITE_MAX][ISP32_3DLUT_BUF_NUM];
u32 buf_3dlut_idx[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_ldch[ISP3_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_ldch_idx[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_cac[ISP3_UNITE_MAX][ISP3X_MESH_BUF_NUM];
u32 buf_cac_idx[ISP3_UNITE_MAX];
struct rkisp_dummy_buffer buf_lsclut[ISP32_LSC_LUT_BUF_NUM];
u32 buf_lsclut_idx;
struct rkisp_dummy_buffer buf_ldch[ISP3X_MESH_BUF_NUM];
u32 buf_ldch_idx;
struct rkisp_dummy_buffer buf_cac[ISP3X_MESH_BUF_NUM];
u32 buf_cac_idx;
struct rkisp_dummy_buffer buf_info[RKISP_INFO2DDR_BUF_MAX];
u32 buf_info_owner;
u32 buf_info_cnt;
int buf_info_idx;
u32 bay3d_ds_size;
u32 bay3d_iir_size;
u32 bay3d_cur_size;
u32 bay3d_cur_wsize;
u32 bay3d_cur_wrap_line;

54
drivers/media/platform/rockchip/isp/isp_params_v3x.c
View File

@@ -591,7 +591,7 @@ isp_lsc_cfg_sram_task(unsigned long data)
struct isp3x_isp_params_cfg *params = params_vdev->isp3x_params;
isp_lsc_matrix_cfg_sram(params_vdev, &params->others.lsc_cfg, true, 0);
if (params_vdev->dev->hw_dev->is_unite) {
if (params_vdev->dev->hw_dev->unite) {
params++;
isp_lsc_matrix_cfg_sram(params_vdev, &params->others.lsc_cfg, true, 1);
}
@@ -1223,7 +1223,7 @@ isp_rawaelite_config(struct rkisp_isp_params_vdev *params_vdev,
block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
if (ispdev->hw_dev->is_unite)
if (ispdev->hw_dev->unite)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (value + 1 > width)
block_hsize -= 1;
@@ -1310,7 +1310,7 @@ isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev,
block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
if (ispdev->hw_dev->is_unite)
if (ispdev->hw_dev->unite)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
if (value + 1 > width)
block_hsize -= 1;
@@ -2887,7 +2887,7 @@ isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev,
value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], 0);
isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4, id);
if (dev->hw_dev->is_unite &&
if (dev->hw_dev->unite &&
dev->hw_dev->is_single &&
ctrl & ISP3X_DHAZ_ENMUX)
ctrl |= ISP3X_SELF_FORCE_UPD;
@@ -4105,7 +4105,7 @@ void rkisp_params_cfgsram_v3x(struct rkisp_isp_params_vdev *params_vdev)
isp_rawhstbig_cfg_sram(params_vdev, &params->meas.rawhist2, 2, true, 0);
isp_rawhstbig_cfg_sram(params_vdev, &params->meas.rawhist3, 0, true, 0);
isp_rawawb_cfg_sram(params_vdev, &params->meas.rawawb, true, 0);
if (params_vdev->dev->hw_dev->is_unite) {
if (params_vdev->dev->hw_dev->unite) {
params++;
isp_lsc_matrix_cfg_sram(params_vdev, &params->others.lsc_cfg, true, 1);
isp_rawhstbig_cfg_sram(params_vdev, &params->meas.rawhist1, 1, true, 1);
@@ -4129,7 +4129,7 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
module_en_update = new_params->module_en_update;
module_ens = new_params->module_ens;
for (id = 0; id <= ispdev->hw_dev->is_unite; id++) {
for (id = 0; id <= !!ispdev->hw_dev->unite; id++) {
priv_val->buf_3dlut_idx[id] = 0;
for (i = 0; i < ISP3X_3DLUT_BUF_NUM; i++) {
priv_val->buf_3dlut[id][i].is_need_vaddr = true;
@@ -4146,10 +4146,10 @@ rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
(module_ens & ISP3X_MODULE_BAY3D)) {
w = ALIGN(isp_sdev->in_crop.width, 16);
h = ALIGN(isp_sdev->in_crop.height, 16);
if (ispdev->hw_dev->is_unite)
if (ispdev->hw_dev->unite)
w = ALIGN(isp_sdev->in_crop.width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL, 16);
for (id = 0; id <= ispdev->hw_dev->is_unite; id++) {
for (id = 0; id <= !!ispdev->hw_dev->unite; id++) {
size = ALIGN((w + w / 8) * h * 2, 16);
priv_val->buf_3dnr_iir[id].size = size;
@@ -4185,7 +4185,7 @@ err_3dnr:
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds[id]);
}
id = ispdev->hw_dev->is_unite ? 1 : 0;
id = ispdev->hw_dev->unite ? 1 : 0;
i = ISP3X_3DLUT_BUF_NUM;
err_3dlut:
for (; id >= 0; id--) {
@@ -4240,7 +4240,7 @@ multi_overflow:
continue;
dev_warn(dev, "isp%d %dx%d over four vir isp max:%dx1536\n",
i, hw->isp_size[i].w, hw->isp_size[i].h,
hw->is_unite ? (2560 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 2560);
hw->unite ? (2560 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 2560);
hw->is_multi_overflow = true;
goto multi_overflow;
}
@@ -4282,7 +4282,7 @@ multi_overflow:
(hw->isp_size[idx1[0]].size > ISP3X_VIR2_MAX_SIZE)) {
dev_warn(dev, "isp%d %dx%d over three vir isp max:%dx1536\n",
idx1[0], hw->isp_size[idx1[0]].w, hw->isp_size[idx1[0]].h,
hw->is_unite ? (2560 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 2560);
hw->unite ? (2560 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 2560);
hw->is_multi_overflow = true;
goto multi_overflow;
} else {
@@ -4341,7 +4341,7 @@ multi_overflow:
hw->isp_size[idx1[k - 1]].size > (ISP3X_VIR4_MAX_SIZE + ISP3X_VIR2_MAX_SIZE)) {
dev_warn(dev, "isp%d %dx%d over two vir isp max:%dx2160\n",
idx1[k - 1], hw->isp_size[idx1[k - 1]].w, hw->isp_size[idx1[k - 1]].h,
hw->is_unite ? (3840 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 3840);
hw->unite ? (3840 - RKMOUDLE_UNITE_EXTEND_PIXEL) * 2 : 3840);
hw->is_multi_overflow = true;
goto multi_overflow;
} else {
@@ -4363,7 +4363,7 @@ multi_overflow:
ispdev->multi_mode = 0;
ispdev->multi_index = 0;
width = crop->width;
if (hw->is_unite)
if (hw->unite)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
height = crop->height;
size = width * height;
@@ -4400,7 +4400,7 @@ rkisp_params_first_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev)
priv_val->lsc_en = 0;
priv_val->mge_en = 0;
priv_val->lut3d_en = 0;
if (hw->is_unite) {
if (hw->unite) {
if (dev->is_bigmode)
rkisp_next_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0,
ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
@@ -4431,7 +4431,7 @@ static void rkisp_save_first_param_v3x(struct rkisp_isp_params_vdev *params_vdev
static void rkisp_clear_first_param_v3x(struct rkisp_isp_params_vdev *params_vdev)
{
u32 mult = params_vdev->dev->hw_dev->is_unite ? ISP3_UNITE_MAX : 1;
u32 mult = params_vdev->dev->hw_dev->unite ? ISP3_UNITE_MAX : 1;
u32 size = sizeof(struct isp3x_isp_params_cfg) * mult;
memset(params_vdev->isp3x_params, 0, size);
@@ -4530,7 +4530,7 @@ static void
rkisp_get_param_size_v3x(struct rkisp_isp_params_vdev *params_vdev,
unsigned int sizes[])
{
u32 mult = params_vdev->dev->hw_dev->is_unite ? ISP3_UNITE_MAX : 1;
u32 mult = params_vdev->dev->hw_dev->unite ? ISP3_UNITE_MAX : 1;
sizes[0] = sizeof(struct isp3x_isp_params_cfg) * mult;
}
@@ -4575,7 +4575,7 @@ rkisp_params_set_meshbuf_size_v3x(struct rkisp_isp_params_vdev *params_vdev,
{
struct rkisp_meshbuf_size *meshsize = size;
if (!params_vdev->dev->hw_dev->is_unite)
if (!params_vdev->dev->hw_dev->unite)
meshsize->unite_isp_id = 0;
rkisp_deinit_mesh_buf(params_vdev, meshsize->module_id, meshsize->unite_isp_id);
return rkisp_init_mesh_buf(params_vdev, meshsize);
@@ -4587,7 +4587,7 @@ rkisp_params_free_meshbuf_v3x(struct rkisp_isp_params_vdev *params_vdev,
{
int id;
for (id = 0; id <= params_vdev->dev->hw_dev->is_unite; id++)
for (id = 0; id <= !!params_vdev->dev->hw_dev->unite; id++)
rkisp_deinit_mesh_buf(params_vdev, module_id, id);
}
@@ -4600,7 +4600,7 @@ rkisp_params_stream_stop_v3x(struct rkisp_isp_params_vdev *params_vdev)
priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
tasklet_disable(&priv_val->lsc_tasklet);
for (id = 0; id <= ispdev->hw_dev->is_unite; id++) {
for (id = 0; id <= !!ispdev->hw_dev->unite; id++) {
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds[id]);
@@ -4616,7 +4616,7 @@ rkisp_params_fop_release_v3x(struct rkisp_isp_params_vdev *params_vdev)
{
int id;
for (id = 0; id <= params_vdev->dev->hw_dev->is_unite; id++) {
for (id = 0; id <= !!params_vdev->dev->hw_dev->unite; id++) {
rkisp_deinit_mesh_buf(params_vdev, ISP3X_MODULE_LDCH, id);
rkisp_deinit_mesh_buf(params_vdev, ISP3X_MODULE_CAC, id);
}
@@ -4631,7 +4631,7 @@ rkisp_params_disable_isp_v3x(struct rkisp_isp_params_vdev *params_vdev)
__isp_isr_other_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
__isp_isr_meas_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
if (params_vdev->dev->hw_dev->is_unite) {
if (params_vdev->dev->hw_dev->unite) {
__isp_isr_other_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 1);
__isp_isr_meas_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 1);
}
@@ -4704,7 +4704,7 @@ rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev,
__isp_isr_other_en(params_vdev, new_params, type, 0);
__isp_isr_meas_en(params_vdev, new_params, type, 0);
new_params->module_cfg_update = 0;
if (hw_dev->is_unite) {
if (hw_dev->unite) {
struct isp3x_isp_params_cfg *params = new_params + 1;
__isp_isr_meas_config(params_vdev, params, type, 1);
@@ -4717,7 +4717,7 @@ rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev,
if (new_params->module_cfg_update &
(ISP3X_MODULE_LDCH | ISP3X_MODULE_CAC)) {
module_data_abandon(params_vdev, new_params, 0);
if (hw_dev->is_unite)
if (hw_dev->unite)
module_data_abandon(params_vdev, new_params, 1);
}
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
@@ -4735,7 +4735,7 @@ rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev,
goto unlock;
new_params = (struct isp3x_isp_params_cfg *)(cur_buf->vaddr[0]);
if (hw_dev->is_unite) {
if (hw_dev->unite) {
__isp_isr_meas_config(params_vdev, new_params + 1, type, 1);
__isp_isr_other_config(params_vdev, new_params + 1, type, 1);
__isp_isr_other_en(params_vdev, new_params + 1, type, 1);
@@ -4748,7 +4748,7 @@ rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev,
if (type != RKISP_PARAMS_IMD) {
new_params->module_cfg_update = 0;
if (hw_dev->is_unite)
if (hw_dev->unite)
(new_params++)->module_cfg_update = 0;
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
cur_buf = NULL;
@@ -4782,7 +4782,7 @@ rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev *params_vdev)
if (value & ISP3X_RAW3D_FST_FRAME)
rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
ISP3X_RAW3D_FST_FRAME, false);
if (hw_dev->is_unite) {
if (hw_dev->unite) {
value = rkisp_next_read(dev, ISP3X_ISP_CTRL1, false);
if (value & ISP3X_YNR_FST_FRAME)
rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
@@ -4857,7 +4857,7 @@ int rkisp_init_params_vdev_v3x(struct rkisp_isp_params_vdev *params_vdev)
return -ENOMEM;
size = sizeof(struct isp3x_isp_params_cfg);
if (ispdev->hw_dev->is_unite)
if (ispdev->hw_dev->unite)
size *= 2;
params_vdev->isp3x_params = vmalloc(size);
if (!params_vdev->isp3x_params) {

195
drivers/media/platform/rockchip/isp/isp_stats_v32.c
View File

@@ -428,6 +428,8 @@ rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev)
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_buffer *buf;
unsigned long flags;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
u32 val = 0;
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!stats_vdev->nxt_buf && !list_empty(&stats_vdev->stat)) {
@@ -439,18 +441,23 @@ rkisp_stats_update_buf(struct rkisp_isp_stats_vdev *stats_vdev)
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
if (stats_vdev->nxt_buf) {
rkisp_write(dev, ISP3X_MI_3A_WR_BASE, stats_vdev->nxt_buf->buff_addr[0], false);
val = stats_vdev->nxt_buf->buff_addr[0];
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"%s BASE:0x%x SHD:0x%x\n",
__func__, stats_vdev->nxt_buf->buff_addr[0],
__func__, val,
isp3_stats_read(stats_vdev, ISP3X_MI_3A_WR_BASE));
if (!dev->hw_dev->is_single) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
} else if (stats_vdev->stats_buf[0].mem_priv) {
rkisp_write(dev, ISP3X_MI_3A_WR_BASE,
stats_vdev->stats_buf[0].dma_addr, false);
val = stats_vdev->stats_buf[0].dma_addr;
}
if (val) {
rkisp_write(dev, ISP3X_MI_3A_WR_BASE, val, false);
if (dev->hw_dev->unite)
rkisp_next_write(dev, ISP3X_MI_3A_WR_BASE, val + size / 2, false);
}
}
@@ -533,14 +540,15 @@ static void
rkisp_stats_send_meas(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_isp_readout_work *meas_work)
{
unsigned int cur_frame_id = -1;
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
struct rkisp_buffer *cur_buf = stats_vdev->cur_buf;
struct rkisp32_isp_stat_buffer *cur_stat_buf = NULL;
struct rkisp_stats_ops_v32 *ops =
(struct rkisp_stats_ops_v32 *)stats_vdev->priv_ops;
struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev;
u32 size = sizeof(struct rkisp32_isp_stat_buffer);
int ret = 0;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
u32 cur_frame_id = meas_work->frame_id;
bool is_dummy = false;
unsigned long flags;
@@ -548,97 +556,107 @@ rkisp_stats_send_meas(struct rkisp_isp_stats_vdev *stats_vdev,
if (!cur_buf && stats_vdev->stats_buf[0].mem_priv) {
rkisp_finish_buffer(stats_vdev->dev, &stats_vdev->stats_buf[0]);
cur_stat_buf = stats_vdev->stats_buf[0].vaddr;
cur_stat_buf->frame_id = -1;
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
is_dummy = true;
} else if (cur_buf) {
cur_stat_buf = cur_buf->vaddr[0];
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
}
/* config buf for next frame */
stats_vdev->cur_buf = NULL;
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
rkisp_stats_update_buf(stats_vdev);
cur_frame_id = meas_work->frame_id;
/* buffer done when frame of right handle */
if (hw->unite == ISP_UNITE_ONE) {
if (dev->unite_index == ISP_UNITE_LEFT) {
cur_buf = NULL;
is_dummy = false;
} else if (cur_stat_buf) {
cur_stat_buf = (void *)cur_stat_buf + size / 2;
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
}
}
if (hw->unite != ISP_UNITE_ONE || dev->unite_index == ISP_UNITE_RIGHT) {
/* config buf for next frame */
stats_vdev->cur_buf = NULL;
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
}
rkisp_stats_update_buf(stats_vdev);
}
} else {
cur_buf = NULL;
}
if (meas_work->isp3a_ris & ISP3X_3A_RAWAWB)
ret |= ops->get_rawawb_meas(stats_vdev, cur_stat_buf);
ops->get_rawawb_meas(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWAF ||
stats_vdev->af_meas_done_next)
ret |= ops->get_rawaf_meas(stats_vdev, cur_stat_buf);
ops->get_rawaf_meas(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_BIG ||
stats_vdev->ae_meas_done_next)
ret |= ops->get_rawae3_meas(stats_vdev, cur_stat_buf);
ops->get_rawae3_meas(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_BIG)
ret |= ops->get_rawhst3_meas(stats_vdev, cur_stat_buf);
ops->get_rawhst3_meas(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH0)
ret |= ops->get_rawae0_meas(stats_vdev, cur_stat_buf);
ops->get_rawae0_meas(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH1)
ret |= ops->get_rawae1_meas(stats_vdev, cur_stat_buf);
ops->get_rawae1_meas(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH2)
ret |= ops->get_rawae2_meas(stats_vdev, cur_stat_buf);
ops->get_rawae2_meas(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH0)
ret |= ops->get_rawhst0_meas(stats_vdev, cur_stat_buf);
ops->get_rawhst0_meas(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH1)
ret |= ops->get_rawhst1_meas(stats_vdev, cur_stat_buf);
ops->get_rawhst1_meas(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH2)
ret |= ops->get_rawhst2_meas(stats_vdev, cur_stat_buf);
ops->get_rawhst2_meas(stats_vdev, cur_stat_buf);
if (meas_work->isp_ris & ISP3X_FRAME) {
ret |= ops->get_bls_stats(stats_vdev, cur_stat_buf);
ret |= ops->get_dhaz_stats(stats_vdev, cur_stat_buf);
ret |= ops->get_vsm_stats(stats_vdev, cur_stat_buf);
ops->get_bls_stats(stats_vdev, cur_stat_buf);
ops->get_dhaz_stats(stats_vdev, cur_stat_buf);
ops->get_vsm_stats(stats_vdev, cur_stat_buf);
}
if (ret || (cur_stat_buf && !cur_stat_buf->meas_type)) {
if (is_dummy) {
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!list_empty(&stats_vdev->stat)) {
cur_buf = list_first_entry(&stats_vdev->stat, struct rkisp_buffer, queue);
list_del(&cur_buf->queue);
}
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
if (cur_buf) {
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
list_add_tail(&cur_buf->queue, &stats_vdev->stat);
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
}
} else {
if (is_dummy) {
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
if (!list_empty(&stats_vdev->stat)) {
cur_buf = list_first_entry(&stats_vdev->stat, struct rkisp_buffer, queue);
list_del(&cur_buf->queue);
} else {
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
}
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
if (cur_buf) {
memcpy(cur_buf->vaddr[0], cur_stat_buf, size);
cur_stat_buf = cur_buf->vaddr[0];
}
}
if (cur_buf && cur_stat_buf) {
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
cur_stat_buf->params.info2ddr.buf_fd = -1;
cur_stat_buf->params.info2ddr.owner = 0;
rkisp_stats_info2ddr(stats_vdev, cur_stat_buf);
vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size);
cur_buf->vb.sequence = cur_frame_id;
cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp;
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
memcpy(cur_buf->vaddr[0], stats_vdev->stats_buf[0].vaddr, size);
cur_stat_buf = cur_buf->vaddr[0];
}
}
if (cur_buf && cur_stat_buf) {
cur_stat_buf->frame_id = cur_frame_id;
cur_stat_buf->params_id = params_vdev->cur_frame_id;
cur_stat_buf->params.info2ddr.buf_fd = -1;
cur_stat_buf->params.info2ddr.owner = 0;
rkisp_stats_info2ddr(stats_vdev, cur_stat_buf);
vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size);
cur_buf->vb.sequence = cur_frame_id;
cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp;
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev,
"%s id:%d seq:%d params_id:%d ris:0x%x buf:%p meas_type:0x%x\n",
__func__, dev->unite_index,
cur_frame_id, params_vdev->cur_frame_id, meas_work->isp3a_ris,
cur_buf, !cur_stat_buf ? 0 : cur_stat_buf->meas_type);
}
static int
@@ -890,12 +908,12 @@ static void
rkisp_stats_send_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev,
struct rkisp_isp_readout_work *meas_work)
{
struct rkisp_isp_params_vdev *params_vdev = &stats_vdev->dev->params_vdev;
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
unsigned int cur_frame_id = meas_work->frame_id;
struct rkisp_buffer *cur_buf = NULL;
struct rkisp32_lite_stat_buffer *cur_stat_buf = NULL;
u32 size = sizeof(struct rkisp32_lite_stat_buffer);
int ret = 0;
spin_lock(&stats_vdev->rd_lock);
if (!list_empty(&stats_vdev->stat)) {
@@ -913,45 +931,42 @@ rkisp_stats_send_meas_lite(struct rkisp_isp_stats_vdev *stats_vdev,
}
if (meas_work->isp3a_ris & ISP3X_3A_RAWAWB)
ret |= rkisp_stats_get_rawawb_meas_lite(stats_vdev, cur_stat_buf);
rkisp_stats_get_rawawb_meas_lite(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWAF ||
stats_vdev->af_meas_done_next)
ret |= rkisp_stats_get_rawaf_meas_lite(stats_vdev, cur_stat_buf);
rkisp_stats_get_rawaf_meas_lite(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_BIG ||
stats_vdev->ae_meas_done_next)
ret |= rkisp_stats_get_rawae3_meas_lite(stats_vdev, cur_stat_buf);
rkisp_stats_get_rawae3_meas_lite(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_BIG)
ret |= rkisp_stats_get_rawhst3_meas_lite(stats_vdev, cur_stat_buf);
rkisp_stats_get_rawhst3_meas_lite(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWAE_CH0)
ret |= rkisp_stats_get_rawaelite_meas_lite(stats_vdev, cur_stat_buf);
rkisp_stats_get_rawaelite_meas_lite(stats_vdev, cur_stat_buf);
if (meas_work->isp3a_ris & ISP3X_3A_RAWHIST_CH0)
ret |= rkisp_stats_get_rawhstlite_meas_lite(stats_vdev, cur_stat_buf);
rkisp_stats_get_rawhstlite_meas_lite(stats_vdev, cur_stat_buf);
if (meas_work->isp_ris & ISP3X_FRAME) {
ret |= rkisp_stats_get_bls_stats(stats_vdev, cur_stat_buf);
ret |= rkisp_stats_get_dhaz_stats(stats_vdev, cur_stat_buf);
rkisp_stats_get_bls_stats(stats_vdev, cur_stat_buf);
rkisp_stats_get_dhaz_stats(stats_vdev, cur_stat_buf);
}
if (cur_buf) {
if (ret || !cur_stat_buf->meas_type) {
unsigned long flags;
spin_lock_irqsave(&stats_vdev->rd_lock, flags);
list_add_tail(&cur_buf->queue, &stats_vdev->stat);
spin_unlock_irqrestore(&stats_vdev->rd_lock, flags);
} else {
rkisp_stats_info2ddr(stats_vdev, cur_stat_buf);
vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size);
cur_buf->vb.sequence = cur_frame_id;
cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp;
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
rkisp_stats_info2ddr(stats_vdev, cur_stat_buf);
vb2_set_plane_payload(&cur_buf->vb.vb2_buf, 0, size);
cur_buf->vb.sequence = cur_frame_id;
cur_buf->vb.vb2_buf.timestamp = meas_work->timestamp;
vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
}
v4l2_dbg(4, rkisp_debug, &dev->v4l2_dev,
"%s seq:%d params_id:%d ris:0x%x buf:%p meas_type:0x%x\n",
__func__,
cur_frame_id, params_vdev->cur_frame_id, meas_work->isp_ris,
cur_buf, !cur_stat_buf ? 0 : cur_stat_buf->meas_type);
}
static void
@@ -1048,6 +1063,7 @@ void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
u32 size = stats_vdev->vdev_fmt.fmt.meta.buffersize;
u32 div = dev->hw_dev->unite ? 2 : 1;
if (dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
@@ -1059,8 +1075,8 @@ void rkisp_stats_first_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev)
else
memset(stats_vdev->stats_buf[0].vaddr, 0, size);
rkisp_stats_update_buf(stats_vdev);
rkisp_write(dev, ISP3X_MI_DBR_WR_SIZE, size, false);
rkisp_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false);
rkisp_unite_write(dev, ISP3X_MI_DBR_WR_SIZE, size / div, false);
rkisp_unite_set_bits(dev, ISP3X_SWS_CFG, 0, ISP3X_3A_DDR_WRITE_EN, false);
if (stats_vdev->nxt_buf) {
stats_vdev->cur_buf = stats_vdev->nxt_buf;
stats_vdev->nxt_buf = NULL;
@@ -1080,6 +1096,7 @@ void rkisp_stats_next_ddr_config_v32(struct rkisp_isp_stats_vdev *stats_vdev)
void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev)
{
int mult = stats_vdev->dev->hw_dev->unite ? 2 : 1;
u32 size;
stats_vdev->vdev_fmt.fmt.meta.dataformat =
@@ -1087,13 +1104,13 @@ void rkisp_init_stats_vdev_v32(struct rkisp_isp_stats_vdev *stats_vdev)
if (stats_vdev->dev->isp_ver == ISP_V32) {
stats_vdev->priv_ops = &stats_ddr_ops_v32;
stats_vdev->rd_stats_from_ddr = true;
size = sizeof(struct rkisp32_isp_stat_buffer);
size = ALIGN(sizeof(struct rkisp32_isp_stat_buffer), 16);
} else {
stats_vdev->priv_ops = NULL;
stats_vdev->rd_stats_from_ddr = false;
size = sizeof(struct rkisp32_lite_stat_buffer);
}
stats_vdev->vdev_fmt.fmt.meta.buffersize = size;
stats_vdev->vdev_fmt.fmt.meta.buffersize = size * mult;
stats_vdev->ops = &rkisp_isp_stats_ops_tbl;
}

18
drivers/media/platform/rockchip/isp/isp_stats_v3x.c
View File

@@ -1038,7 +1038,7 @@ rkisp_stats_send_meas_v3x(struct rkisp_isp_stats_vdev *stats_vdev,
ret |= ops->get_dhaz_stats(stats_vdev, cur_stat_buf, 0);
}
if (stats_vdev->dev->hw_dev->is_unite) {
if (stats_vdev->dev->hw_dev->unite) {
size *= 2;
if (cur_buf) {
cur_stat_buf++;
@@ -1086,7 +1086,7 @@ rkisp_stats_isr_v3x(struct rkisp_isp_stats_vdev *stats_vdev,
{
struct rkisp_device *dev = stats_vdev->dev;
struct rkisp_hw_dev *hw = dev->hw_dev;
void __iomem *base = !hw->is_unite ?
void __iomem *base = hw->unite != ISP_UNITE_TWO ?
hw->base_addr : hw->base_next_addr;
struct rkisp_isp_readout_work work;
u32 iq_isr_mask = ISP3X_SIAWB_DONE | ISP3X_SIAF_FIN |
@@ -1138,7 +1138,7 @@ rkisp_stats_isr_v3x(struct rkisp_isp_stats_vdev *stats_vdev,
rkisp_write(dev, ISP3X_MI_3A_WR_BASE,
stats_vdev->stats_buf[wr_buf_idx].dma_addr, false);
if (dev->hw_dev->is_unite)
if (dev->hw_dev->unite)
rkisp_next_write(dev, ISP3X_MI_3A_WR_BASE,
stats_vdev->stats_buf[wr_buf_idx].dma_addr +
ISP3X_RD_STATS_BUF_SIZE, false);
@@ -1178,7 +1178,7 @@ static struct rkisp_isp_stats_ops rkisp_isp_stats_ops_tbl = {
void rkisp_stats_first_ddr_config_v3x(struct rkisp_isp_stats_vdev *stats_vdev)
{
struct rkisp_device *dev = stats_vdev->dev;
int i, mult = dev->hw_dev->is_unite ? 2 : 1;
int i, mult = dev->hw_dev->unite ? 2 : 1;
if (dev->isp_sdev.in_fmt.fmt_type == FMT_YUV)
return;
@@ -1199,14 +1199,12 @@ void rkisp_stats_first_ddr_config_v3x(struct rkisp_isp_stats_vdev *stats_vdev)
stats_vdev->wr_buf_idx = 0;
rkisp_unite_write(dev, ISP3X_MI_DBR_WR_SIZE,
ISP3X_RD_STATS_BUF_SIZE,
false, dev->hw_dev->is_unite);
ISP3X_RD_STATS_BUF_SIZE, false);
rkisp_unite_set_bits(dev, ISP3X_SWS_CFG, 0,
ISP3X_3A_DDR_WRITE_EN, false,
dev->hw_dev->is_unite);
ISP3X_3A_DDR_WRITE_EN, false);
rkisp_write(dev, ISP3X_MI_3A_WR_BASE,
stats_vdev->stats_buf[0].dma_addr, false);
if (dev->hw_dev->is_unite)
if (dev->hw_dev->unite)
rkisp_next_write(dev, ISP3X_MI_3A_WR_BASE,
stats_vdev->stats_buf[0].dma_addr +
ISP3X_RD_STATS_BUF_SIZE, false);
@@ -1220,7 +1218,7 @@ err:
void rkisp_init_stats_vdev_v3x(struct rkisp_isp_stats_vdev *stats_vdev)
{
int mult = stats_vdev->dev->hw_dev->is_unite ? 2 : 1;
int mult = stats_vdev->dev->hw_dev->unite ? 2 : 1;
stats_vdev->vdev_fmt.fmt.meta.dataformat =
V4L2_META_FMT_RK_ISP1_STAT_3A;

4
drivers/media/platform/rockchip/isp/procfs.c
View File

@@ -933,7 +933,7 @@ static int isp_show(struct seq_file *p, void *v)
break;
case ISP_V30:
if (IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V30)) {
if (dev->hw_dev->is_unite)
if (dev->hw_dev->unite)
isp30_unite_show(dev, p);
else
isp30_show(dev, p);
@@ -963,7 +963,7 @@ static int isp_show(struct seq_file *p, void *v)
msecs_to_jiffies(1000));
seq_printf(p, "****************HW REG*Ret:%d**************\n", ret);
for (i = 0; i < ISP3X_RAWAWB_RAM_DATA_BASE; i += 16) {
if (!dev->hw_dev->is_unite) {
if (dev->hw_dev->unite != ISP_UNITE_TWO) {
seq_printf(p, "%04x: %08x %08x %08x %08x\n", i,
rkisp_read(dev, i, true),
rkisp_read(dev, i + 4, true),

62
drivers/media/platform/rockchip/isp/regs.c
View File

@@ -45,8 +45,7 @@ void rkisp_disable_dcrop(struct rkisp_stream *stream, bool async)
if (async && dev->hw_dev->is_single)
val = CIF_DUAL_CROP_GEN_CFG_UPD;
rkisp_unite_set_bits(dev, stream->config->dual_crop.ctrl,
mask, val, false, dev->hw_dev->is_unite);
rkisp_unite_set_bits(dev, stream->config->dual_crop.ctrl, mask, val, false);
}
void rkisp_config_dcrop(struct rkisp_stream *stream,
@@ -54,7 +53,7 @@ void rkisp_config_dcrop(struct rkisp_stream *stream,
{
struct rkisp_device *dev = stream->ispdev;
u32 val = stream->config->dual_crop.yuvmode_mask;
bool is_unite = dev->hw_dev->is_unite;
bool is_unite = !!dev->hw_dev->unite;
struct v4l2_rect tmp = *rect;
u32 reg;
@@ -69,9 +68,9 @@ void rkisp_config_dcrop(struct rkisp_stream *stream,
rkisp_write(dev, reg, tmp.width, false);
reg = stream->config->dual_crop.v_offset;
rkisp_unite_write(dev, reg, tmp.top, false, is_unite);
rkisp_unite_write(dev, reg, tmp.top, false);
reg = stream->config->dual_crop.v_size;
rkisp_unite_write(dev, reg, tmp.height, false, is_unite);
rkisp_unite_write(dev, reg, tmp.height, false);
if (async && dev->hw_dev->is_single)
val |= CIF_DUAL_CROP_GEN_CFG_UPD;
@@ -149,8 +148,7 @@ static void update_rsz_shadow(struct rkisp_stream *stream, bool async)
if (async && dev->hw_dev->is_single)
val = CIF_RSZ_CTRL_CFG_UPD_AUTO;
rkisp_unite_set_bits(dev, stream->config->rsz.ctrl, 0,
val, false, dev->hw_dev->is_unite);
rkisp_unite_set_bits(dev, stream->config->rsz.ctrl, 0, val, false);
}
static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
@@ -220,17 +218,8 @@ static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
rkisp_write(dev, scale_vc_addr, scale_vc, false);
}
if (dev->hw_dev->is_unite) {
u32 hy_size_reg = stream->id == RKISP_STREAM_MP ?
ISP3X_MAIN_RESIZE_HY_SIZE : ISP3X_SELF_RESIZE_HY_SIZE;
u32 hc_size_reg = stream->id == RKISP_STREAM_MP ?
ISP3X_MAIN_RESIZE_HC_SIZE : ISP3X_SELF_RESIZE_HC_SIZE;
u32 hy_offs_mi_reg = stream->id == RKISP_STREAM_MP ?
ISP3X_MAIN_RESIZE_HY_OFFS_MI : ISP3X_SELF_RESIZE_HY_OFFS_MI;
u32 hc_offs_mi_reg = stream->id == RKISP_STREAM_MP ?
ISP3X_MAIN_RESIZE_HC_OFFS_MI : ISP3X_SELF_RESIZE_HC_OFFS_MI;
u32 in_crop_offs_reg = stream->id == RKISP_STREAM_MP ?
ISP3X_MAIN_RESIZE_IN_CROP_OFFSET : ISP3X_SELF_RESIZE_IN_CROP_OFFSET;
if (dev->hw_dev->unite) {
u32 hy_size_reg, hc_size_reg, hy_offs_mi_reg, hc_offs_mi_reg, in_crop_offs_reg;
u32 isp_in_w = in_y->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
u32 scl_w = out_y->width / 2;
u32 left_y = scale_hy == 1 ? scl_w : DIV_ROUND_UP(scl_w * 65536, scale_hy);
@@ -249,6 +238,34 @@ static void set_scale(struct rkisp_stream *stream, struct v4l2_rect *in_y,
u32 right_scl_in_y;
u32 right_scl_in_c;
switch (stream->id) {
case RKISP_STREAM_MP:
hy_size_reg = ISP3X_MAIN_RESIZE_HY_SIZE;
hc_size_reg = ISP3X_MAIN_RESIZE_HC_SIZE;
hy_offs_mi_reg = ISP3X_MAIN_RESIZE_HY_OFFS_MI;
hc_offs_mi_reg = ISP3X_MAIN_RESIZE_HC_OFFS_MI;
in_crop_offs_reg = ISP3X_MAIN_RESIZE_IN_CROP_OFFSET;
break;
case RKISP_STREAM_SP:
hy_size_reg = ISP3X_SELF_RESIZE_HY_SIZE;
hc_size_reg = ISP3X_SELF_RESIZE_HC_SIZE;
hy_offs_mi_reg = ISP3X_SELF_RESIZE_HY_OFFS_MI;
hc_offs_mi_reg = ISP3X_SELF_RESIZE_HC_OFFS_MI;
in_crop_offs_reg = ISP3X_SELF_RESIZE_IN_CROP_OFFSET;
break;
case RKISP_STREAM_BP:
hy_size_reg = ISP32_BP_RESIZE_HY_SIZE;
hc_size_reg = ISP32_BP_RESIZE_HC_SIZE;
hy_offs_mi_reg = ISP32_BP_RESIZE_HY_OFFS_MI;
hc_offs_mi_reg = ISP32_BP_RESIZE_HC_OFFS_MI;
in_crop_offs_reg = ISP32_BP_RESIZE_IN_CROP_OFFSET;
break;
default:
v4l2_warn(&dev->v4l2_dev, "%s no support unite for stream:%d\n",
__func__, stream->id);
return;
}
if (right_crop_y < RKMOUDLE_UNITE_EXTEND_PIXEL) {
u32 reg;
@@ -362,7 +379,6 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
{
struct rkisp_device *dev = stream->ispdev;
int i = 0;
bool is_unite = dev->hw_dev->is_unite;
if (dev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP) {
set_bilinear_scale(stream, in_y, in_c, out_y, out_c, async);
@@ -377,8 +393,8 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
/* Linear interpolation */
for (i = 0; i < 64; i++) {
rkisp_unite_write(dev, stream->config->rsz.scale_lut_addr, i, true, is_unite);
rkisp_unite_write(dev, stream->config->rsz.scale_lut, i, true, is_unite);
rkisp_unite_write(dev, stream->config->rsz.scale_lut_addr, i, true);
rkisp_unite_write(dev, stream->config->rsz.scale_lut, i, true);
}
set_scale(stream, in_y, in_c, out_y, out_c);
@@ -388,9 +404,7 @@ void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
void rkisp_disable_rsz(struct rkisp_stream *stream, bool async)
{
bool is_unite = stream->ispdev->hw_dev->is_unite;
rkisp_unite_write(stream->ispdev, stream->config->rsz.ctrl, 0, false, is_unite);
rkisp_unite_write(stream->ispdev, stream->config->rsz.ctrl, 0, false);
if (stream->ispdev->isp_ver == ISP_V32_L && stream->id == RKISP_STREAM_SP)
return;
update_rsz_shadow(stream, async);

14
drivers/media/platform/rockchip/isp/regs.h
View File

@@ -1753,7 +1753,7 @@ static inline void mi_set_cr_offset(struct rkisp_stream *stream, int val)
static inline void mi_frame_end_int_enable(struct rkisp_stream *stream)
{
struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
void __iomem *base = !hw->is_unite ?
void __iomem *base = hw->unite != ISP_UNITE_TWO ?
hw->base_addr : hw->base_next_addr;
void __iomem *addr = base + CIF_MI_IMSC;
@@ -1763,7 +1763,7 @@ static inline void mi_frame_end_int_enable(struct rkisp_stream *stream)
static inline void mi_frame_end_int_disable(struct rkisp_stream *stream)
{
struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
void __iomem *base = !hw->is_unite ?
void __iomem *base = hw->unite != ISP_UNITE_TWO ?
hw->base_addr : hw->base_next_addr;
void __iomem *addr = base + CIF_MI_IMSC;
@@ -1773,7 +1773,7 @@ static inline void mi_frame_end_int_disable(struct rkisp_stream *stream)
static inline void mi_frame_end_int_clear(struct rkisp_stream *stream)
{
struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
void __iomem *base = !hw->is_unite ?
void __iomem *base = hw->unite != ISP_UNITE_TWO ?
hw->base_addr : hw->base_next_addr;
void __iomem *addr = base + CIF_MI_ICR;
@@ -1783,7 +1783,6 @@ static inline void mi_frame_end_int_clear(struct rkisp_stream *stream)
static inline void stream_data_path(struct rkisp_stream *stream)
{
struct rkisp_device *dev = stream->ispdev;
bool is_unite = dev->hw_dev->is_unite;
u32 dpcl = 0;
if (stream->id == RKISP_STREAM_MP)
@@ -1792,7 +1791,7 @@ static inline void stream_data_path(struct rkisp_stream *stream)
dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
if (dpcl)
rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true, is_unite);
rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true);
}
static inline void mp_set_uv_swap(void __iomem *base)
@@ -1914,16 +1913,15 @@ static inline void sp_mi_ctrl_autoupdate_en(void __iomem *base)
static inline void force_cfg_update(struct rkisp_device *dev)
{
u32 val = CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN;
bool is_unite = dev->hw_dev->is_unite;
if (dev->isp_ver == ISP_V21) {
val |= rkisp_read_reg_cache(dev, CIF_MI_CTRL);
rkisp_write(dev, CIF_MI_CTRL, val, true);
}
dev->hw_dev->is_mi_update = true;
rkisp_unite_set_bits(dev, CIF_MI_CTRL, 0, val, false, is_unite);
rkisp_unite_set_bits(dev, CIF_MI_CTRL, 0, val, false);
val = CIF_MI_INIT_SOFT_UPD;
rkisp_unite_write(dev, CIF_MI_INIT, val, true, is_unite);
rkisp_unite_write(dev, CIF_MI_INIT, val, true);
}
static inline void dmatx0_ctrl(void __iomem *base, u32 val)

2
drivers/media/platform/rockchip/isp/regs_v2x.h
View File

@@ -2700,7 +2700,7 @@ static inline void mi_raw_length(struct rkisp_stream *stream)
stream->out_fmt.plane_fmt[0].bytesperline, is_direct);
if (stream->ispdev->isp_ver == ISP_V21 || stream->ispdev->isp_ver == ISP_V30)
rkisp_set_bits(stream->ispdev, MI_RD_CTRL2, 0, BIT(30), false);
if (stream->ispdev->hw_dev->is_unite) {
if (stream->ispdev->hw_dev->unite) {
rkisp_next_write(stream->ispdev, stream->config->mi.length,
stream->out_fmt.plane_fmt[0].bytesperline, is_direct);
rkisp_next_set_bits(stream->ispdev, MI_RD_CTRL2, 0, BIT(30), false);

9
drivers/media/platform/rockchip/isp/regs_v3x.h
View File

@@ -343,6 +343,15 @@
#define ISP32_BP_RESIZE_PHASE_HC_SHD (ISP32_BP_RESIZE_BASE + 0x0004c)
#define ISP32_BP_RESIZE_PHASE_VY_SHD (ISP32_BP_RESIZE_BASE + 0x00050)
#define ISP32_BP_RESIZE_PHASE_VC_SHD (ISP32_BP_RESIZE_BASE + 0x00054)
#define ISP32_BP_RESIZE_HY_SIZE (ISP32_BP_RESIZE_BASE + 0x00058)
#define ISP32_BP_RESIZE_HC_SIZE (ISP32_BP_RESIZE_BASE + 0x0005c)
#define ISP32_BP_RESIZE_HY_OFFS_MI (ISP32_BP_RESIZE_BASE + 0x00060)
#define ISP32_BP_RESIZE_HC_OFFS_MI (ISP32_BP_RESIZE_BASE + 0x00064)
#define ISP32_BP_RESIZE_HY_SIZE_SHD (ISP32_BP_RESIZE_BASE + 0x00068)
#define ISP32_BP_RESIZE_HC_SIZE_SHD (ISP32_BP_RESIZE_BASE + 0x0006c)
#define ISP32_BP_RESIZE_HY_OFFS_MI_SHD (ISP32_BP_RESIZE_BASE + 0x00070)
#define ISP32_BP_RESIZE_HC_OFFS_MI_SHD (ISP32_BP_RESIZE_BASE + 0x00074)
#define ISP32_BP_RESIZE_IN_CROP_OFFSET (ISP32_BP_RESIZE_BASE + 0x00078)
#define ISP3X_SELF_RESIZE_BASE 0x00001000
#define ISP3X_SELF_RESIZE_CTRL (ISP3X_SELF_RESIZE_BASE + 0x00000)

331
drivers/media/platform/rockchip/isp/rkisp.c
View File

@@ -213,17 +213,16 @@ int rkisp_align_sensor_resolution(struct rkisp_device *dev,
max_h = CIF_ISP_INPUT_H_MAX_V21;
break;
case ISP_V30:
if (dev->hw_dev->is_unite) {
max_w = CIF_ISP_INPUT_W_MAX_V30_UNITE;
max_h = CIF_ISP_INPUT_H_MAX_V30_UNITE;
} else {
max_w = CIF_ISP_INPUT_W_MAX_V30;
max_h = CIF_ISP_INPUT_H_MAX_V30;
}
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
break;
case ISP_V32:
max_w = CIF_ISP_INPUT_W_MAX_V32;
max_h = CIF_ISP_INPUT_H_MAX_V32;
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
break;
case ISP_V32_L:
max_w = CIF_ISP_INPUT_W_MAX_V32_L;
@@ -517,7 +516,7 @@ static void rkisp_dvfs(struct rkisp_device *dev)
/* set isp clock rate */
rkisp_set_clk_rate(hw->clks[0], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
if (hw->is_unite)
if (hw->unite == ISP_UNITE_TWO)
rkisp_set_clk_rate(hw->clks[5], hw->clk_rate_tbl[i].clk_rate * 1000000UL);
/* aclk equal to core clk */
if (dev->isp_ver == ISP_V32)
@@ -550,7 +549,7 @@ static void rkisp_multi_overflow_hdl(struct rkisp_device *dev, bool on)
writel(0, hw->base_addr + ISP3X_MPFBC_CTRL);
writel(0, hw->base_addr + ISP3X_MI_BP_WR_CTRL);
writel(0xc, hw->base_addr + ISP3X_SWS_CFG);
if (hw->is_unite) {
if (hw->unite == ISP_UNITE_TWO) {
writel(0, hw->base_next_addr + ISP3X_MI_WR_CTRL);
writel(0, hw->base_next_addr + ISP3X_MPFBC_CTRL);
writel(0, hw->base_next_addr + ISP3X_MI_BP_WR_CTRL);
@@ -562,7 +561,7 @@ static void rkisp_multi_overflow_hdl(struct rkisp_device *dev, bool on)
writel(0, hw->base_addr + ISP32_MI_MPDS_WR_CTRL);
}
}
rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite);
rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
}
/*
@@ -582,7 +581,8 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
hw->cur_dev_id = dev->dev_id;
rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true);
if (hw->is_multi_overflow && is_try)
/* isp process the same frame */
if (is_try)
goto run_next;
val = 0;
@@ -612,13 +612,12 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
}
if (rd_mode != dev->rd_mode) {
rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK,
val, false, hw->is_unite);
rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK, val, false);
dev->skip_frame = 2;
is_upd = true;
}
if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL && !is_try) {
if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL) {
if (dev->rd_mode != rd_mode && dev->br_dev.en) {
tmp = dev->isp_sdev.in_crop.height;
val = rkisp_read(dev, CIF_DUAL_CROP_CTRL, false);
@@ -639,12 +638,15 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
}
dev->rd_mode = rd_mode;
rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt,
dev->isp_sdev.quantization);
rkisp_params_cfg(params_vdev, cur_frame_id);
rkisp_config_cmsk(dev);
rkisp_stream_frame_start(dev, 0);
if (!hw->is_single && !is_try) {
if (hw->unite != ISP_UNITE_ONE || dev->unite_index == ISP_UNITE_LEFT) {
rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt,
dev->isp_sdev.quantization);
rkisp_params_cfg(params_vdev, cur_frame_id);
rkisp_config_cmsk(dev);
rkisp_stream_frame_start(dev, 0);
}
if (!hw->is_single) {
/* multi sensor need to reset isp resize mode if scale up */
val = 0;
if (rkisp_read(dev, ISP3X_MAIN_RESIZE_CTRL, true) & 0xf0)
@@ -680,7 +682,7 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
} else {
if (dev->isp_ver == ISP_V32_L)
rkisp_write(dev, ISP32_SELF_SCALE_UPDATE, ISP32_SCALE_FORCE_UPD, true);
rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true, hw->is_unite);
rkisp_unite_write(dev, ISP3X_MI_WR_INIT, CIF_MI_INIT_SOFT_UPD, true);
}
/* sensor mode & index */
if (dev->isp_ver >= ISP_V21) {
@@ -691,7 +693,7 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
else
val |= ISP21_SENSOR_MODE(dev->multi_mode);
writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
if (hw->is_unite)
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP_ACQ_H_OFFS);
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"sensor mode:%d index:%d | 0x%x\n",
@@ -711,49 +713,15 @@ void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, boo
else
dev->rdbk_cnt_x1++;
dev->rdbk_cnt++;
rkisp_params_cfgsram(params_vdev);
params_vdev->rdbk_times = dma2frm + 1;
if (dev->isp_ver == ISP_V20)
params_vdev->rdbk_times = dma2frm + 1;
run_next:
if (hw->is_multi_overflow && !dev->is_first_double) {
stats_vdev->rdbk_drop = false;
if (dev->sw_rd_cnt) {
/* the frame first running to off mi to save bandwidth */
rkisp_multi_overflow_hdl(dev, false);
/* FST_FRAME no to read sram thumb */
val = ISP3X_YNR_FST_FRAME | ISP3X_DHAZ_FST_FRAME;
if (dev->isp_ver == ISP_V32)
val |= ISP32_SHP_FST_FRAME;
else
val |= ISP3X_CNR_FST_FRAME;
rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL1, 0, val, false, hw->is_unite);
/* ADRC low iir thumb weight for first sensor switch */
val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN);
val &= ~ISP3X_DRC_IIR_WEIGHT_MASK;
writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN);
/* ADRC iir5x5 and cur3x3 weight */
val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO);
val &= ~ISP3X_DRC_WEIPRE_FRAME_MASK;
writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO);
/* YNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */
val = rkisp_read_reg_cache(dev, ISP3X_YNR_GLOBAL_CTRL);
val |= ISP3X_YNR_THUMB_MIX_CUR_EN;
writel(val, hw->base_addr + ISP3X_YNR_GLOBAL_CTRL);
if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30) {
/* CNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */
val = rkisp_read_reg_cache(dev, ISP3X_CNR_CTRL);
val |= ISP3X_CNR_THUMB_MIX_CUR_EN;
writel(val, hw->base_addr + ISP3X_CNR_CTRL);
if (hw->is_unite)
writel(val, hw->base_next_addr + ISP3X_CNR_CTRL);
}
params_vdev->rdbk_times += dev->sw_rd_cnt;
stats_vdev->rdbk_drop = true;
is_upd = true;
} else if (is_try) {
rkisp_params_cfgsram(params_vdev);
stats_vdev->rdbk_drop = false;
if (dev->is_frame_double) {
is_upd = true;
if (is_try) {
/* the frame second running to on mi */
rkisp_multi_overflow_hdl(dev, true);
rkisp_update_regs(dev, ISP_LDCH_BASE, ISP_LDCH_BASE);
@@ -763,13 +731,53 @@ run_next:
val |= ISP32_SHP_FST_FRAME;
else
val |= ISP3X_CNR_FST_FRAME;
rkisp_unite_clear_bits(dev, ISP3X_ISP_CTRL1, val, false, hw->is_unite);
rkisp_unite_clear_bits(dev, ISP3X_ISP_CTRL1, val, false);
val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN);
writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN);
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP3X_DRC_IIRWG_GAIN);
val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO);
writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO);
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP3X_DRC_EXPLRATIO);
} else {
/* the frame first running to off mi to save bandwidth */
rkisp_multi_overflow_hdl(dev, false);
is_upd = true;
/* FST_FRAME no to read sram thumb */
val = ISP3X_YNR_FST_FRAME | ISP3X_DHAZ_FST_FRAME;
if (dev->isp_ver == ISP_V32)
val |= ISP32_SHP_FST_FRAME;
else
val |= ISP3X_CNR_FST_FRAME;
rkisp_unite_set_bits(dev, ISP3X_ISP_CTRL1, 0, val, false);
/* ADRC low iir thumb weight for first sensor switch */
val = rkisp_read_reg_cache(dev, ISP3X_DRC_IIRWG_GAIN);
val &= ~ISP3X_DRC_IIR_WEIGHT_MASK;
writel(val, hw->base_addr + ISP3X_DRC_IIRWG_GAIN);
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP3X_DRC_IIRWG_GAIN);
/* ADRC iir5x5 and cur3x3 weight */
val = rkisp_read_reg_cache(dev, ISP3X_DRC_EXPLRATIO);
val &= ~ISP3X_DRC_WEIPRE_FRAME_MASK;
writel(val, hw->base_addr + ISP3X_DRC_EXPLRATIO);
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP3X_DRC_EXPLRATIO);
/* YNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */
val = rkisp_read_reg_cache(dev, ISP3X_YNR_GLOBAL_CTRL);
val |= ISP3X_YNR_THUMB_MIX_CUR_EN;
writel(val, hw->base_addr + ISP3X_YNR_GLOBAL_CTRL);
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP3X_YNR_GLOBAL_CTRL);
if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30) {
/* CNR_THUMB_MIX_CUR_EN for thumb read addr to 0 */
val = rkisp_read_reg_cache(dev, ISP3X_CNR_CTRL);
val |= ISP3X_CNR_THUMB_MIX_CUR_EN;
writel(val, hw->base_addr + ISP3X_CNR_CTRL);
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP3X_CNR_CTRL);
}
stats_vdev->rdbk_drop = true;
}
}
@@ -778,13 +786,13 @@ run_next:
*/
if (hw->is_single && is_upd &&
rkisp_read_reg_cache(dev, ISP_3DLUT_UPDATE) & 0x1) {
rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true, hw->is_unite);
rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 0, true);
is_3dlut_upd = true;
}
if (is_upd) {
val = rkisp_read(dev, ISP_CTRL, false);
val |= CIF_ISP_CTRL_ISP_CFG_UPD;
rkisp_unite_write(dev, ISP_CTRL, val, true, hw->is_unite);
rkisp_unite_write(dev, ISP_CTRL, val, true);
/* bayer pat after ISP_CFG_UPD for multi sensor to read lsc r/g/b table */
rkisp_update_regs(dev, ISP3X_ISP_CTRL1, ISP3X_ISP_CTRL1);
/* fix ldch multi sensor case:
@@ -797,12 +805,12 @@ run_next:
udelay(50);
val &= ~(BIT(0) | BIT(31));
writel(val, hw->base_addr + ISP_LDCH_BASE);
if (hw->is_unite)
if (hw->unite == ISP_UNITE_TWO)
writel(val, hw->base_next_addr + ISP_LDCH_BASE);
}
}
if (is_3dlut_upd)
rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true, hw->is_unite);
rkisp_unite_write(dev, ISP_3DLUT_UPDATE, 1, true);
/* if output stream enable, wait it end */
val = rkisp_read(dev, CIF_MI_CTRL_SHD, true);
@@ -836,10 +844,10 @@ run_next:
if (dev->isp_ver > ISP_V20)
dma2frm = dev->sw_rd_cnt;
v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
"readback frame:%d time:%d 0x%x\n",
cur_frame_id, dma2frm + 1, val);
"readback frame:%d time:%d 0x%x try:%d\n",
cur_frame_id, dma2frm + 1, val, is_try);
if (!hw->is_shutdown)
rkisp_unite_write(dev, CSI2RX_CTRL0, val, true, hw->is_unite);
rkisp_unite_write(dev, CSI2RX_CTRL0, val, true);
}
static void rkisp_fast_switch_rx_buf(struct rkisp_device *dev, bool is_current)
@@ -893,6 +901,12 @@ static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
isp = dev;
is_try = true;
times = 0;
if (hw->unite == ISP_UNITE_ONE) {
if (dev->sw_rd_cnt < 2)
isp->unite_index = ISP_UNITE_RIGHT;
if (!hw->is_multi_overflow || (dev->sw_rd_cnt & 0x1))
is_try = false;
}
goto end;
}
hw->is_idle = true;
@@ -942,17 +956,40 @@ static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
times = t.times;
hw->cur_dev_id = id;
hw->is_idle = false;
/* this frame will read count by isp */
isp->sw_rd_cnt = 0;
if (hw->is_multi_overflow && (hw->pre_dev_id != id)) {
/* frame double for multi camera resolution out of hardware limit
* first for HW save this camera information, and second to output image
*/
isp->is_frame_double = false;
if (hw->is_multi_overflow &&
(hw->unite == ISP_UNITE_ONE ||
(hw->pre_dev_id != -1 && hw->pre_dev_id != id))) {
isp->is_frame_double = true;
isp->sw_rd_cnt = 1;
times = 0;
}
/* resolution out of hardware limit
* frame is vertically divided into left and right
*/
isp->unite_index = ISP_UNITE_LEFT;
if (hw->unite == ISP_UNITE_ONE) {
isp->sw_rd_cnt *= 2;
isp->sw_rd_cnt += 1;
}
/* first frame handle twice for thunderboot
* first output stats to AIQ and wait new params to run second
*/
if (isp->is_pre_on && t.frame_id == 0) {
isp->is_first_double = true;
isp->skip_frame = 1;
isp->sw_rd_cnt = 0;
if (hw->unite != ISP_UNITE_ONE) {
isp->sw_rd_cnt = 0;
isp->is_frame_double = false;
}
rkisp_fast_switch_rx_buf(isp, false);
}
isp->params_vdev.rdbk_times = isp->sw_rd_cnt + 1;
}
end:
spin_unlock_irqrestore(&hw->rdbk_lock, lock_flags);
@@ -1010,12 +1047,6 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
{
u32 val = 0;
if (dev->hw_dev->is_multi_overflow &&
dev->sw_rd_cnt &&
irq & ISP_FRAME_END &&
!dev->is_first_double)
goto end;
dev->irq_ends |= (irq & dev->irq_ends_mask);
v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
"%s irq:0x%x ends:0x%x mask:0x%x\n",
@@ -1030,6 +1061,9 @@ void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
!IS_HDR_RDBK(dev->rd_mode))
return;
if (dev->sw_rd_cnt)
goto end;
if (dev->is_first_double) {
rkisp_fast_switch_rx_buf(dev, true);
dev->skip_frame = 0;
@@ -1096,26 +1130,25 @@ static void rkisp_config_ism(struct rkisp_device *dev)
{
struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop;
u32 width = out_crop->width, mult = 1;
bool is_unite = dev->hw_dev->is_unite;
u32 unite = dev->hw_dev->unite;
/* isp2.0 no ism */
if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21 ||
dev->isp_ver == ISP_V32_L)
return;
if (is_unite)
if (unite)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false, is_unite);
rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false, is_unite);
rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false, is_unite);
rkisp_unite_write(dev, CIF_ISP_IS_DISPLACE, 0, false, is_unite);
rkisp_unite_write(dev, CIF_ISP_IS_H_OFFS, out_crop->left, false, is_unite);
rkisp_unite_write(dev, CIF_ISP_IS_V_OFFS, out_crop->top, false, is_unite);
rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false, is_unite);
rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false);
rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false);
rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false);
rkisp_unite_write(dev, CIF_ISP_IS_DISPLACE, 0, false);
rkisp_unite_write(dev, CIF_ISP_IS_H_OFFS, out_crop->left, false);
rkisp_unite_write(dev, CIF_ISP_IS_V_OFFS, out_crop->top, false);
rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false);
if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced)
mult = 2;
rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult,
false, is_unite);
rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult, false);
if (dev->isp_ver == ISP_V30 || dev->isp_ver == ISP_V32)
return;
@@ -1417,20 +1450,18 @@ static void rkisp_config_color_space(struct rkisp_device *dev)
for (i = 0; i < 9; i++)
rkisp_unite_write(dev, CIF_ISP_CC_COEFF_0 + i * 4,
*(coeff + i), false, dev->hw_dev->is_unite);
*(coeff + i), false);
val = rkisp_read_reg_cache(dev, CIF_ISP_CTRL);
if (dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
rkisp_unite_write(dev, CIF_ISP_CTRL, val |
CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA,
false, dev->hw_dev->is_unite);
CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA, false);
else
rkisp_unite_write(dev, CIF_ISP_CTRL, val &
~(CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA),
false, dev->hw_dev->is_unite);
CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA), false);
}
static void rkisp_config_cmsk_single(struct rkisp_device *dev,
@@ -1629,7 +1660,7 @@ static void rkisp_config_cmsk(struct rkisp_device *dev)
cfg = dev->cmsk_cfg;
spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
if (!dev->hw_dev->is_unite)
if (!dev->hw_dev->unite)
rkisp_config_cmsk_single(dev, &cfg);
else
rkisp_config_cmsk_dual(dev, &cfg);
@@ -1644,7 +1675,7 @@ static int rkisp_config_isp(struct rkisp_device *dev)
struct ispsd_out_fmt *out_fmt;
struct v4l2_rect *in_crop;
struct rkisp_sensor_info *sensor;
bool is_unite = dev->hw_dev->is_unite;
bool is_unite = !!dev->hw_dev->unite;
u32 isp_ctrl = 0;
u32 irq_mask = 0;
u32 signal = 0;
@@ -1674,22 +1705,20 @@ static int rkisp_config_isp(struct rkisp_device *dev)
in_fmt->mbus_code == MEDIA_BUS_FMT_Y10_1X10 ||
in_fmt->mbus_code == MEDIA_BUS_FMT_Y12_1X12) {
if (dev->isp_ver >= ISP_V20)
rkisp_unite_write(dev, ISP_DEBAYER_CONTROL,
0, false, is_unite);
rkisp_unite_write(dev, ISP_DEBAYER_CONTROL, 0, false);
else
rkisp_write(dev, CIF_ISP_DEMOSAIC,
CIF_ISP_DEMOSAIC_BYPASS |
CIF_ISP_DEMOSAIC_TH(0xc), false);
CIF_ISP_DEMOSAIC_BYPASS |
CIF_ISP_DEMOSAIC_TH(0xc), false);
} else {
if (dev->isp_ver >= ISP_V20)
rkisp_unite_write(dev, ISP_DEBAYER_CONTROL,
SW_DEBAYER_EN |
SW_DEBAYER_FILTER_G_EN |
SW_DEBAYER_FILTER_C_EN,
false, is_unite);
SW_DEBAYER_FILTER_C_EN, false);
else
rkisp_write(dev, CIF_ISP_DEMOSAIC,
CIF_ISP_DEMOSAIC_TH(0xc), false);
CIF_ISP_DEMOSAIC_TH(0xc), false);
}
if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
@@ -1741,38 +1770,31 @@ static int rkisp_config_isp(struct rkisp_device *dev)
if (rkisp_read_reg_cache(dev, CIF_ISP_CTRL) & ISP32_MIR_ENABLE)
isp_ctrl |= ISP32_MIR_ENABLE;
rkisp_unite_write(dev, CIF_ISP_CTRL, isp_ctrl, false, is_unite);
rkisp_unite_write(dev, CIF_ISP_CTRL, isp_ctrl, false);
acq_prop |= signal | in_fmt->yuv_seq |
CIF_ISP_ACQ_PROP_BAYER_PAT(in_fmt->bayer_pat) |
CIF_ISP_ACQ_PROP_FIELD_SEL_ALL;
rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false, is_unite);
rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true, is_unite);
rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false);
rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true);
if (is_unite)
width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
/* Acquisition Size */
rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left,
false, is_unite);
rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top,
false, is_unite);
rkisp_unite_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * width,
false, is_unite);
rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left, false);
rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top, false);
rkisp_unite_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * width, false);
/* ISP Out Area differ with ACQ is only FIFO, so don't crop in this */
rkisp_unite_write(dev, CIF_ISP_OUT_H_OFFS, 0, true, is_unite);
rkisp_unite_write(dev, CIF_ISP_OUT_V_OFFS, 0, true, is_unite);
rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false, is_unite);
rkisp_unite_write(dev, CIF_ISP_OUT_H_OFFS, 0, true);
rkisp_unite_write(dev, CIF_ISP_OUT_V_OFFS, 0, true);
rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false);
if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) {
rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2,
false, is_unite);
rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2,
false, is_unite);
rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2, false);
rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2, false);
} else {
rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line,
false, is_unite);
rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line,
false, is_unite);
rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line, false);
rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line, false);
}
/* interrupt mask */
@@ -1781,7 +1803,7 @@ static int rkisp_config_isp(struct rkisp_device *dev)
irq_mask |= ISP2X_LSC_LUT_ERR;
if (dev->is_pre_on)
irq_mask |= CIF_ISP_FRAME_IN;
rkisp_unite_write(dev, CIF_ISP_IMSC, irq_mask, true, is_unite);
rkisp_unite_write(dev, CIF_ISP_IMSC, irq_mask, true);
if ((dev->isp_ver == ISP_V20 ||
dev->isp_ver == ISP_V21) &&
@@ -1922,8 +1944,7 @@ static int rkisp_config_path(struct rkisp_device *dev)
if (dev->isp_ver == ISP_V32)
dpcl |= BIT(0);
rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true,
dev->hw_dev->is_unite);
rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true);
return ret;
}
@@ -2020,9 +2041,9 @@ static int rkisp_isp_stop(struct rkisp_device *dev)
v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
"%s refcnt:%d\n", __func__,
atomic_read(&dev->hw_dev->refcnt));
atomic_read(&hw->refcnt));
if (atomic_read(&dev->hw_dev->refcnt) > 1)
if (atomic_read(&hw->refcnt) > 1)
goto end;
/*
* ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
@@ -2078,7 +2099,7 @@ static int rkisp_isp_stop(struct rkisp_device *dev)
val = readl(base + CIF_ISP_CTRL);
writel(val | CIF_ISP_CTRL_ISP_CFG_UPD, base + CIF_ISP_CTRL);
if (hw->is_unite)
if (hw->unite == ISP_UNITE_TWO)
rkisp_next_write(dev, CIF_ISP_CTRL,
val | CIF_ISP_CTRL_ISP_CFG_UPD, true);
@@ -2095,11 +2116,11 @@ static int rkisp_isp_stop(struct rkisp_device *dev)
safe_rate = hw->clk_rate_tbl[0].clk_rate * 1000000UL;
if (old_rate > safe_rate) {
rkisp_set_clk_rate(hw->clks[0], safe_rate);
if (hw->is_unite)
if (hw->unite == ISP_UNITE_TWO)
rkisp_set_clk_rate(hw->clks[5], safe_rate);
udelay(100);
}
rkisp_soft_reset(dev->hw_dev, false);
rkisp_soft_reset(hw, false);
}
if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
@@ -2110,14 +2131,15 @@ static int rkisp_isp_stop(struct rkisp_device *dev)
writel(0, base + CIF_ISP_CSI0_MASK3);
} else if (dev->isp_ver >= ISP_V20) {
writel(0, base + CSI2RX_CSI2_RESETN);
if (hw->is_unite)
if (hw->unite == ISP_UNITE_TWO)
rkisp_next_write(dev, CSI2RX_CSI2_RESETN, 0, true);
}
hw->is_dvfs = false;
hw->is_runing = false;
dev->hw_dev->is_idle = true;
dev->hw_dev->is_mi_update = false;
hw->is_idle = true;
hw->is_mi_update = false;
hw->pre_dev_id = -1;
end:
dev->irq_ends_mask = 0;
dev->hdr.op_mode = 0;
@@ -2168,12 +2190,9 @@ static int rkisp_isp_start(struct rkisp_device *dev)
val = dev->isp_sdev.out_crop.height / 15;
val = dev->cap_dev.wait_line / val;
val = ISP3X_RAWAF_INELINE0(val) | ISP3X_RAWAF_INTLINE0_EN;
rkisp_unite_write(dev, ISP3X_RAWAF_INT_LINE,
val, false, dev->hw_dev->is_unite);
rkisp_unite_set_bits(dev, ISP_ISP3A_IMSC, 0,
ISP2X_3A_RAWAF, false, dev->hw_dev->is_unite);
rkisp_unite_clear_bits(dev, CIF_ISP_IMSC,
ISP2X_LSC_LUT_ERR, false, dev->hw_dev->is_unite);
rkisp_unite_write(dev, ISP3X_RAWAF_INT_LINE, val, false);
rkisp_unite_set_bits(dev, ISP_ISP3A_IMSC, 0, ISP2X_3A_RAWAF, false);
rkisp_unite_clear_bits(dev, CIF_ISP_IMSC, ISP2X_LSC_LUT_ERR, false);
dev->rawaf_irq_cnt = 0;
}
}
@@ -2201,7 +2220,7 @@ static int rkisp_isp_start(struct rkisp_device *dev)
val |= NOC_HURRY_PRIORITY(2) | NOC_HURRY_W_MODE(2) | NOC_HURRY_R_MODE(1);
if (atomic_read(&dev->hw_dev->refcnt) > 1)
is_direct = false;
rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct, dev->hw_dev->is_unite);
rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct);
rkisp_clear_reg_cache_bits(dev, CIF_ISP_CTRL, CIF_ISP_CTRL_ISP_CFG_UPD);
dev->isp_err_cnt = 0;
@@ -2681,14 +2700,16 @@ static int rkisp_isp_sd_get_selection(struct v4l2_subdev *sd,
max_h = CIF_ISP_INPUT_H_MAX_V21;
break;
case ISP_V30:
max_w = dev->hw_dev->is_unite ?
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
max_h = dev->hw_dev->is_unite ?
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
break;
case ISP_V32:
max_w = CIF_ISP_INPUT_W_MAX_V32;
max_h = CIF_ISP_INPUT_H_MAX_V32;
max_w = dev->hw_dev->unite ?
CIF_ISP_INPUT_W_MAX_V32_UNITE : CIF_ISP_INPUT_W_MAX_V32;
max_h = dev->hw_dev->unite ?
CIF_ISP_INPUT_H_MAX_V32_UNITE : CIF_ISP_INPUT_H_MAX_V32;
break;
case ISP_V32_L:
max_w = CIF_ISP_INPUT_W_MAX_V32_L;
@@ -2953,7 +2974,7 @@ static void rkisp_rx_qbuf_online(struct rkisp_stream *stream,
u32 val = pool->buf.buff_addr[RKISP_PLANE_Y];
rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
if (dev->hw_dev->is_unite) {
if (dev->hw_dev->unite == ISP_UNITE_TWO) {
u32 offs = stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL;
if (stream->memory)
@@ -3426,7 +3447,7 @@ static int rkisp_get_info(struct rkisp_device *dev, struct rkisp_isp_info *info)
if (dev->is_bigmode)
mode |= RKISP_ISP_BIGMODE;
info->mode = mode;
if (dev->hw_dev->is_unite)
if (dev->hw_dev->unite)
info->act_width = in_crop->width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
else
info->act_width = in_crop->width;
@@ -3713,7 +3734,7 @@ static void rkisp_isp_sd_init_default_fmt(struct rkisp_isp_subdev *isp_sd)
struct ispsd_in_fmt *in_fmt = &isp_sd->in_fmt;
struct ispsd_out_fmt *out_fmt = &isp_sd->out_fmt;
*in_fmt = rkisp_isp_input_formats[0];
*in_fmt = rkisp_isp_input_formats[8];
in_frm->width = RKISP_DEFAULT_WIDTH;
in_frm->height = RKISP_DEFAULT_HEIGHT;
in_frm->code = in_fmt->mbus_code;
@@ -4040,7 +4061,7 @@ void rkisp_isp_isr(unsigned int isp_mis,
struct rkisp_device *dev)
{
struct rkisp_hw_dev *hw = dev->hw_dev;
void __iomem *base = !hw->is_unite ?
void __iomem *base = hw->unite != ISP_UNITE_TWO ?
hw->base_addr : hw->base_next_addr;
unsigned int isp_mis_tmp = 0;
unsigned int isp_err = 0;
@@ -4061,7 +4082,7 @@ void rkisp_isp_isr(unsigned int isp_mis,
if (isp3a_mis & ISP2X_3A_RAWAE_BIG && dev->params_vdev.rdbk_times > 0)
writel(BIT(31), base + RAWAE_BIG1_BASE + RAWAE_BIG_CTRL);
if (hw->is_unite) {
if (hw->unite == ISP_UNITE_TWO) {
u32 val = rkisp_read(dev, ISP3X_ISP_RIS, true);
if (val) {
@@ -4097,7 +4118,7 @@ void rkisp_isp_isr(unsigned int isp_mis,
*/
if (!dev->hw_dev->is_single) {
writel(0, hw->base_addr + ISP_3DLUT_UPDATE);
if (hw->is_unite)
if (hw->unite == ISP_UNITE_TWO)
writel(0, hw->base_next_addr + ISP_3DLUT_UPDATE);
}
rkisp_stats_rdbk_enable(&dev->stats_vdev, true);

2
drivers/media/platform/rockchip/isp/rkisp.h
View File

@@ -57,6 +57,8 @@
#define CIF_ISP_INPUT_H_MAX_V30_UNITE 6144
#define CIF_ISP_INPUT_W_MAX_V32 3072
#define CIF_ISP_INPUT_H_MAX_V32 1728
#define CIF_ISP_INPUT_W_MAX_V32_UNITE 3840
#define CIF_ISP_INPUT_H_MAX_V32_UNITE 2160
#define CIF_ISP_INPUT_W_MAX_V32_L 4224
#define CIF_ISP_INPUT_H_MAX_V32_L 3136
#define CIF_ISP_INPUT_W_MIN 272

6
drivers/pci/controller/dwc/pcie-dw-rockchip.c
View File

@@ -202,6 +202,7 @@ struct rk_pcie {
struct workqueue_struct *hot_rst_wq;
struct work_struct hot_rst_work;
u32 comp_prst[2];
u32 intx;
};
enum dw_pcie_as_type {
@@ -2339,6 +2340,8 @@ no_l2:
phy_power_off(rk_pcie->phy);
phy_exit(rk_pcie->phy);
rk_pcie->intx = rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_INTR_MASK_LEGACY);
clk_bulk_disable_unprepare(rk_pcie->clk_cnt, rk_pcie->clks);
rk_pcie->in_suspend = true;
@@ -2403,6 +2406,9 @@ static int __maybe_unused rockchip_dw_pcie_resume(struct device *dev)
if (std_rc)
dw_pcie_setup_rc(&rk_pcie->pci->pp);
rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_INTR_MASK_LEGACY,
rk_pcie->intx | 0xffff0000);
ret = rk_pcie_establish_link(rk_pcie->pci);
if (ret) {
dev_err(dev, "failed to establish pcie link\n");

1
drivers/rpmsg/rockchip_rpmsg_test.c
View File

@@ -92,6 +92,7 @@ static void rockchip_rpmsg_test_remove(struct rpmsg_device *rp)
static struct rpmsg_device_id rockchip_rpmsg_test_id_table[] = {
{ .name = "rpmsg-ap3-ch0" },
{ .name = "rpmsg-mcu0-test" },
{ /* sentinel */ },
};

1
include/soc/rockchip/rockchip_sip.h
View File

@@ -20,6 +20,7 @@
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL 0x0a
#define ROCKCHIP_SIP_CONFIG_DRAM_DEBUG 0x0b
#define ROCKCHIP_SIP_CONFIG_MCU_START 0x0c
#define ROCKCHIP_SIP_CONFIG_DRAM_ECC 0x0d
#define ROCKCHIP_SIP_CONFIG_DRAM_GET_FREQ_INFO 0x0e
#define ROCKCHIP_SIP_CONFIG_DRAM_ADDRMAP_GET 0x10

6
sound/soc/codecs/Kconfig
View File

@@ -239,6 +239,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_TAS5720
imply SND_SOC_TAS6424
imply SND_SOC_TDA7419
imply SND_SOC_TDA7803
imply SND_SOC_TFA9879
imply SND_SOC_TFA989X
imply SND_SOC_TLV320ADC3XXX
@@ -1698,6 +1699,11 @@ config SND_SOC_TDA7419
depends on I2C
select REGMAP_I2C
config SND_SOC_TDA7803
tristate "ST TDA7803 audio processor"
depends on I2C
select REGMAP_I2C
config SND_SOC_TFA9879
tristate "NXP Semiconductors TFA9879 amplifier"
depends on I2C

2
sound/soc/codecs/Makefile
View File

@@ -269,6 +269,7 @@ snd-soc-tas5720-objs := tas5720.o
snd-soc-tas5805m-objs := tas5805m.o
snd-soc-tas6424-objs := tas6424.o
snd-soc-tda7419-objs := tda7419.o
snd-soc-tda7803-objs := tda7803.o
snd-soc-tas2770-objs := tas2770.o
snd-soc-tfa9879-objs := tfa9879.o
snd-soc-tfa989x-objs := tfa989x.o
@@ -642,6 +643,7 @@ obj-$(CONFIG_SND_SOC_TAS5720) += snd-soc-tas5720.o
obj-$(CONFIG_SND_SOC_TAS5805M) += snd-soc-tas5805m.o
obj-$(CONFIG_SND_SOC_TAS6424) += snd-soc-tas6424.o
obj-$(CONFIG_SND_SOC_TDA7419) += snd-soc-tda7419.o
obj-$(CONFIG_SND_SOC_TDA7803) += snd-soc-tda7803.o
obj-$(CONFIG_SND_SOC_TAS2770) += snd-soc-tas2770.o
obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o
obj-$(CONFIG_SND_SOC_TFA989X) += snd-soc-tfa989x.o

171
sound/soc/codecs/tda7803.c Normal file
View File

@@ -0,0 +1,171 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/regmap.h>
#include <sound/core.h>
#include <sound/control.h>
#include <sound/soc.h>
#include "tda7803.h"
#define TDA7803_SAMPLE_RATE \
(SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
struct tda7803_priv {
struct regmap *regmap;
u32 input_format;
};
static int tda7803_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct tda7803_priv *tda7803 = snd_soc_component_get_drvdata(component);
struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
int val = 0;
snd_soc_component_write(component, TDA7803_REG2, DIGITAL_MUTE_OFF |
CH2_4_UMUTE | CH1_3_UMUTE |
MUTE_TIME_SETTING_1_45MS);
snd_soc_component_write(component, TDA7803_REG7, AMPLIEFIR_SWITCH_ON);
switch (tda7803->input_format) {
case 0:
val = INPUT_FORMAT_TDM_8CH_MODEL1;
break;
case 1:
val = INPUT_FORMAT_TDM_8CH_MODEL2;
break;
default:
return -EINVAL;
}
snd_soc_dai_set_fmt(codec_dai, val);
return 0;
}
static int tda7803_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
int val = 0;
switch (params_rate(params)) {
case 44100:
val = SAMPLE_FREQUENCY_RANGE_44100HZ;
break;
case 48000:
val = SAMPLE_FREQUENCY_RANGE_48000HZ;
break;
case 96000:
val = SAMPLE_FREQUENCY_RANGE_96000HZ;
break;
case 192000:
val = SAMPLE_FREQUENCY_RANGE_192000HZ;
break;
default:
return -EINVAL;
}
snd_soc_component_write(component, TDA7803_REG3, val);
return 0;
}
static int tda7803_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
{
struct snd_soc_component *component = dai->component;
snd_soc_component_write(component, TDA7803_REG3, fmt);
return 0;
}
static const struct snd_soc_dai_ops tda7803_ops = {
.startup = tda7803_startup,
.hw_params = tda7803_hw_params,
.set_fmt = tda7803_set_fmt,
};
static struct snd_soc_dai_driver tda7803_dai = {
.name = "tda7803-hifi",
.playback = {
.stream_name = "Playback",
.channels_min = 2,
.channels_max = 8,
.rates = TDA7803_SAMPLE_RATE,
.formats = SNDRV_PCM_FMTBIT_S32_LE |
SNDRV_PCM_FMTBIT_S24_LE |
SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &tda7803_ops,
};
static const struct snd_soc_component_driver soc_codec_dev_tda7803 = {
.name = "tda7803",
};
static const struct regmap_config tda7803_i2c_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = TDA7803_REGMAX,
.cache_type = REGCACHE_RBTREE,
};
static int tda7803_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
struct tda7803_priv *tda7803;
int val;
tda7803 = devm_kzalloc(&i2c->dev, sizeof(*tda7803), GFP_KERNEL);
if (!tda7803)
return -ENOMEM;
i2c_set_clientdata(i2c, tda7803);
tda7803->regmap = devm_regmap_init_i2c(i2c, &tda7803_i2c_regmap);
if (IS_ERR(tda7803->regmap))
return PTR_ERR(tda7803->regmap);
if (!device_property_read_u32(&i2c->dev, "st,tda7803-format", &val))
tda7803->input_format = val;
return devm_snd_soc_register_component(&i2c->dev,
&soc_codec_dev_tda7803,
&tda7803_dai, 1);
}
static const struct i2c_device_id tda7803_i2c_id[] = {
{ "tda7803", 0 },
{ }
};
MODULE_DEVICE_TABLE(i2c, tda7803_i2c_id);
static const struct of_device_id tda7803_of_match[] = {
{ .compatible = "st,tda7803" },
{ },
};
static struct i2c_driver tda7803_i2c_driver = {
.driver = {
.name = "tda7803",
.of_match_table = of_match_ptr(tda7803_of_match),
},
.probe = tda7803_i2c_probe,
.id_table = tda7803_i2c_id,
};
module_i2c_driver(tda7803_i2c_driver);
MODULE_AUTHOR("Jun Zeng <jun.zeng@rock-chips.com>");
MODULE_DESCRIPTION("TDA7803 audio processor driver");
MODULE_LICENSE("GPL");

138
sound/soc/codecs/tda7803.h Normal file
View File

@@ -0,0 +1,138 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*
*/
#ifndef __TDA7803_H__
#define __TDA7803_H__
/* tda7803 registers space*/
#define TDA7803_REG0 (0x00)
#define CH1_AMP_SBI_MODE (0x00 << 0)
#define CH1_AMP_ABI_MODE (0x01 << 0)
#define CH2_AMP_SBI_MODE (0x00 << 1)
#define CH2_AMP_ABI_MODE (0x01 << 1)
#define CH3_AMP_SBI_MODE (0x00 << 2)
#define CH3_AMP_ABI_MODE (0x01 << 2)
#define CH4_AMP_SBI_MODE (0x00 << 3)
#define CH4_AMP_ABI_MODE (0x01 << 3)
#define CH1_TRI_MODE_OFF (0x00 << 4)
#define CH1_TRI_MODE_ON (0x01 << 4)
#define CH2_TRI_MODE_OFF (0x00 << 5)
#define CH2_TRI_MODE_ON (0x01 << 5)
#define CH3_TRI_MODE_OFF (0x00 << 6)
#define CH3_TRI_MODE_ON (0x01 << 6)
#define CH4_TRI_MODE_OFF (0x00 << 7)
#define CH4_TRI_MODE_ON (0x01 << 7)
#define TDA7803_REG1 (0x01)
#define CH2_4_GAIN_GV1 (0x00 << 0)
#define CH2_4_GAIN_GV2 (0x01 << 0)
#define CH2_4_GAIN_GV3 (0x02 << 0)
#define CH2_4_GAIN_GV4 (0x03 << 0)
#define CH1_3_GAIN_GV1 (0x00 << 2)
#define CH1_3_GAIN_GV2 (0x01 << 2)
#define CH1_3_GAIN_GV3 (0x02 << 2)
#define CH1_3_GAIN_GV4 (0x03 << 2)
#define GAIN_SELECT_NO (0x00 << 4)
#define GAIN_SELECT_6DB (0x01 << 4)
#define GAIN_SELECT_12DB (0x02 << 4)
#define GAIN_SELECT_NOT_USED (0x03 << 4)
#define IMPEDANCE_OPTIMIZER_REAR_2OHM (0x00 << 6)
#define IMPEDANCE_OPTIMIZER_REAR_4OHM (0x01 << 6)
#define IMPEDANCE_OPTIMIZER_FRONT_2OHM (0x00 << 7)
#define IMPEDANCE_OPTIMIZER_FRONT_4OHM (0x01 << 7)
#define TDA7803_REG2 (0x02)
#define LOW_BATTERY_MUTE_THRESHOLD_1 (0x00 << 0)
#define LOW_BATTERY_MUTE_THRESHOLD_2 (0x01 << 0)
#define DIGITAL_MUTE_ON (0x00 << 2)
#define DIGITAL_MUTE_OFF (0x01 << 2)
#define CH2_4_MUTE (0x00 << 3)
#define CH2_4_UMUTE (0x01 << 3)
#define CH1_3_MUTE (0x00 << 4)
#define CH1_3_UMUTE (0x01 << 4)
#define MUTE_TIME_SETTING_1_45MS (0x00 << 5)
#define MUTE_TIME_SETTING_5_8MS (0x01 << 5)
#define MUTE_TIME_SETTING_11_6MS (0x02 << 5)
#define MUTE_TIME_SETTING_23_2MS (0x03 << 5)
#define MUTE_TIME_SETTING_46_4MS (0x04 << 5)
#define MUTE_TIME_SETTING_92_8MS (0x05 << 5)
#define MUTE_TIME_SETTING_185_5MS (0x06 << 5)
#define MUTE_TIME_SETTING_371_1MS (0x07 << 5)
#define TDA7803_REG3 (0x03)
#define HIGH_PASS_FILTER_DISABLE (0x00 << 0)
#define HIGH_PASS_FILTER_ENABLE (0x01 << 0)
#define INPUT_OFFSET_DETECTION_DIS (0x00 << 1)
#define INPUT_OFFSET_DETECTION_EN (0x01 << 1)
#define NOISE_GATING_FUNCTION_EN (0x00 << 2)
#define NOISE_GATING_FUNCTION_DIS (0x01 << 2)
#define INPUT_FORMAT_I2S_STD (0x00 << 3)
#define INPUT_FORMAT_TDM_4CH (0x01 << 3)
#define INPUT_FORMAT_TDM_8CH_MODEL1 (0x02 << 3)
#define INPUT_FORMAT_TDM_8CH_MODEL2 (0x03 << 3)
#define INPUT_FORMAT_TDM_16CH_MODEL1 (0x04 << 3)
#define INPUT_FORMAT_TDM_16CH_MODEL2 (0x05 << 3)
#define INPUT_FORMAT_TDM_16CH_MODEL3 (0x06 << 3)
#define INPUT_FORMAT_TDM_16CH_MODEL4 (0x07 << 3)
#define SAMPLE_FREQUENCY_RANGE_44100HZ (0x00 << 6)
#define SAMPLE_FREQUENCY_RANGE_48000HZ (0x01 << 6)
#define SAMPLE_FREQUENCY_RANGE_96000HZ (0x02 << 6)
#define SAMPLE_FREQUENCY_RANGE_192000HZ (0x03 << 6)
#define TDA7803_REG4 (0x04)
#define DIAGNOSTIC_MODE_DISABLE (0x00 << 0)
#define DIAGNOSTIC_MODE_ENABLE (0x01 << 0)
#define CH2_4_SPEAKER_MODE (0x00 << 1)
#define CH2_4_LINE_DRIVER_MODE (0x01 << 1)
#define CH1_3_SPEAKER_MODE (0x00 << 2)
#define CH1_3_LINE_DRIVER_MODE (0x01 << 2)
#define DIAGNOSTIC_DISABLE (0X00 << 3)
#define DIAGNOSTIC_ENABLE (0X01 << 3)
#define DIAGNOSTIC_CURRENT_THRESHOLD_HIGH (0X00 << 4)
#define DIAGNOSTIC_CURRENT_THRESHOLD_LOW (0X01 << 4)
#define OFFSET_INFORMATION_YES (0X00 << 5)
#define OFFSET_INFORMATION_NO (0X01 << 5)
#define SHORT_FAULT_INFORMATION_YES (0X00 << 6)
#define SHORT_FAULT_INFORMATION_NO (0X01 << 6)
#define TDA7803_REG5 (0x05)
#define CAPABILITY_ENHANCER_DISABLE (0x00 << 1)
#define CAPABILITY_ENHANCER_ENABLE (0x0F << 1)
#define THERMAL_THRESHOLD_DEFAULT (0x00 << 6)
#define THERMAL_THRESHOLD_TW_NEGATIVE_10 (0x01 << 6)
#define THERMAL_THRESHOLD_TW_NEGATIVE_20 (0x02 << 6)
#define TDA7803_REG6 (0x06)
#define PARALLEL_MODE_CONFIG_MODE_1 (0x00 << 2)
#define PARALLEL_MODE_CONFIG_MODE_2 (0x01 << 2)
#define PARALLEL_MODE_CONFIG_MODE_3 (0x02 << 2)
#define PARALLEL_MODE_CONFIG_MODE_4 (0x03 << 2)
#define DIAGNOSITC_PULSE_STRETCH_MODE_1 (0x00 << 5)
#define DIAGNOSITC_PULSE_STRETCH_MODE_2 (0x01 << 5)
#define DIAGNOSITC_PULSE_STRETCH_MODE_3 (0x02 << 5)
#define DIAGNOSITC_PULSE_STRETCH_MODE_4 (0x03 << 5)
#define DIAGNOSITC_PULSE_STRETCH_MODE_5 (0x04 << 5)
#define DIAGNOSITC_PULSE_STRETCH_DEFAULT (0x05 << 5)
#define TDA7803_REG7 (0x07)
#define AMPLIEFIR_SWITCH_OFF (0x00 << 0)
#define AMPLIEFIR_SWITCH_ON (0x01 << 0)
#define CLIPP_LEVEL_1_REAR_CHANNELS2_4 (0x00 << 1)
#define CLIPP_LEVEL_2_REAR_CHANNELS2_4 (0x01 << 1)
#define CLIPP_LEVEL_3_REAR_CHANNELS2_4 (0x02 << 1)
#define NOT_CLIPP_FOR_REAR_CHANNELS2_4 (0x03 << 1)
#define CLIPP_LEVEL_1_REAR_CHANNELS1_3 (0x00 << 3)
#define CLIPP_LEVEL_2_REAR_CHANNELS1_3 (0x01 << 3)
#define CLIPP_LEVEL_3_REAR_CHANNELS1_3 (0x02 << 3)
#define NOT_CLIPP_FOR_REAR_CHANNELS1_3 (0x03 << 3)
#define TEMPERATURE_WARNING_TW1 (0x00 << 5)
#define TEMPERATURE_WARNING_TW2 (0x01 << 5)
#define TEMPERATURE_WARNING_TW3 (0x02 << 5)
#define TEMPERATURE_WARNING_TW4 (0x03 << 5)
#define NOT_TEMPERATURE_WARNING (0x04 << 5)
#define TDA7803_REGMAX (0x08)
#endif /* __TDA7803_H__ */