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rk3026: set gpll=768M, cpll=594M as rk31xx

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This commit is contained in:
chenxing
2013-08-02 17:20:51 +08:00
parent 2aff25e8de
commit df8225bff9
2 changed files with 28 additions and 6 deletions
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7
arch/arm/mach-rk2928/include/mach/board.h
View File

@@ -39,6 +39,7 @@ enum _periph_pll {
periph_pll_1485mhz = 148500000,
periph_pll_297mhz = 297000000,
periph_pll_300mhz = 300000000,
periph_pll_768mhz = 768000000,
periph_pll_1188mhz = 1188000000, /* for box*/
};
enum _codec_pll {
@@ -47,6 +48,7 @@ enum _codec_pll {
codec_pll_456mhz = 456000000,
codec_pll_504mhz = 504000000,
codec_pll_552mhz = 552000000, /* for HDMI */
codec_pll_594mhz = 594000000, /* for HDMI */
codec_pll_600mhz = 600000000,
codec_pll_742_5khz = 742500000,
codec_pll_798mhz = 798000000,
@@ -61,8 +63,13 @@ enum _codec_pll {
#define CLK_FLG_MAX_I2S_49152KHZ (1<<4)
#define RK30_CLOCKS_DEFAULT_FLAGS (CLK_FLG_MAX_I2S_12288KHZ/*|CLK_FLG_EXT_27MHZ*/)
#if defined(CONFIG_ARCH_RK3026)
#define periph_pll_default periph_pll_768mhz
#define codec_pll_default codec_pll_594mhz
#else
#define periph_pll_default periph_pll_297mhz
#define codec_pll_default codec_pll_798mhz
#endif
//#define codec_pll_default codec_pll_1064mhz

27
arch/arm/mach-rk3026/clock_data.c
View File

@@ -174,11 +174,13 @@ static const struct apll_clk_set apll_clks[] = {
}
static const struct pll_clk_set cpll_clks[] = {
_PLL_SET_CLKS(798000, 4, 133, 1, 1, 1, 0),
_PLL_SET_CLKS(594000, 2, 99, 2, 1, 1, 0),
_PLL_SET_CLKS(1064000, 3, 133, 1, 1, 1, 0),
};
static const struct pll_clk_set gpll_clks[] = {
_PLL_SET_CLKS(297000, 2, 99, 4, 1, 1, 0),
_PLL_SET_CLKS(768000, 1, 32, 1, 1, 1, 0),
};
static u32 clk_gcd(u32 numerator, u32 denominator)
@@ -347,7 +349,7 @@ static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
{
u32 div = 0;
for (div = 0; div < clk->div_max; div++) {
for (div = 0; div <= clk->div_max; div++) {
u32 new_rate = clk->parent->rate / (div + 1);
if (new_rate <= rate) {
set_cru_bits_w_msk(div, clk->div_mask, clk->div_shift, clk->clksel_con);
@@ -370,7 +372,7 @@ static int clksel_set_rate_freediv(struct clk *clk, unsigned long rate)
static int clksel_set_rate_shift(struct clk *clk, unsigned long rate)
{
u32 shift;
for (shift = 0; (1 << shift) < clk->div_max; shift++) {
for (shift = 0; (1 << shift) <= clk->div_max; shift++) {
u32 new_rate = clk->parent->rate >> shift;
if (new_rate <= rate) {
set_cru_bits_w_msk(shift, clk->div_mask, clk->div_shift, clk->clksel_con);
@@ -405,7 +407,7 @@ static int clksel_set_rate_shift_2(struct clk *clk, unsigned long rate)
static int clksel_set_rate_even(struct clk *clk, unsigned long rate)
{
u32 div = 0, new_rate = 0;
for (div = 1; div < clk->div_max; div++) {
for (div = 1; div <= clk->div_max; div++) {
if (div >= 3 && div % 2 != 0)
continue;
new_rate = clk->parent->rate / div;
@@ -2655,9 +2657,16 @@ static void periph_clk_set_init(void)
pclk_p = aclk_p >> 2;
break;
case 1188*MHZ:
aclk_p = aclk_p >> 3; // 0
aclk_p = gpll_rate >> 3; // 0
hclk_p = aclk_p >> 1;
pclk_p = aclk_p >> 2;
break;
case 768 * MHZ:
aclk_p = gpll_rate >> 2;
hclk_p = aclk_p >> 1;
pclk_p = aclk_p >> 2;
break;
case 297 * MHZ:
aclk_p = gpll_rate >> 0;
@@ -2693,6 +2702,12 @@ static void cpu_axi_init(void)
pclk_cpu_rate = aclk_cpu_rate >> 2;
break;
case 768 * MHZ:
aclk_cpu_rate = gpll_rate >> 2;
hclk_cpu_rate = aclk_cpu_rate >> 1;
pclk_cpu_rate = aclk_cpu_rate >> 2;
break;
default:
aclk_cpu_rate = 150 * MHZ;
hclk_cpu_rate = 150 * MHZ;
@@ -2701,8 +2716,8 @@ static void cpu_axi_init(void)
}
clk_set_parent_nolock(&clk_cpu_div, &clk_cpu_gpll);
clk_set_rate_nolock(&clk_cpu_div, gpll_rate);
clk_set_rate_nolock(&aclk_cpu_pre, aclk_cpu_rate);
clk_set_rate_nolock(&clk_cpu_div, aclk_cpu_rate);
//clk_set_rate_nolock(&aclk_cpu_pre, aclk_cpu_rate);
clk_set_rate_nolock(&hclk_cpu_pre, hclk_cpu_rate);
clk_set_rate_nolock(&pclk_cpu_pre, pclk_cpu_rate);
}