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drm/rockchip: dsi2: use mode->crtc_clock instead of mode->clock to calculate

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the mode->clock is the requested pixel clock which may different from
the actual allocated mode->crtc_clock.

example:
cat /d/dri/0/summary
Video Port3: ACTIVE
    Connector: DSI-1
        bus_format[100a]: RGB888_1X24
        overlay_mode[0] output_mode[0] color_space[0], eotf:0
    Display mode: 1920x384p60
        clk[47400] real_clk[46875] type[48] flag[a]
        H: 1920 1946 1958 1974
        V: 384 392 395 400

Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I63a5c7b83b96174c2044e4bde969d74cff8af0b7
This commit is contained in:
Guochun Huang
2022-04-29 11:43:06 +08:00
committed by Tao Huang
parent 33abd5ac99
commit dfa43c60cd
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
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@@ -501,7 +501,7 @@ static void dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2)
else
lane_rate = 80 * USEC_PER_SEC;
} else {
tmp = (u64)mode->clock * 1000 * bpp;
tmp = (u64)mode->crtc_clock * 1000 * bpp;
do_div(tmp, lanes);
/*
@@ -610,7 +610,7 @@ static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2)
phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);
/* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */
pixel_clk = mode->clock * MSEC_PER_SEC;
pixel_clk = mode->crtc_clock * MSEC_PER_SEC;
ipi_clk = pixel_clk / 4;
tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, ipi_clk);
@@ -749,7 +749,7 @@ static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2)
hbp = mode->htotal - mode->hsync_end;
hline = mode->htotal;
pixel_clk = mode->clock * MSEC_PER_SEC;
pixel_clk = mode->crtc_clock * MSEC_PER_SEC;
if (dsi2->c_option)
phy_hs_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 7);