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ge2d: add ge2d driver for axg bringup

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PD#146096: ge2d: add ge2d driver for axg bringup

Change-Id: Iac19fca564ebb564372445c6011143968f2c9739
Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
This commit is contained in:
Pengcheng Chen
2017-06-06 13:13:19 +08:00
committed by Jianxin Pan
parent 7996a06730
commit dfcd0d80a0
11 changed files with 640 additions and 228 deletions
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15
arch/arm64/boot/dts/amlogic/axg_pxp.dts
View File

@@ -230,6 +230,21 @@
logo_addr = "0x3e000000";
pxp_mode = <1>; /** 0:normal mode 1:pxp mode */
};
ge2d {
compatible = "amlogic, ge2d";
dev_name = "ge2d";
status = "okay";
interrupts = <0 150 1>;
interrupt-names = "ge2d";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_GE2D_GATE>,
<&clkc CLKID_G2D>;
clock-names = "clk_vapb_0",
"clk_ge2d",
"clk_ge2d_gate";
reg = <0x0 0xff940000 0x0 0x10000>;
};
}; /* end of / */
&spicc_a{

28
arch/arm64/boot/dts/amlogic/axg_s400.dts
View File

@@ -60,9 +60,9 @@
//reg = <0x0 0x3e000000 0x0 0x1f00000>;
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x2000000>;
size = <0x0 0x1000000>;
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x3e000000 0x0 0x2000000>;
alloc-ranges = <0x0 0x3f000000 0x0 0x1000000>;
};
};
mtd_nand {
@@ -735,6 +735,7 @@
mask = <4>;
};
};
meson-fb {
compatible = "amlogic, meson-fb";
memory-region = <&fb_reserved>;
@@ -743,16 +744,31 @@
interrupts = <0 3 1
0 89 1>;
interrupt-names = "viu-vsync", "rdma";
mem_size = <0x006AF000 0x01851000 0x00000000>;
mem_size = <0x00300000 0x600000 0x00000000>;
/* uboot logo,fb0/fb1 memory size */
display_mode_default = "1080p60hz";
scale_mode = <0>;
/** 0:VPU free scale 1:OSD free scale 2:OSD super scale */
display_size_default = <1920 1080 1920 3240 32>;
/*1920*1080*4*3 = 0x17BB000*/
logo_addr = "0x3e000000";
display_size_default = <768 1024 768 2048 32>;
/*768*1024*4*2 = 0x600000*/
logo_addr = "0x3f000000";
pxp_mode = <0>; /** 0:normal mode 1:pxp mode */
};
ge2d {
compatible = "amlogic, ge2d";
dev_name = "ge2d";
status = "okay";
interrupts = <0 150 1>;
interrupt-names = "ge2d";
clocks = <&clkc CLKID_VAPB_MUX>,
<&clkc CLKID_GE2D_GATE>,
<&clkc CLKID_G2D>;
clock-names = "clk_vapb_0",
"clk_ge2d",
"clk_ge2d_gate";
reg = <0x0 0xff940000 0x0 0x10000>;
};
}; /* end of / */
/* Audio Related start */

46
drivers/amlogic/media/common/ge2d/blend.c
View File

@@ -14,8 +14,11 @@
* more details.
*
*/
/* Linux Headers */
#include <linux/types.h>
/* Amlogic Headers */
#include <linux/amlogic/cpu_version.h>
#include <linux/amlogic/media/ge2d/ge2d.h>
void blend(struct ge2d_context_s *wq,
@@ -62,12 +65,13 @@ void blend(struct ge2d_context_s *wq,
ge2d_cmd_cfg->alpha_src_blend_factor = (op >> 4) & 0xf;
ge2d_cmd_cfg->alpha_dst_blend_factor = (op >> 0) & 0xf;
if (ge2d_cmd_cfg->color_blend_mode >= BLENDOP_LOGIC) {
ge2d_cmd_cfg->color_logic_op =
ge2d_cmd_cfg->color_blend_mode - BLENDOP_LOGIC;
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
if (get_cpu_type() != MESON_CPU_MAJOR_ID_AXG) {
if (ge2d_cmd_cfg->color_blend_mode >= BLENDOP_LOGIC) {
ge2d_cmd_cfg->color_logic_op =
ge2d_cmd_cfg->color_blend_mode - BLENDOP_LOGIC;
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
}
}
ge2d_cmd_cfg->alpha_blend_mode = (op >> 8) & 0xff;
if (ge2d_cmd_cfg->alpha_blend_mode >= BLENDOP_LOGIC) {
ge2d_cmd_cfg->alpha_logic_op =
@@ -124,13 +128,13 @@ void blend_noblk(struct ge2d_context_s *wq,
ge2d_cmd_cfg->color_dst_blend_factor = (op >> 16) & 0xf;
ge2d_cmd_cfg->alpha_src_blend_factor = (op >> 4) & 0xf;
ge2d_cmd_cfg->alpha_dst_blend_factor = (op >> 0) & 0xf;
if (ge2d_cmd_cfg->color_blend_mode >= BLENDOP_LOGIC) {
ge2d_cmd_cfg->color_logic_op =
ge2d_cmd_cfg->color_blend_mode - BLENDOP_LOGIC;
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
if (get_cpu_type() != MESON_CPU_MAJOR_ID_AXG) {
if (ge2d_cmd_cfg->color_blend_mode >= BLENDOP_LOGIC) {
ge2d_cmd_cfg->color_logic_op =
ge2d_cmd_cfg->color_blend_mode - BLENDOP_LOGIC;
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
}
}
ge2d_cmd_cfg->alpha_blend_mode = (op >> 8) & 0xff;
if (ge2d_cmd_cfg->alpha_blend_mode >= BLENDOP_LOGIC) {
ge2d_cmd_cfg->alpha_logic_op =
@@ -187,10 +191,12 @@ void blend_noalpha(struct ge2d_context_s *wq,
ge2d_cmd_cfg->alpha_src_blend_factor = (op >> 4) & 0xf;
ge2d_cmd_cfg->alpha_dst_blend_factor = (op >> 0) & 0xf;
if (ge2d_cmd_cfg->color_blend_mode >= BLENDOP_LOGIC) {
ge2d_cmd_cfg->color_logic_op =
ge2d_cmd_cfg->color_blend_mode - BLENDOP_LOGIC;
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
if (get_cpu_type() != MESON_CPU_MAJOR_ID_AXG) {
if (ge2d_cmd_cfg->color_blend_mode >= BLENDOP_LOGIC) {
ge2d_cmd_cfg->color_logic_op =
ge2d_cmd_cfg->color_blend_mode - BLENDOP_LOGIC;
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
}
}
ge2d_cmd_cfg->alpha_blend_mode = OPERATION_LOGIC;
ge2d_cmd_cfg->alpha_logic_op = LOGIC_OPERATION_SET;
@@ -246,10 +252,12 @@ void blend_noalpha_noblk(struct ge2d_context_s *wq,
ge2d_cmd_cfg->alpha_src_blend_factor = (op >> 4) & 0xf;
ge2d_cmd_cfg->alpha_dst_blend_factor = (op >> 0) & 0xf;
if (ge2d_cmd_cfg->color_blend_mode >= BLENDOP_LOGIC) {
ge2d_cmd_cfg->color_logic_op =
ge2d_cmd_cfg->color_blend_mode - BLENDOP_LOGIC;
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
if (get_cpu_type() != MESON_CPU_MAJOR_ID_AXG) {
if (ge2d_cmd_cfg->color_blend_mode >= BLENDOP_LOGIC) {
ge2d_cmd_cfg->color_logic_op =
ge2d_cmd_cfg->color_blend_mode - BLENDOP_LOGIC;
ge2d_cmd_cfg->color_blend_mode = OPERATION_LOGIC;
}
}
ge2d_cmd_cfg->alpha_blend_mode = OPERATION_LOGIC;
ge2d_cmd_cfg->alpha_logic_op = LOGIC_OPERATION_SET;

63
drivers/amlogic/media/common/ge2d/ge2d_hw.c
View File

@@ -26,6 +26,11 @@
#include "ge2d_log.h"
#include "ge2d_io.h"
#include "ge2d_reg.h"
#define GE2D_DST1_INDEX 0
#define GE2D_SRC1_INDEX 1
#define GE2D_SRC2_INDEX 2
static const unsigned int filt_coef_gau1[] = { /* gau1+phase */
0x20402000,
0x203f2001,
@@ -279,6 +284,20 @@ static const unsigned int filt_coef3[] = { /* 3 point triangle */
0x00
};
void ge2d_canv_config(u32 index, u32 addr, u32 stride)
{
ge2d_log_dbg("ge2d_canv_config:index=%d,addr=%x,stride=%d\n",
index, addr, stride);
if (get_cpu_type() == MESON_CPU_MAJOR_ID_AXG) {
if (index <= 2) {
ge2d_reg_write(GE2D_DST1_BADDR_CTRL
+ index * 2, ((addr + 7) >> 3));
ge2d_reg_write(GE2D_DST1_STRIDE_CTRL
+ index * 2, ((stride + 7) >> 3));
}
}
}
void ge2d_set_src1_data(struct ge2d_src1_data_s *cfg)
{
ge2d_reg_set_bits(GE2D_GEN_CTRL1, cfg->urgent_en, 10, 1);
@@ -287,10 +306,16 @@ void ge2d_set_src1_data(struct ge2d_src1_data_s *cfg)
ge2d_reg_set_bits(GE2D_GEN_CTRL1, cfg->ddr_burst_size_cb, 18, 2);
ge2d_reg_set_bits(GE2D_GEN_CTRL1, cfg->ddr_burst_size_cr, 16, 2);
ge2d_reg_write(GE2D_SRC1_CANVAS,
((cfg->canaddr & 0xff) << 24) |
(((cfg->canaddr >> 8) & 0xff) << 16) |
(((cfg->canaddr >> 16) & 0xff) << 8));
if (get_cpu_type() == MESON_CPU_MAJOR_ID_AXG) {
ge2d_canv_config(GE2D_SRC1_INDEX,
cfg->phy_addr,
cfg->stride);
} else {
ge2d_reg_write(GE2D_SRC1_CANVAS,
((cfg->canaddr & 0xff) << 24) |
(((cfg->canaddr >> 8) & 0xff) << 16) |
(((cfg->canaddr >> 16) & 0xff) << 8));
}
ge2d_reg_set_bits(GE2D_GEN_CTRL0,
((cfg->x_yc_ratio << 1) | cfg->y_yc_ratio),
@@ -301,6 +326,13 @@ void ge2d_set_src1_data(struct ge2d_src1_data_s *cfg)
ge2d_reg_set_bits(GE2D_GEN_CTRL2, cfg->format, 0, 2);
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXL)
ge2d_reg_set_bits(GE2D_GEN_CTRL2, cfg->deep_color, 2, 1);
if (get_cpu_type() == MESON_CPU_MAJOR_ID_AXG) {
ge2d_reg_set_bits(GE2D_GEN_CTRL2, cfg->mult_rounding, 18, 1);
ge2d_reg_set_bits(GE2D_GEN_CTRL2, cfg->alpha_conv_mode0, 31, 1);
ge2d_reg_set_bits(GE2D_GEN_CTRL2, cfg->alpha_conv_mode1, 10, 1);
ge2d_reg_set_bits(GE2D_GEN_CTRL2, cfg->color_conv_mode0, 30, 1);
ge2d_reg_set_bits(GE2D_GEN_CTRL1, cfg->color_conv_mode1, 26, 1);
}
ge2d_reg_set_bits(GE2D_GEN_CTRL0, cfg->mode_8b_sel, 5, 2);
ge2d_reg_set_bits(GE2D_GEN_CTRL0, cfg->lut_en, 3, 1);
@@ -400,11 +432,20 @@ void ge2d_set_src2_dst_data(struct ge2d_src2_dst_data_s *cfg)
ge2d_reg_set_bits(GE2D_GEN_CTRL1, cfg->urgent_en, 9, 1);
ge2d_reg_set_bits(GE2D_GEN_CTRL1, cfg->ddr_burst_size, 22, 2);
/* only for m6 and later chips. */
ge2d_reg_write(GE2D_SRC2_DST_CANVAS, (cfg->src2_canaddr << 8) |
((cfg->dst_canaddr & 0xff) << 0) |
((cfg->dst_canaddr & 0xff00) << 8)
);
if (get_cpu_type() == MESON_CPU_MAJOR_ID_AXG) {
ge2d_canv_config(GE2D_SRC2_INDEX,
cfg->src2_phyaddr,
cfg->src2_stride);
ge2d_canv_config(GE2D_DST1_INDEX,
cfg->dst_phyaddr,
cfg->dst_stride);
} else {
/* only for m6 and later chips. */
ge2d_reg_write(GE2D_SRC2_DST_CANVAS, (cfg->src2_canaddr << 8) |
((cfg->dst_canaddr & 0xff) << 0) |
((cfg->dst_canaddr & 0xff00) << 8)
);
}
ge2d_reg_set_bits(GE2D_GEN_CTRL2, cfg->src2_endian, 15, 1);
ge2d_reg_set_bits(GE2D_GEN_CTRL2, cfg->src2_color_map, 11, 4);
@@ -892,7 +933,7 @@ void ge2d_set_cmd(struct ge2d_cmd_s *cfg)
* scale_out_done(test1823) hang issue when
* scaling down ratio is high.
*/
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX)
if (get_cpu_type() == MESON_CPU_MAJOR_ID_TXLX)
ge2d_reg_set_bits(GE2D_GEN_CTRL4, cfg->hang_flag, 0, 1);
ge2d_reg_write(GE2D_CMD_CTRL,
(cfg->src2_fill_color_en << 9) |
@@ -939,7 +980,7 @@ void ge2d_set_gen(struct ge2d_gen_s *cfg)
(cfg->vfmt_onoff_en << 15) |
(cfg->dp_off_cnt << 0)
);
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) {
if (get_cpu_type() == MESON_CPU_MAJOR_ID_TXLX) {
ge2d_reg_set_bits(GE2D_GEN_CTRL4,
(cfg->fifo_size << 26) |
(cfg->fifo_size << 24) |

16
drivers/amlogic/media/common/ge2d/ge2d_io.h
View File

@@ -53,14 +53,14 @@ static int check_map_flag(unsigned int addr)
reg_map.flag = 1;
ret = 1;
} else {
reg_map.vir_addr = ioremap(reg_map.phy_addr, reg_map.size);
if (!reg_map.vir_addr) {
pr_info("failed map phy: 0x%x\n", addr);
ret = 0;
} else {
reg_map.flag = 1;
pr_info("mapped phy: 0x%x\n", reg_map.phy_addr);
ret = 1;
reg_map.vir_addr = ioremap(reg_map.phy_addr, reg_map.size);
if (!reg_map.vir_addr) {
pr_info("failed map phy: 0x%x\n", addr);
ret = 0;
} else {
reg_map.flag = 1;
ge2d_log_dbg("mapped phy: 0x%x\n", reg_map.phy_addr);
ret = 1;
}
}
return ret;

6
drivers/amlogic/media/common/ge2d/ge2d_reg.h
View File

@@ -91,6 +91,12 @@
#define GE2D_GEN_CTRL3 0x18e8
#define GE2D_STATUS2 0x18e9
#define GE2D_GEN_CTRL4 0x18ea
#define GE2D_DST1_BADDR_CTRL 0x18f1
#define GE2D_DST1_STRIDE_CTRL 0x18f2
#define GE2D_SRC1_BADDR_CTRL 0x18f3
#define GE2D_SRC1_STRIDE_CTRL 0x18f4
#define GE2D_SRC2_BADDR_CTRL 0x18f5
#define GE2D_SRC2_STRIDE_CTRL 0x18f6
#define VIU_OSD1_BLK0_CFG_W0 0x1a1b

623
drivers/amlogic/media/common/ge2d/ge2d_wq.c
View File

@@ -28,6 +28,7 @@
#include <linux/clk.h>
/* Amlogic Headers */
#include <linux/amlogic/cpu_version.h>
#include <linux/amlogic/media/canvas/canvas.h>
#include <linux/amlogic/media/canvas/canvas_mgr.h>
#include <linux/amlogic/media/ge2d/ge2d.h>
@@ -42,6 +43,7 @@
#include "ge2d_wq.h"
#include "osd_io.h"
#include "osd_hw.h"
#define OSD1_CANVAS_INDEX 0x40
#define OSD2_CANVAS_INDEX 0x43
#define OSD3_CANVAS_INDEX 0x41
@@ -53,38 +55,6 @@ static int ge2d_irq = -ENXIO;
static struct reset_control *ge2d_rstc;
static struct clk *ge2d_clk;
enum color_index_e {
COLOR_INDEX_02_PAL4 = 2,
COLOR_INDEX_04_PAL16 = 4,
COLOR_INDEX_08_PAL256 = 8,
COLOR_INDEX_16_655 = 9,
COLOR_INDEX_16_844 = 10,
COLOR_INDEX_16_6442 = 11,
COLOR_INDEX_16_4444_R = 12,
COLOR_INDEX_16_4642_R = 13,
COLOR_INDEX_16_1555_A = 14,
COLOR_INDEX_16_4444_A = 15,
COLOR_INDEX_16_565 = 16,
COLOR_INDEX_24_6666_A = 19,
COLOR_INDEX_24_6666_R = 20,
COLOR_INDEX_24_8565 = 21,
COLOR_INDEX_24_5658 = 22,
COLOR_INDEX_24_888_B = 23,
COLOR_INDEX_24_RGB = 24,
COLOR_INDEX_32_BGRX = 25,
COLOR_INDEX_32_XBGR = 26,
COLOR_INDEX_32_RGBX = 27,
COLOR_INDEX_32_XRGB = 28,
COLOR_INDEX_32_BGRA = 29,
COLOR_INDEX_32_ABGR = 30,
COLOR_INDEX_32_RGBA = 31,
COLOR_INDEX_32_ARGB = 32,
COLOR_INDEX_YUV_422 = 33,
};
static const int bpp_type_lut[] = {
/* 16bit */
@@ -557,51 +527,80 @@ static void build_ge2d_config(struct config_para_s *cfg,
struct src_dst_para_s *dst,
int index)
{
int cpu_type;
index &= 0xff;
cpu_type = get_cpu_type();
if (src) {
src->xres = cfg->src_planes[0].w;
src->yres = cfg->src_planes[0].h;
src->ge2d_color_index = cfg->src_format;
src->bpp = bpp(cfg->src_format);
if (cfg->src_planes[0].addr) {
src->canvas_index = index;
canvas_config(index++,
cfg->src_planes[0].addr,
cfg->src_planes[0].w * src->bpp / 8,
cfg->src_planes[0].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG) {
src->canvas_index = 0;
src->phy_addr = cfg->src_planes[0].addr;
src->stride = cfg->src_planes[0].w *
src->bpp / 8;
}
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
else {
src->canvas_index = index;
canvas_config(index++,
cfg->src_planes[0].addr,
cfg->src_planes[0].w * src->bpp / 8,
cfg->src_planes[0].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
}
#endif
}
/* multi-src_planes */
if (cfg->src_planes[1].addr) {
src->canvas_index |= index << 8;
canvas_config(index++,
cfg->src_planes[1].addr,
cfg->src_planes[1].w * src->bpp / 8,
cfg->src_planes[1].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG)
ge2d_log_info("ge2d not support src_planes[1]\n");
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
else {
src->canvas_index |= index << 8;
canvas_config(index++,
cfg->src_planes[1].addr,
cfg->src_planes[1].w * src->bpp / 8,
cfg->src_planes[1].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
}
#endif
}
if (cfg->src_planes[2].addr) {
src->canvas_index |= index << 16;
canvas_config(index++,
cfg->src_planes[2].addr,
cfg->src_planes[2].w * src->bpp / 8,
cfg->src_planes[2].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG)
ge2d_log_info("ge2d not support src_planes[2]\n");
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
else {
src->canvas_index |= index << 16;
canvas_config(index++,
cfg->src_planes[2].addr,
cfg->src_planes[2].w * src->bpp / 8,
cfg->src_planes[2].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
}
#endif
}
if (cfg->src_planes[3].addr) {
src->canvas_index |= index << 24;
canvas_config(index++,
cfg->src_planes[3].addr,
cfg->src_planes[3].w * src->bpp / 8,
cfg->src_planes[3].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG)
ge2d_log_info("ge2d not support src_planes[3]\n");
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
else {
src->canvas_index |= index << 24;
canvas_config(index++,
cfg->src_planes[3].addr,
cfg->src_planes[3].w * src->bpp / 8,
cfg->src_planes[3].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
}
#endif
}
}
if (dst) {
dst->xres = cfg->dst_planes[0].w;
@@ -609,42 +608,69 @@ static void build_ge2d_config(struct config_para_s *cfg,
dst->ge2d_color_index = cfg->dst_format;
dst->bpp = bpp(cfg->dst_format);
if (cfg->dst_planes[0].addr) {
dst->canvas_index = index;
canvas_config(index++ & 0xff,
cfg->dst_planes[0].addr,
cfg->dst_planes[0].w,
cfg->dst_planes[0].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG) {
dst->canvas_index = 0;
dst->phy_addr = cfg->src_planes[0].addr;
dst->stride = cfg->src_planes[0].w *
src->bpp / 8;
}
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
else {
dst->canvas_index = index;
canvas_config(index++ & 0xff,
cfg->dst_planes[0].addr,
cfg->dst_planes[0].w,
cfg->dst_planes[0].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
}
#endif
}
/* multi-src_planes */
if (cfg->dst_planes[1].addr) {
dst->canvas_index |= index << 8;
canvas_config(index++,
cfg->dst_planes[1].addr,
cfg->dst_planes[1].w,
cfg->dst_planes[1].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG)
ge2d_log_info("ge2d not support dst_planes[1]\n");
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
else {
dst->canvas_index |= index << 8;
canvas_config(index++,
cfg->dst_planes[1].addr,
cfg->dst_planes[1].w,
cfg->dst_planes[1].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
}
#endif
}
if (cfg->dst_planes[2].addr) {
dst->canvas_index |= index << 16;
canvas_config(index++,
cfg->dst_planes[2].addr,
cfg->dst_planes[2].w,
cfg->dst_planes[2].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG)
ge2d_log_info("ge2d not support dst_planes[2]\n");
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
else {
dst->canvas_index |= index << 16;
canvas_config(index++,
cfg->dst_planes[2].addr,
cfg->dst_planes[2].w,
cfg->dst_planes[2].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
}
#endif
}
if (cfg->dst_planes[3].addr) {
dst->canvas_index |= index << 24;
canvas_config(index++,
cfg->dst_planes[3].addr,
cfg->dst_planes[3].w,
cfg->dst_planes[3].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG)
ge2d_log_info("ge2d not support dst_planes[3]\n");
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
else {
dst->canvas_index |= index << 24;
canvas_config(index++,
cfg->dst_planes[3].addr,
cfg->dst_planes[3].w,
cfg->dst_planes[3].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
}
#endif
}
}
}
@@ -652,21 +678,47 @@ static void build_ge2d_config(struct config_para_s *cfg,
static int setup_display_property(struct src_dst_para_s *src_dst, int index)
{
#define REG_OFFSET (0x20)
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
struct canvas_s canvas;
#endif
u32 cs_width = 0, cs_height = 0, cs_addr = 0;
unsigned int data32;
unsigned int bpp;
unsigned int block_mode[] = {2, 4, 8, 16, 16, 32, 0, 24};
int cpu_type;
cpu_type = get_cpu_type();
src_dst->canvas_index = index;
canvas_read(index, &canvas);
if (cpu_type != MESON_CPU_MAJOR_ID_AXG) {
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
canvas_read(index, &canvas);
cs_width = canvas.width;
cs_height = canvas.height;
#else
cs_width = 0;
cs_height = 0;
#endif
}
index = (index == OSD1_CANVAS_INDEX ? 0 : 1);
ge2d_log_dbg("osd%d ", index);
#ifdef CONFIG_AMLOGIC_MEDIA_FB
data32 = VSYNCOSD_RD_MPEG_REG(
VIU_OSD1_BLK0_CFG_W0 + REG_OFFSET * index);
src_dst->canvas_index = (data32 >> 16) & 0xff;
canvas_read(src_dst->canvas_index, &canvas);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG) {
src_dst->canvas_index = 0;
osd_get_info(index, &cs_addr,
&cs_width, &cs_height);
src_dst->phy_addr = cs_addr;
src_dst->stride = cs_width;
}
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
else {
canvas_read(src_dst->canvas_index, &canvas);
cs_width = canvas.width;
cs_height = canvas.height;
}
#endif
#else
data32 = 0;
#endif
@@ -678,8 +730,8 @@ static int setup_display_property(struct src_dst_para_s *src_dst, int index)
return -1;
src_dst->bpp = bpp;
src_dst->xres = canvas.width / (bpp >> 3);
src_dst->yres = canvas.height;
src_dst->xres = cs_width / (bpp >> 3);
src_dst->yres = cs_height;
if (index == 3) /* yuv422 32bit for two pixel. */
src_dst->ge2d_color_index = GE2D_FORMAT_S16_YUV422;
else { /* for block mode=4,5,7 */
@@ -784,20 +836,89 @@ int ge2d_context_config(struct ge2d_context_s *context,
ge2d_log_dbg("src_format: 0x%x, dst_format: 0x%x\n",
src.ge2d_color_index, dst.ge2d_color_index);
ge2dgen_src(context, src.canvas_index, src.ge2d_color_index);
ge2dgen_src(context, src.canvas_index,
src.ge2d_color_index,
src.phy_addr,
src.stride);
ge2dgen_src_clip(context,
0, 0, src.xres, src.yres);
ge2dgen_src2(context, dst.canvas_index, dst.ge2d_color_index);
ge2dgen_src2(context, dst.canvas_index,
dst.ge2d_color_index,
dst.phy_addr,
dst.stride);
ge2dgen_src2_clip(context,
0, 0, dst.xres, dst.yres);
ge2dgen_const_color(context, ge2d_config->alu_const_color);
ge2dgen_dst(context, dst.canvas_index, dst.ge2d_color_index);
ge2dgen_dst(context, dst.canvas_index,
dst.ge2d_color_index,
dst.phy_addr,
dst.stride);
ge2dgen_dst_clip(context,
0, 0, dst.xres, dst.yres, DST_CLIP_MODE_INSIDE);
return 0;
}
static int build_ge2d_addr_config(
struct config_planes_s *plane,
unsigned int format,
unsigned int *addr,
unsigned int *stride
)
{
int ret = -1;
int bpp_value = bpp(format);
bpp_value /= 8;
ge2d_log_dbg("build_ge2d_addr_config bpp_value=%d\n",
bpp_value);
if (plane) {
if (plane[0].addr) {
*addr = plane[0].addr;
*stride = plane[0].w * bpp_value;
ret = 0;
}
/* not support multi-src_planes */
if ((plane[1].addr) ||
(plane[2].addr) ||
(plane[3].addr)) {
ge2d_log_info("ge2d not support NV21 mode\n");
ret = -1;
}
}
return ret;
}
static int build_ge2d_addr_config_ion(
struct config_planes_ion_s *plane,
unsigned int format,
unsigned int *addr,
unsigned int *stride
)
{
int ret = -1;
int bpp_value = bpp(format);
bpp_value /= 8;
ge2d_log_dbg("build_ge2d_addr_config_ion bpp_value=%d\n",
bpp_value);
if (plane) {
if (plane[0].addr) {
*addr = plane[0].addr;
*stride = plane[0].w * bpp_value;
ret = 0;
}
/* not support multi-src_planes */
if ((plane[1].addr) ||
(plane[2].addr) ||
(plane[3].addr)) {
ge2d_log_info("ge2d not support NV21 mode\n");
ret = -1;
}
}
return ret;
}
static int build_ge2d_config_ex(struct config_planes_s *plane,
unsigned int format,
unsigned int *canvas_index,
@@ -813,40 +934,48 @@ static int build_ge2d_config_ex(struct config_planes_s *plane,
if (plane[0].addr) {
*canvas_index = index;
*r_offset += 1;
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
canvas_config(index++, plane[0].addr,
plane[0].w * bpp_value,
plane[0].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#endif
ret = 0;
}
/* multi-src_planes */
if (plane[1].addr) {
*canvas_index |= index << 8;
*r_offset += 1;
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
canvas_config(index++, plane[1].addr,
plane[1].w * bpp_value,
plane[1].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#endif
}
if (plane[2].addr) {
*canvas_index |= index << 16;
*r_offset += 1;
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
canvas_config(index++, plane[2].addr,
plane[2].w * bpp_value,
plane[2].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#endif
}
if (plane[3].addr) {
*canvas_index |= index << 24;
*r_offset += 1;
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
canvas_config(index++, plane[3].addr,
plane[3].w * bpp_value,
plane[3].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#endif
}
}
return ret;
@@ -879,11 +1008,13 @@ static int build_ge2d_config_ex_ion(struct config_planes_ion_s *plane,
plane[0].addr += addr;
*canvas_index = index;
*r_offset += 1;
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
canvas_config(index++, plane[0].addr,
plane[0].w * bpp_value,
plane[0].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#endif
ret = 0;
}
/* multi-src_planes */
@@ -891,31 +1022,37 @@ static int build_ge2d_config_ex_ion(struct config_planes_ion_s *plane,
plane[1].addr += plane[0].addr;
*canvas_index |= index << 8;
*r_offset += 1;
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
canvas_config(index++, plane[1].addr,
plane[1].w * bpp_value,
plane[1].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#endif
}
if (plane[2].addr) {
plane[2].addr += plane[1].addr;
*canvas_index |= index << 16;
*r_offset += 1;
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
canvas_config(index++, plane[2].addr,
plane[2].w * bpp_value,
plane[2].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#endif
}
if (plane[3].addr) {
plane[3].addr += plane[2].addr;
*canvas_index |= index << 24;
*r_offset += 1;
#ifdef CONFIG_AMLOGIC_MEDIA_CANVAS
canvas_config(index++, plane[3].addr,
plane[3].w * bpp_value,
plane[3].h,
CANVAS_ADDR_NOWRAP,
CANVAS_BLKMODE_LINEAR);
#endif
}
}
return ret;
@@ -932,7 +1069,11 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
struct ge2d_dp_gen_s *dp_gen_cfg;
struct ge2d_cmd_s *ge2d_cmd_cfg;
int top, left, width, height;
int cpu_type;
unsigned int src_addr = 0, src2_addr = 0, dst_addr = 0;
unsigned int src_stride = 0, src2_stride = 0, dst_stride = 0;
cpu_type = get_cpu_type();
/* setup src and dst */
switch (ge2d_config->src_para.mem_type) {
case CANVAS_OSD0:
@@ -943,7 +1084,8 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
return -1;
ge2d_config->src_para.canvas_index = tmp.canvas_index;
ge2d_config->src_para.format = tmp.ge2d_color_index;
src_addr = tmp.phy_addr;
src_stride = tmp.stride;
ge2d_log_dbg("ge2d: src1-->type: osd%d, format: 0x%x !!\n",
ge2d_config->src_para.mem_type - CANVAS_OSD0,
ge2d_config->src_para.format);
@@ -959,6 +1101,10 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
}
ge2d_config->src_para.width = tmp.xres;
ge2d_config->src_para.height = tmp.yres;
ge2d_log_dbg("ge2d osd phy_addr:0x%x,stride=0x%x,format:0x%x\n",
src_addr,
src_stride,
ge2d_config->src_para.format);
break;
case CANVAS_ALLOC:
top = ge2d_config->src_para.top;
@@ -970,15 +1116,28 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
ge2d_log_dbg("ge2d error: src alloc, out of range\n");
return -1;
}
if (build_ge2d_config_ex(&ge2d_config->src_planes[0],
ge2d_config->src_para.format,
&index,
ALLOC_CANVAS_INDEX + alloc_canvas_offset,
&alloc_canvas_offset) < 0)
return -1;
ge2d_config->src_para.canvas_index = index;
ge2d_log_dbg("ge2d alloc canvas index:0x%x, format:0x%x\n",
index, ge2d_config->src_para.format);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG) {
if (build_ge2d_addr_config(
&ge2d_config->src_planes[0],
ge2d_config->src_para.format,
&src_addr,
&src_stride) < 0)
return -1;
ge2d_log_dbg("ge2d alloc phy_addr:0x%x,stride=0x%x,format:0x%x\n",
src_addr,
src_stride,
ge2d_config->src_para.format);
} else {
if (build_ge2d_config_ex(&ge2d_config->src_planes[0],
ge2d_config->src_para.format,
&index,
ALLOC_CANVAS_INDEX + alloc_canvas_offset,
&alloc_canvas_offset) < 0)
return -1;
ge2d_config->src_para.canvas_index = index;
ge2d_log_dbg("ge2d alloc canvas index:0x%x, format:0x%x\n",
index, ge2d_config->src_para.format);
}
break;
default:
break;
@@ -993,7 +1152,8 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
return -1;
ge2d_config->src2_para.canvas_index = tmp.canvas_index;
ge2d_config->src2_para.format = tmp.ge2d_color_index;
src2_addr = tmp.phy_addr;
src2_stride = tmp.stride;
ge2d_log_dbg("ge2d: src2-->type: osd%d, format: 0x%x !!\n",
ge2d_config->src2_para.mem_type - CANVAS_OSD0,
ge2d_config->src2_para.format);
@@ -1009,6 +1169,10 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
}
ge2d_config->src2_para.width = tmp.xres;
ge2d_config->src2_para.height = tmp.yres;
ge2d_log_dbg("ge2d osd phy_addr:0x%x,stride=0x%x,format:0x%x\n",
src2_addr,
src_stride,
ge2d_config->src2_para.format);
break;
case CANVAS_ALLOC:
top = ge2d_config->src2_para.top;
@@ -1021,17 +1185,37 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
return -1;
}
if (ge2d_config->src2_planes[0].addr ==
ge2d_config->src_planes[0].addr)
index = ge2d_config->src_para.canvas_index;
else if (build_ge2d_config_ex(&ge2d_config->src2_planes[0],
ge2d_config->src2_para.format,
&index,
ALLOC_CANVAS_INDEX + alloc_canvas_offset,
&alloc_canvas_offset) < 0)
return -1;
ge2d_config->src2_para.canvas_index = index;
ge2d_log_dbg("ge2d src2 alloc, canvas index:0x%x,format:0x%x\n",
index, ge2d_config->src2_para.format);
ge2d_config->src_planes[0].addr) {
ge2d_config->src2_para.canvas_index =
ge2d_config->src_para.canvas_index;
src2_addr = src_addr;
src2_stride = src_stride;
} else {
if (cpu_type == MESON_CPU_MAJOR_ID_AXG) {
if (build_ge2d_addr_config(
&ge2d_config->src2_planes[0],
ge2d_config->src2_para.format,
&src2_addr,
&src2_stride) < 0)
return -1;
ge2d_log_dbg("ge2d alloc phy_addr:0x%x,stride=0x%x,format:0x%x\n",
src2_addr,
src2_stride,
ge2d_config->src2_para.format);
} else {
if (build_ge2d_config_ex(
&ge2d_config->src2_planes[0],
ge2d_config->src2_para.format,
&index,
ALLOC_CANVAS_INDEX +
alloc_canvas_offset,
&alloc_canvas_offset) < 0)
return -1;
ge2d_config->src2_para.canvas_index = index;
ge2d_log_dbg("ge2d src2 alloc, canvas index:0x%x,format:0x%x\n",
index, ge2d_config->src2_para.format);
}
}
break;
default:
break;
@@ -1046,6 +1230,8 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
return -1;
ge2d_config->dst_para.canvas_index = tmp.canvas_index;
ge2d_config->dst_para.format = tmp.ge2d_color_index;
dst_addr = tmp.phy_addr;
dst_stride = tmp.stride;
ge2d_log_dbg("ge2d: dst-->type: osd%d, format: 0x%x !!\n",
ge2d_config->dst_para.mem_type - CANVAS_OSD0,
@@ -1062,6 +1248,10 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
}
ge2d_config->dst_para.width = tmp.xres;
ge2d_config->dst_para.height = tmp.yres;
ge2d_log_dbg("ge2d osd phy_addr:0x%x,stride=0x%x,format:0x%x\n",
dst_addr,
dst_stride,
ge2d_config->dst_para.format);
break;
case CANVAS_ALLOC:
top = ge2d_config->dst_para.top;
@@ -1074,20 +1264,44 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
return -1;
}
if (ge2d_config->dst_planes[0].addr ==
ge2d_config->src_planes[0].addr)
index = ge2d_config->src_para.canvas_index;
ge2d_config->src_planes[0].addr) {
ge2d_config->dst_para.canvas_index =
ge2d_config->src_para.canvas_index;
dst_addr = src_addr;
dst_stride = src_stride;
}
else if (ge2d_config->dst_planes[0].addr ==
ge2d_config->src2_planes[0].addr)
index = ge2d_config->src2_para.canvas_index;
else if (build_ge2d_config_ex(&ge2d_config->dst_planes[0],
ge2d_config->dst_para.format,
&index,
ALLOC_CANVAS_INDEX + alloc_canvas_offset,
&alloc_canvas_offset) < 0)
return -1;
ge2d_config->dst_para.canvas_index = index;
ge2d_log_dbg("ge2d: dst alloc, index:0x%x, format:0x%x\n",
index, ge2d_config->dst_para.format);
ge2d_config->src2_planes[0].addr) {
ge2d_config->dst_para.canvas_index =
ge2d_config->src2_para.canvas_index;
dst_addr = src2_addr;
dst_stride = src2_stride;
} else {
if (cpu_type == MESON_CPU_MAJOR_ID_AXG) {
if (build_ge2d_addr_config(
&ge2d_config->dst_planes[0],
ge2d_config->dst_para.format,
&dst_addr,
&dst_stride) < 0)
return -1;
ge2d_log_dbg("ge2d alloc phy_addr:0x%x,stride=0x%x,format:0x%x\n",
dst_addr,
dst_stride,
ge2d_config->dst_para.format);
} else {
if (build_ge2d_config_ex(
&ge2d_config->dst_planes[0],
ge2d_config->dst_para.format,
&index,
ALLOC_CANVAS_INDEX +
alloc_canvas_offset,
&alloc_canvas_offset) < 0)
return -1;
ge2d_config->dst_para.canvas_index = index;
ge2d_log_dbg("ge2d: dst alloc, index:0x%x, format:0x%x\n",
index, ge2d_config->dst_para.format);
}
}
break;
default:
break;
@@ -1101,7 +1315,9 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
ge2dgen_const_color(context, ge2d_config->alu_const_color);
ge2dgen_src(context, ge2d_config->src_para.canvas_index,
ge2d_config->src_para.format);
ge2d_config->src_para.format,
src_addr,
src_stride);
ge2dgen_src_clip(context, ge2d_config->src_para.left,
ge2d_config->src_para.top,
ge2d_config->src_para.width,
@@ -1115,14 +1331,18 @@ int ge2d_context_config_ex(struct ge2d_context_s *context,
ge2dgen_src_color(context, ge2d_config->src_para.color);
ge2dgen_src2(context, ge2d_config->src2_para.canvas_index,
ge2d_config->src2_para.format);
ge2d_config->src2_para.format,
src2_addr,
src2_stride);
ge2dgen_src2_clip(context, ge2d_config->src2_para.left,
ge2d_config->src2_para.top,
ge2d_config->src2_para.width,
ge2d_config->src2_para.height);
ge2dgen_dst(context, ge2d_config->dst_para.canvas_index,
ge2d_config->dst_para.format);
ge2d_config->dst_para.format,
dst_addr,
dst_stride);
ge2dgen_dst_clip(context, ge2d_config->dst_para.left,
ge2d_config->dst_para.top,
ge2d_config->dst_para.width,
@@ -1208,7 +1428,11 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
struct ge2d_dp_gen_s *dp_gen_cfg;
struct ge2d_cmd_s *ge2d_cmd_cfg;
int top, left, width, height;
int cpu_type;
unsigned int src_addr = 0, src2_addr = 0, dst_addr = 0;
unsigned int src_stride = 0, src2_stride = 0, dst_stride = 0;
cpu_type = get_cpu_type();
/* setup src and dst */
switch (ge2d_config->src_para.mem_type) {
case CANVAS_OSD0:
@@ -1219,6 +1443,8 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
return -1;
ge2d_config->src_para.canvas_index = tmp.canvas_index;
ge2d_config->src_para.format = tmp.ge2d_color_index;
src_addr = tmp.phy_addr;
src_stride = tmp.stride;
ge2d_log_dbg("ge2d: src1-->type: osd%d, format: 0x%x !!\n",
ge2d_config->src_para.mem_type - CANVAS_OSD0,
@@ -1235,6 +1461,10 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
}
ge2d_config->src_para.width = tmp.xres;
ge2d_config->src_para.height = tmp.yres;
ge2d_log_dbg("ge2d osd phy_addr:0x%x,stride=0x%x,format:0x%x\n",
src_addr,
src_stride,
ge2d_config->src_para.format);
break;
case CANVAS_ALLOC:
top = ge2d_config->src_para.top;
@@ -1246,15 +1476,30 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
ge2d_log_dbg("ge2d error: src alloc, out of range\n");
return -1;
}
if (build_ge2d_config_ex_ion(&ge2d_config->src_planes[0],
ge2d_config->src_para.format,
&index,
ALLOC_CANVAS_INDEX + alloc_canvas_offset,
&alloc_canvas_offset) < 0)
if (cpu_type == MESON_CPU_MAJOR_ID_AXG) {
if (build_ge2d_addr_config_ion(
&ge2d_config->src_planes[0],
ge2d_config->src_para.format,
&src_addr,
&src_stride) < 0)
return -1;
ge2d_log_dbg("ge2d alloc phy_addr:0x%x,stride=0x%x,format:0x%x\n",
src_addr,
src_stride,
ge2d_config->src_para.format);
} else {
if (build_ge2d_config_ex_ion(
&ge2d_config->src_planes[0],
ge2d_config->src_para.format,
&index,
ALLOC_CANVAS_INDEX + alloc_canvas_offset,
&alloc_canvas_offset) < 0)
return -1;
ge2d_config->src_para.canvas_index = index;
ge2d_log_dbg("ge2d alloc canvas index:0x%x, format:0x%x\n",
index, ge2d_config->src_para.format);
ge2d_config->src_para.canvas_index = index;
ge2d_log_dbg("ge2d alloc canvas index:0x%x, format:0x%x\n",
index, ge2d_config->src_para.format);
}
break;
default:
break;
@@ -1269,6 +1514,8 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
return -1;
ge2d_config->src2_para.canvas_index = tmp.canvas_index;
ge2d_config->src2_para.format = tmp.ge2d_color_index;
src2_addr = tmp.phy_addr;
src2_stride = tmp.stride;
ge2d_log_dbg("ge2d: src2-->type: osd%d, format: 0x%x !!\n",
ge2d_config->src2_para.mem_type - CANVAS_OSD0,
@@ -1285,6 +1532,10 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
}
ge2d_config->src2_para.width = tmp.xres;
ge2d_config->src2_para.height = tmp.yres;
ge2d_log_dbg("ge2d osd phy_addr:0x%x,stride=0x%x,format:0x%x\n",
src2_addr,
src2_stride,
ge2d_config->src2_para.format);
break;
case CANVAS_ALLOC:
top = ge2d_config->src2_para.top;
@@ -1301,15 +1552,29 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
* index = ge2d_config->src_para.canvas_index;
* else
*/
if (build_ge2d_config_ex_ion(&ge2d_config->src2_planes[0],
ge2d_config->src2_para.format,
&index,
ALLOC_CANVAS_INDEX + alloc_canvas_offset,
&alloc_canvas_offset) < 0)
return -1;
ge2d_config->src2_para.canvas_index = index;
ge2d_log_dbg("ge2d src2 alloc, canvas index:0x%x,format:0x%x\n",
index, ge2d_config->src2_para.format);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG) {
if (build_ge2d_addr_config_ion(
&ge2d_config->src2_planes[0],
ge2d_config->src2_para.format,
&src2_addr,
&src2_stride) < 0)
return -1;
ge2d_log_dbg("ge2d alloc phy_addr:0x%x,stride=0x%x,format:0x%x\n",
src2_addr,
src2_stride,
ge2d_config->src2_para.format);
} else {
if (build_ge2d_config_ex_ion(
&ge2d_config->src2_planes[0],
ge2d_config->src2_para.format,
&index,
ALLOC_CANVAS_INDEX + alloc_canvas_offset,
&alloc_canvas_offset) < 0)
return -1;
ge2d_config->src2_para.canvas_index = index;
ge2d_log_dbg("ge2d src2 alloc, canvas index:0x%x,format:0x%x\n",
index, ge2d_config->src2_para.format);
}
break;
default:
break;
@@ -1324,6 +1589,8 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
return -1;
ge2d_config->dst_para.canvas_index = tmp.canvas_index;
ge2d_config->dst_para.format = tmp.ge2d_color_index;
dst_addr = tmp.phy_addr;
dst_stride = tmp.stride;
ge2d_log_dbg("ge2d: dst-->type: osd%d, format: 0x%x !!\n",
ge2d_config->dst_para.mem_type - CANVAS_OSD0,
@@ -1340,6 +1607,10 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
}
ge2d_config->dst_para.width = tmp.xres;
ge2d_config->dst_para.height = tmp.yres;
ge2d_log_dbg("ge2d osd phy_addr:0x%x,stride=0x%x,format:0x%x\n",
dst_addr,
dst_stride,
ge2d_config->dst_para.format);
break;
case CANVAS_ALLOC:
top = ge2d_config->dst_para.top;
@@ -1359,15 +1630,29 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
* index = ge2d_config->src2_para.canvas_index;
* else
*/
if (build_ge2d_config_ex_ion(&ge2d_config->dst_planes[0],
ge2d_config->dst_para.format,
&index,
ALLOC_CANVAS_INDEX + alloc_canvas_offset,
&alloc_canvas_offset) < 0)
return -1;
ge2d_config->dst_para.canvas_index = index;
ge2d_log_dbg("ge2d: dst alloc, index:0x%x, format:0x%x\n",
index, ge2d_config->dst_para.format);
if (cpu_type == MESON_CPU_MAJOR_ID_AXG) {
if (build_ge2d_addr_config_ion(
&ge2d_config->dst_planes[0],
ge2d_config->dst_para.format,
&dst_addr,
&dst_stride) < 0)
return -1;
ge2d_log_dbg("ge2d alloc phy_addr:0x%x,stride=0x%x,format:0x%x\n",
dst_addr,
dst_stride,
ge2d_config->dst_para.format);
} else {
if (build_ge2d_config_ex_ion(
&ge2d_config->dst_planes[0],
ge2d_config->dst_para.format,
&index,
ALLOC_CANVAS_INDEX + alloc_canvas_offset,
&alloc_canvas_offset) < 0)
return -1;
ge2d_config->dst_para.canvas_index = index;
ge2d_log_dbg("ge2d: dst alloc, index:0x%x, format:0x%x\n",
index, ge2d_config->dst_para.format);
}
break;
default:
break;
@@ -1381,7 +1666,9 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
ge2dgen_const_color(context, ge2d_config->alu_const_color);
ge2dgen_src(context, ge2d_config->src_para.canvas_index,
ge2d_config->src_para.format);
ge2d_config->src_para.format,
src_addr,
src_stride);
ge2dgen_src_clip(context, ge2d_config->src_para.left,
ge2d_config->src_para.top,
ge2d_config->src_para.width,
@@ -1395,14 +1682,18 @@ int ge2d_context_config_ex_ion(struct ge2d_context_s *context,
ge2dgen_src_color(context, ge2d_config->src_para.color);
ge2dgen_src2(context, ge2d_config->src2_para.canvas_index,
ge2d_config->src2_para.format);
ge2d_config->src2_para.format,
src2_addr,
src2_stride);
ge2dgen_src2_clip(context, ge2d_config->src2_para.left,
ge2d_config->src2_para.top,
ge2d_config->src2_para.width,
ge2d_config->src2_para.height);
ge2dgen_dst(context, ge2d_config->dst_para.canvas_index,
ge2d_config->dst_para.format);
ge2d_config->dst_para.format,
dst_addr,
dst_stride);
ge2dgen_dst_clip(context, ge2d_config->dst_para.left,
ge2d_config->dst_para.top,
ge2d_config->dst_para.width,

34
drivers/amlogic/media/common/ge2d/ge2dgen.c
View File

@@ -129,8 +129,10 @@ static inline void _set_dst_format(
}
void ge2dgen_src(struct ge2d_context_s *wq,
unsigned int canvas_addr,
unsigned int format)
unsigned int canvas_addr,
unsigned int format,
unsigned int phy_addr,
unsigned int stride)
{
struct ge2d_src1_data_s *src1_data_cfg = ge2d_wq_get_src_data(wq);
struct ge2d_src1_gen_s *src1_gen_cfg = ge2d_wq_get_src_gen(wq);
@@ -139,11 +141,15 @@ void ge2dgen_src(struct ge2d_context_s *wq,
ge2d_wq_get_dst_data(wq);
if ((format != src1_data_cfg->format_all) ||
(canvas_addr != src1_data_cfg->canaddr)) {
(canvas_addr != src1_data_cfg->canaddr) ||
(phy_addr != src1_data_cfg->phy_addr) ||
(stride != src1_data_cfg->stride)) {
src1_data_cfg->canaddr = canvas_addr;
_set_src1_format(src1_data_cfg, src1_gen_cfg, dp_gen_cfg,
format, src2_dst_data_cfg->dst_format_all);
src1_data_cfg->phy_addr = phy_addr;
src1_data_cfg->stride = stride;
wq->config.update_flag |= UPDATE_SRC_DATA;
wq->config.update_flag |= UPDATE_SRC_GEN;
wq->config.update_flag |= UPDATE_DP_GEN;
@@ -204,19 +210,25 @@ void ge2dgen_cb(struct ge2d_context_s *wq,
}
void ge2dgen_src2(struct ge2d_context_s *wq,
unsigned int canvas_addr,
unsigned int format)
unsigned int canvas_addr,
unsigned int format,
unsigned int phy_addr,
unsigned int stride)
{
struct ge2d_src2_dst_data_s *src2_dst_data_cfg =
ge2d_wq_get_dst_data(wq);
struct ge2d_src2_dst_gen_s *src2_dst_gen_cfg = ge2d_wq_get_dst_gen(wq);
if ((format != src2_dst_data_cfg->src2_format_all) ||
(canvas_addr != src2_dst_data_cfg->src2_canaddr)) {
(canvas_addr != src2_dst_data_cfg->src2_canaddr) ||
(phy_addr != src2_dst_data_cfg->src2_phyaddr) ||
(stride != src2_dst_data_cfg->src2_stride)) {
src2_dst_data_cfg->src2_canaddr = canvas_addr;
_set_src2_format(src2_dst_data_cfg, src2_dst_gen_cfg, format);
src2_dst_data_cfg->src2_phyaddr = phy_addr;
src2_dst_data_cfg->src2_stride = stride;
wq->config.update_flag |= UPDATE_DST_DATA;
wq->config.update_flag |= UPDATE_DST_GEN;
}
@@ -224,7 +236,9 @@ void ge2dgen_src2(struct ge2d_context_s *wq,
void ge2dgen_dst(struct ge2d_context_s *wq,
unsigned int canvas_addr,
unsigned int format)
unsigned int format,
unsigned int phy_addr,
unsigned int stride)
{
struct ge2d_src1_data_s *src1_data_cfg = ge2d_wq_get_src_data(wq);
struct ge2d_src2_dst_data_s *src2_dst_data_cfg =
@@ -233,11 +247,15 @@ void ge2dgen_dst(struct ge2d_context_s *wq,
struct ge2d_dp_gen_s *dp_gen_cfg = ge2d_wq_get_dp_gen(wq);
if ((format != src2_dst_data_cfg->dst_format_all) ||
(canvas_addr != src2_dst_data_cfg->dst_canaddr)) {
(canvas_addr != src2_dst_data_cfg->dst_canaddr) ||
(phy_addr != src2_dst_data_cfg->dst_phyaddr) ||
(stride != src2_dst_data_cfg->dst_stride)) {
src2_dst_data_cfg->dst_canaddr = canvas_addr;
_set_dst_format(src2_dst_data_cfg, src2_dst_gen_cfg, dp_gen_cfg,
src1_data_cfg->format_all, format);
src2_dst_data_cfg->dst_phyaddr = phy_addr;
src2_dst_data_cfg->dst_stride = stride;
wq->config.update_flag |= UPDATE_DST_DATA;
wq->config.update_flag |= UPDATE_DST_GEN;
wq->config.update_flag |= UPDATE_DP_GEN;

20
drivers/amlogic/media/common/ge2d/ge2dgen.h
View File

@@ -19,8 +19,10 @@
#define _GE2DGEN_H_
void ge2dgen_src(struct ge2d_context_s *wq,
unsigned int canvas_addr,
unsigned int format);
unsigned int canvas_addr,
unsigned int format,
unsigned int phy_addr,
unsigned int stride);
void ge2dgen_post_release_src1buf(struct ge2d_context_s *wq,
unsigned int buffer);
@@ -33,8 +35,10 @@ void ge2dgen_post_release_src2buf(struct ge2d_context_s *wq,
void ge2dgen_post_release_src2canvas(struct ge2d_context_s *wq);
void ge2dgen_src2(struct ge2d_context_s *wq,
unsigned int canvas_addr,
unsigned int format);
unsigned int canvas_addr,
unsigned int format,
unsigned int phy_addr,
unsigned int stride);
void ge2dgen_src2_clip(struct ge2d_context_s *wq,
int x, int y, int w, int h);
@@ -47,8 +51,10 @@ void ge2dgen_rendering_dir(struct ge2d_context_s *wq,
int dst_xy_swap);
void ge2dgen_dst(struct ge2d_context_s *wq,
unsigned int canvas_addr,
unsigned int format);
unsigned int canvas_addr,
unsigned int format,
unsigned int phy_addr,
unsigned int stride);
void ge2dgen_src_clip(struct ge2d_context_s *wq,
int x, int y, int w, int h);
@@ -66,8 +72,6 @@ void ge2dgent_rendering_dir(struct ge2d_context_s *wq,
int src_x_dir, int src_y_dir,
int dst_x_dir, int dst_y_dir);
void ge2dgen_src2(struct ge2d_context_s *wq,
unsigned int canvas_addr, unsigned int format);
void ge2dgen_dst_clip(struct ge2d_context_s *wq,
int x, int y, int w, int h, int mode);

2
drivers/amlogic/media/osd/osd_hw.c
View File

@@ -2373,7 +2373,7 @@ void osd_get_info(u32 index, u32 *addr, u32 *width, u32 *height)
{
*addr = osd_hw.fb_gem[index].addr;
*width = osd_hw.fb_gem[index].width;
*height = osd_hw.fb_gem[index].height;
*height = osd_hw.fb_gem[index].yres;
}
static void osd1_update_disp_scale_enable(void)

15
include/linux/amlogic/media/ge2d/ge2d.h
View File

@@ -382,8 +382,15 @@ struct ge2d_src1_data_s {
unsigned char mode_8b_sel;
unsigned char lut_en;
unsigned char deep_color;
unsigned char mult_rounding;
unsigned char alpha_conv_mode0;
unsigned char alpha_conv_mode1;
unsigned char color_conv_mode0;
unsigned char color_conv_mode1;
unsigned int def_color;
unsigned int format_all;
unsigned int phy_addr;
unsigned int stride;
};
struct ge2d_src1_gen_s {
@@ -432,6 +439,10 @@ struct ge2d_src2_dst_data_s {
unsigned char dst2_discard_mode;
unsigned char dst2_enable;
unsigned int src2_phyaddr;
unsigned int src2_stride;
unsigned int dst_phyaddr;
unsigned int dst_stride;
};
struct ge2d_src2_dst_gen_s {
@@ -654,6 +665,8 @@ struct src_dst_para_s {
int canvas_index;
int bpp;
int ge2d_color_index;
int phy_addr;
int stride;
};
enum ge2d_op_type_e {
@@ -968,7 +981,7 @@ extern struct ge2d_src2_dst_gen_s
extern struct ge2d_dp_gen_s *ge2d_wq_get_dp_gen(struct ge2d_context_s *wq);
extern struct ge2d_cmd_s *ge2d_wq_get_cmd(struct ge2d_context_s *wq);
extern int ge2d_wq_add_work(struct ge2d_context_s *wq);
void ge2d_canv_config(u32 index, u32 addr, u32 stride);
#include "ge2d_func.h"