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thermal: rockchip: Support the rk3562 SoC in thermal driver

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There are one Temperature Sensor on rk3562, channel 0 is for chip.

Signed-off-by: Shaohan Yao <shaohan.yao@rock-chips.com>
Change-Id: Ided46b86470bb9cd506206bb4880ca024c0ec5cf
This commit is contained in:
Shaohan Yao
2022-10-28 15:06:35 +08:00
committed by Tao Huang
parent 86921d7d83
commit dfdb9d1b2f
1 changed files with 105 additions and 0 deletions
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105
drivers/thermal/rockchip_thermal.c
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@@ -269,7 +269,10 @@ struct rockchip_thermal_data {
#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
#define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */
#define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
#define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */
#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
@@ -289,6 +292,8 @@ struct rockchip_thermal_data {
#define RK3528_GRF_TSADC_CON 0x40030
#define RK3562_GRF_TSADC_CON 0x0580
#define RK3568_GRF_TSADC_CON 0x0600
#define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
#define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
@@ -655,6 +660,45 @@ static const struct tsadc_table rk3528_code_table[] = {
{TSADCV5_DATA_MASK, 125000},
};
static const struct tsadc_table rk3562_code_table[] = {
{0, -40000},
{1419, -40000},
{1428, -35000},
{1436, -30000},
{1445, -25000},
{1453, -20000},
{1462, -15000},
{1470, -10000},
{1479, -5000},
{1487, 0},
{1496, 5000},
{1504, 10000},
{1512, 15000},
{1521, 20000},
{1529, 25000},
{1538, 30000},
{1546, 35000},
{1555, 40000},
{1563, 45000},
{1572, 50000},
{1580, 55000},
{1589, 60000},
{1598, 65000},
{1606, 70000},
{1615, 75000},
{1623, 80000},
{1632, 85000},
{1640, 90000},
{1648, 95000},
{1657, 100000},
{1666, 105000},
{1674, 110000},
{1682, 115000},
{1691, 120000},
{1699, 125000},
{TSADCV2_DATA_MASK, 125000},
};
static const struct tsadc_table rk3568_code_table[] = {
{0, -40000},
{1584, -40000},
@@ -1107,6 +1151,37 @@ static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs,
}
}
static void rk_tsadcv12_initialize(struct regmap *grf, void __iomem *regs,
enum tshut_polarity tshut_polarity)
{
writel_relaxed(TSADCV12_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
writel_relaxed(TSADCV12_AUTO_PERIOD_HT_TIME,
regs + TSADCV3_AUTO_PERIOD_HT);
writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
regs + TSADCV3_HIGHT_INT_DEBOUNCE);
writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
writel_relaxed(TSADCV12_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
regs + TSADCV2_AUTO_CON);
if (tshut_polarity == TSHUT_HIGH_ACTIVE)
writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
TSADCV2_AUTO_TSHUT_POLARITY_MASK,
regs + TSADCV2_AUTO_CON);
else
writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
regs + TSADCV2_AUTO_CON);
if (!IS_ERR(grf)) {
regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
udelay(15);
regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
usleep_range(100, 200);
}
}
static void rk_tsadcv2_irq_ack(void __iomem *regs)
{
u32 val;
@@ -1767,6 +1842,30 @@ static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
},
};
static const struct rockchip_tsadc_chip rk3562_tsadc_data = {
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
.chn_num = 1, /* one channels for tsadc */
.tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
.tshut_temp = 95000,
.initialize = rk_tsadcv12_initialize,
.irq_ack = rk_tsadcv4_irq_ack,
.control = rk_tsadcv4_control,
.get_temp = rk_tsadcv4_get_temp,
.set_alarm_temp = rk_tsadcv3_alarm_temp,
.set_tshut_temp = rk_tsadcv3_tshut_temp,
.set_tshut_mode = rk_tsadcv4_tshut_mode,
.table = {
.id = rk3562_code_table,
.length = ARRAY_SIZE(rk3562_code_table),
.data_mask = TSADCV2_DATA_MASK,
.mode = ADC_INCREMENT,
},
};
static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
@@ -1899,6 +1998,12 @@ static const struct of_device_id of_rockchip_thermal_match[] = {
.data = (void *)&rk3528_tsadc_data,
},
#endif
#ifdef CONFIG_CPU_RK3562
{
.compatible = "rockchip,rk3562-tsadc",
.data = (void *)&rk3562_tsadc_data,
},
#endif
#ifdef CONFIG_CPU_RK3568
{
.compatible = "rockchip,rk3568-tsadc",