ARM: rockchip: rk3036 add cpu axi bus support

This commit is contained in:
黄涛
2014-07-17 22:23:54 +08:00
parent bf9fcb917c
commit e005a30415
2 changed files with 47 additions and 1 deletions

View File

@@ -50,6 +50,51 @@
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
cpu_axi_bus: cpu_axi_bus {
compatible = "rockchip,cpu_axi_bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
qos {
#address-cells = <1>;
#size-cells = <1>;
ranges;
core {
reg = <0x1012a000 0x20>;
rockchip,priority = <3 2>;
};
peri {
reg = <0x1012c000 0x20>;
};
gpu {
reg = <0x1012d000 0x20>;
};
vpu {
reg = <0x1012e000 0x20>;
};
hevc {
reg = <0x1012e080 0x20>;
};
vio {
reg = <0x1012f000 0x20>;
rockchip,priority = <3 3>;
};
};
msch {
#address-cells = <1>;
#size-cells = <1>;
ranges;
msch@10128000 {
reg = <0x10128000 0x40>;
rockchip,read-latency = <0x80>;
};
};
};
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x2000>;

View File

@@ -12,7 +12,8 @@
#define CPU_AXI_QOS_MODE_LIMITER 2
#define CPU_AXI_QOS_MODE_REGULATOR 3
#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 2) | ((l) & 3))
#define CPU_AXI_QOS_PRIORITY_LEVEL(h, l) \
((((h) & 3) << 8) | (((h) & 3) << 2) | ((l) & 3))
#define CPU_AXI_SET_QOS_PRIORITY(h, l, base) \
writel_relaxed(CPU_AXI_QOS_PRIORITY_LEVEL(h, l), base + CPU_AXI_QOS_PRIORITY)