shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-07 19:30:30 +09:00
Code Issues Packages Projects Releases Wiki Activity

clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1

Browse Source 
Change-Id: Icd566864d3651e7b64ee8209b66e8a326011422f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Xing Zheng
2016-07-27 10:50:12 +08:00
committed by Tao Huang
parent d856a9e4a5
commit e04b0bc907
2 changed files with 7 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/rockchip/clk-rk3399.c
View File

@@ -435,9 +435,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 6, GFLAGS),
GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),

8
include/dt-bindings/clock/rk3399-cru.h
View File

@@ -131,9 +131,11 @@
#define SCLK_DPHY_RX0_CFG 165
#define SCLK_RMII_SRC 166
#define SCLK_PCIEPHY_REF100M 167
#define SCLK_DDRC 168
#define SCLK_TESTCLKOUT1 169
#define SCLK_TESTCLKOUT2 170
#define SCLK_USBPHY0_480M_SRC 168
#define SCLK_USBPHY1_480M_SRC 169
#define SCLK_DDRC 170
#define SCLK_TESTCLKOUT2 171
#define SCLK_TESTCLKOUT1 179
#define DCLK_VOP0 180
#define DCLK_VOP1 181