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Merge tag 'v6.1.53' of git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable into odroidg12-6.1.y

Browse Source 
This is the 6.1.53 stable release

Change-Id: Ib544e5a42e702010650d66f57ae256bf8383af68
This commit is contained in:
Mauro (mdrjr) Ribeiro
2023-10-02 16:14:31 -03:00
parent bb3d21acb6 09045dae0d
commit e04f50fd44
704 changed files with 5868 additions and 3175 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/ABI/testing/sysfs-bus-fsi-devices-sbefifo
View File

@@ -5,6 +5,6 @@ Description:
Indicates whether or not this SBE device has experienced a
timeout; i.e. the SBE did not respond within the time allotted
by the driver. A value of 1 indicates that a timeout has
ocurred and no transfers have completed since the timeout. A
value of 0 indicates that no timeout has ocurred, or if one
has, more recent transfers have completed successful.
occurred and no transfers have completed since the timeout. A
value of 0 indicates that no timeout has occurred, or if one
has, more recent transfers have completed successfully.

2
Documentation/ABI/testing/sysfs-driver-chromeos-acpi
View File

@@ -134,4 +134,4 @@ KernelVersion: 5.19
Description:
Returns the verified boot data block shared between the
firmware verification step and the kernel verification step
(binary).
(hex dump).

1
Documentation/devicetree/bindings/extcon/maxim,max77843.yaml
View File

@@ -23,6 +23,7 @@ properties:
connector:
$ref: /schemas/connector/usb-connector.yaml#
unevaluatedProperties: false
ports:
$ref: /schemas/graph.yaml#/properties/ports

4
Documentation/scsi/scsi_mid_low_api.rst
View File

@@ -1190,11 +1190,11 @@ Members of interest:
- pointer to scsi_device object that this command is
associated with.
resid
- an LLD should set this signed integer to the requested
- an LLD should set this unsigned integer to the requested
transfer length (i.e. 'request_bufflen') less the number
of bytes that are actually transferred. 'resid' is
preset to 0 so an LLD can ignore it if it cannot detect
underruns (overruns should be rare). If possible an LLD
underruns (overruns should not be reported). An LLD
should set 'resid' prior to invoking 'done'. The most
interesting case is data transfers from a SCSI target
device (e.g. READs) that underrun.

7
Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst
View File

@@ -2923,6 +2923,13 @@ This structure contains all loop filter related parameters. See sections
- ``poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- PocLtCurr as described in section 8.3.2 "Decoding process for reference
picture set": provides the index of the long term references in DPB array.
* - __u8
- ``num_delta_pocs_of_ref_rps_idx``
- When the short_term_ref_pic_set_sps_flag in the slice header is equal to 0,
it is the same as the derived value NumDeltaPocs[RefRpsIdx]. It can be used to parse
the RPS data in slice headers instead of skipping it with @short_term_ref_pic_set_size.
When the value of short_term_ref_pic_set_sps_flag in the slice header is
equal to 1, num_delta_pocs_of_ref_rps_idx shall be set to 0.
* - struct :c:type:`v4l2_hevc_dpb_entry`
- ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]``
- The decoded picture buffer, for meta-data about reference frames.

6
Makefile
View File

@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 6
PATCHLEVEL = 1
SUBLEVEL = 52
SUBLEVEL = 53
EXTRAVERSION =
NAME = Curry Ramen
@@ -1291,7 +1291,7 @@ prepare0: archprepare
# All the preparing..
prepare: prepare0
ifdef CONFIG_RUST
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/rust_is_available.sh -v
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/rust_is_available.sh
$(Q)$(MAKE) $(build)=rust
endif
@@ -1817,7 +1817,7 @@ $(DOC_TARGETS):
# "Is Rust available?" target
PHONY += rustavailable
rustavailable:
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/rust_is_available.sh -v && echo "Rust is available!"
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/rust_is_available.sh && echo "Rust is available!"
# Documentation target
#

8
arch/arm/boot/dts/Makefile
View File

@@ -331,6 +331,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
kirkwood-iconnect.dtb \
kirkwood-iomega_ix2_200.dtb \
kirkwood-is2.dtb \
kirkwood-km_fixedeth.dtb \
kirkwood-km_kirkwood.dtb \
kirkwood-l-50.dtb \
kirkwood-laplug.dtb \
@@ -861,7 +862,10 @@ dtb-$(CONFIG_ARCH_OMAP3) += \
am3517-craneboard.dtb \
am3517-evm.dtb \
am3517_mt_ventoux.dtb \
logicpd-torpedo-35xx-devkit.dtb \
logicpd-torpedo-37xx-devkit.dtb \
logicpd-torpedo-37xx-devkit-28.dtb \
logicpd-som-lv-35xx-devkit.dtb \
logicpd-som-lv-37xx-devkit.dtb \
omap3430-sdp.dtb \
omap3-beagle.dtb \
@@ -1527,6 +1531,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-388-helios4.dtb \
armada-388-rd.dtb
dtb-$(CONFIG_MACH_ARMADA_39X) += \
armada-390-db.dtb \
armada-395-gp.dtb \
armada-398-db.dtb
dtb-$(CONFIG_MACH_ARMADA_XP) += \
armada-xp-axpwifiap.dtb \
@@ -1556,6 +1562,7 @@ dtb-$(CONFIG_MACH_DOVE) += \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt2701-evb.dtb \
mt6580-evbp1.dtb \
mt6582-prestigio-pmt5008-3g.dtb \
mt6589-aquaris5.dtb \
mt6589-fairphone-fp1.dtb \
mt6592-evb.dtb \
@@ -1608,6 +1615,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-intel-s2600wf.dtb \
aspeed-bmc-inspur-fp5280g2.dtb \
aspeed-bmc-inspur-nf5280m6.dtb \
aspeed-bmc-inspur-on5263m5.dtb \
aspeed-bmc-lenovo-hr630.dtb \
aspeed-bmc-lenovo-hr855xg2.dtb \
aspeed-bmc-microsoft-olympus.dtb \

13
arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts
View File

@@ -46,3 +46,16 @@
};
};
};
&gmac0 {
phy-mode = "rgmii";
phy-handle = <&bcm54210e>;
mdio {
/delete-node/ switch@1e;
bcm54210e: ethernet-phy@0 {
reg = <0>;
};
};
};

13
arch/arm/boot/dts/bcm47189-luxul-xap-810.dts
View File

@@ -83,3 +83,16 @@
};
};
};
&gmac0 {
phy-mode = "rgmii";
phy-handle = <&bcm54210e>;
mdio {
/delete-node/ switch@1e;
bcm54210e: ethernet-phy@0 {
reg = <0>;
};
};
};

4
arch/arm/boot/dts/bcm47189-tenda-ac9.dts
View File

@@ -135,8 +135,8 @@
label = "lan4";
};
port@5 {
reg = <5>;
port@8 {
reg = <8>;
label = "cpu";
ethernet = <&gmac0>;
};

5
arch/arm/boot/dts/bcm53573.dtsi
View File

@@ -127,6 +127,9 @@
pcie0: pcie@2000 {
reg = <0x00002000 0x1000>;
#address-cells = <3>;
#size-cells = <2>;
};
usb2: usb2@4000 {
@@ -156,8 +159,6 @@
};
ohci: usb@d000 {
#usb-cells = <0>;
compatible = "generic-ohci";
reg = <0xd000 0x1000>;
interrupt-parent = <&gic>;

6
arch/arm/boot/dts/bcm947189acdbmr.dts
View File

@@ -60,9 +60,9 @@
spi {
compatible = "spi-gpio";
num-chipselects = <1>;
gpio-sck = <&chipcommon 21 0>;
gpio-miso = <&chipcommon 22 0>;
gpio-mosi = <&chipcommon 23 0>;
sck-gpios = <&chipcommon 21 0>;
miso-gpios = <&chipcommon 22 0>;
mosi-gpios = <&chipcommon 23 0>;
cs-gpios = <&chipcommon 24 0>;
#address-cells = <1>;
#size-cells = <0>;

6
arch/arm/boot/dts/imx7s.dtsi
View File

@@ -1184,6 +1184,8 @@
<&clks IMX7D_USDHC1_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
status = "disabled";
};
@@ -1196,6 +1198,8 @@
<&clks IMX7D_USDHC2_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
status = "disabled";
};
@@ -1208,6 +1212,8 @@
<&clks IMX7D_USDHC3_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
status = "disabled";
};

9
arch/arm/boot/dts/qcom-ipq4019.dtsi
View File

@@ -228,9 +228,12 @@
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <8>;
clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_DCD_XO_CLK>;
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo>;
clock-names = "iface",
"core",
"xo";
status = "disabled";
};

2
arch/arm/boot/dts/s3c6410-mini6410.dts
View File

@@ -51,7 +51,7 @@
ethernet@18000000 {
compatible = "davicom,dm9000";
reg = <0x18000000 0x2 0x18000004 0x2>;
reg = <0x18000000 0x2>, <0x18000004 0x2>;
interrupt-parent = <&gpn>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
davicom,no-eeprom;

10
arch/arm/boot/dts/s5pv210-smdkv210.dts
View File

@@ -41,7 +41,7 @@
ethernet@a8000000 {
compatible = "davicom,dm9000";
reg = <0xA8000000 0x2 0xA8000002 0x2>;
reg = <0xa8000000 0x2>, <0xa8000002 0x2>;
interrupt-parent = <&gph1>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
local-mac-address = [00 00 de ad be ef];
@@ -55,6 +55,14 @@
default-brightness-level = <6>;
pinctrl-names = "default";
pinctrl-0 = <&pwm3_out>;
power-supply = <&dc5v_reg>;
};
dc5v_reg: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "DC5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};

21
arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi
View File

@@ -68,11 +68,6 @@
reg = <0x38000000 0x10000>;
no-map;
};
gpu_reserved: gpu@dc000000 {
reg = <0xdc000000 0x4000000>;
no-map;
};
};
led: gpio_leds {
@@ -102,9 +97,11 @@
adc1: adc@0 {
pinctrl-names = "default";
pinctrl-0 = <&adc1_in6_pins_a>;
st,min-sample-time-nsecs = <5000>;
st,adc-channels = <6>;
status = "disabled";
channel@6 {
reg = <6>;
st,min-sample-time-ns = <5000>;
};
};
adc2: adc@100 {
@@ -173,7 +170,7 @@
phy-handle = <&phy0>;
st,eth-ref-clk-sel;
mdio0 {
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
@@ -183,10 +180,6 @@
};
};
&gpu {
contiguous-area = <&gpu_reserved>;
};
&hash1 {
status = "okay";
};
@@ -375,8 +368,8 @@
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
mbox-names = "vq0", "vq1", "shutdown";
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
mbox-names = "vq0", "vq1", "shutdown", "detach";
interrupt-parent = <&exti>;
interrupts = <68 1>;
interrupt-names = "wdg";

2
arch/arm/boot/dts/stm32mp157c-ev1.dts
View File

@@ -144,7 +144,7 @@
max-speed = <1000>;
phy-handle = <&phy0>;
mdio0 {
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";

2
arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts
View File

@@ -112,7 +112,7 @@
phy-handle = <&ethphy>;
status = "okay";
mdio0 {
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;

14
arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi
View File

@@ -62,11 +62,6 @@
reg = <0x38000000 0x10000>;
no-map;
};
gpu_reserved: gpu@d4000000 {
reg = <0xd4000000 0x4000000>;
no-map;
};
};
led {
@@ -80,11 +75,6 @@
};
};
&gpu {
contiguous-area = <&gpu_reserved>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
@@ -240,8 +230,8 @@
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
mbox-names = "vq0", "vq1", "shutdown";
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
mbox-names = "vq0", "vq1", "shutdown", "detach";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";

2
arch/arm/boot/dts/stm32mp157c-odyssey.dts
View File

@@ -41,7 +41,7 @@
assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */
st,eth-clk-sel;
mdio0 {
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";

24
arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi
View File

@@ -80,17 +80,19 @@
vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "okay";
};
adc1: adc@0 {
st,min-sample-time-nsecs = <5000>;
st,adc-channels = <0>;
status = "okay";
&adc1 {
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
};
adc2: adc@100 {
st,adc-channels = <1>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
&adc2 {
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
};
@@ -125,7 +127,7 @@
max-speed = <100>;
phy-handle = <&phy0>;
mdio0 {
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
@@ -414,8 +416,8 @@
&m4_rproc {
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
<&vdev0vring1>, <&vdev0buffer>;
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
mbox-names = "vq0", "vq1", "shutdown";
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
mbox-names = "vq0", "vq1", "shutdown", "detach";
interrupt-parent = <&exti>;
interrupts = <68 1>;
status = "okay";

40
arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
View File

@@ -112,17 +112,39 @@
vdda-supply = <&vdda>;
vref-supply = <&vdda>;
status = "okay";
};
adc1: adc@0 {
st,adc-channels = <0 1 6>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
&adc1 {
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
adc2: adc@100 {
st,adc-channels = <0 1 2>;
st,min-sample-time-nsecs = <5000>;
status = "okay";
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
channel@6 {
reg = <6>;
st,min-sample-time-ns = <5000>;
};
};
&adc2 {
channel@0 {
reg = <0>;
st,min-sample-time-ns = <5000>;
};
channel@1 {
reg = <1>;
st,min-sample-time-ns = <5000>;
};
channel@2 {
reg = <2>;
st,min-sample-time-ns = <5000>;
};
};
@@ -151,7 +173,7 @@
max-speed = <1000>;
phy-handle = <&phy0>;
mdio0 {
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";

2
arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi
View File

@@ -78,7 +78,7 @@
max-speed = <1000>;
phy-handle = <&phy0>;
mdio0 {
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";

2
arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
View File

@@ -141,7 +141,7 @@
max-speed = <1000>;
phy-handle = <&phy0>;
mdio0 {
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";

3
arch/arm/include/asm/syscall.h
View File

@@ -25,6 +25,9 @@ static inline int syscall_get_nr(struct task_struct *task,
if (IS_ENABLED(CONFIG_AEABI) && !IS_ENABLED(CONFIG_OABI_COMPAT))
return task_thread_info(task)->abi_syscall;
if (task_thread_info(task)->abi_syscall == -1)
return -1;
return task_thread_info(task)->abi_syscall & __NR_SYSCALL_MASK;
}

1
arch/arm/kernel/entry-common.S
View File

@@ -103,6 +103,7 @@ slow_work_pending:
cmp r0, #0
beq no_work_pending
movlt scno, #(__NR_restart_syscall - __NR_SYSCALL_BASE)
str scno, [tsk, #TI_ABI_SYSCALL] @ make sure tracers see update
ldmia sp, {r0 - r6} @ have to reload r0 - r6
b local_restart @ ... and off we go
ENDPROC(ret_fast_syscall)

5
arch/arm/kernel/ptrace.c
View File

@@ -785,8 +785,9 @@ long arch_ptrace(struct task_struct *child, long request,
break;
case PTRACE_SET_SYSCALL:
task_thread_info(child)->abi_syscall = data &
__NR_SYSCALL_MASK;
if (data != -1)
data &= __NR_SYSCALL_MASK;
task_thread_info(child)->abi_syscall = data;
ret = 0;
break;

2
arch/arm/mach-omap2/powerdomain.c
View File

@@ -174,7 +174,7 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
break;
case PWRDM_STATE_PREV:
prev = pwrdm_read_prev_pwrst(pwrdm);
if (pwrdm->state != prev)
if (prev >= 0 && pwrdm->state != prev)
pwrdm->state_counter[prev]++;
if (prev == PWRDM_POWER_RET)
_update_logic_membank_counters(pwrdm);

1
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
View File

@@ -1312,6 +1312,7 @@
uartd: serial@70006300 {
compatible = "nvidia,tegra30-hsuart";
reset-names = "serial";
status = "okay";
bluetooth {

1
arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
View File

@@ -2004,6 +2004,7 @@
serial@3100000 {
compatible = "nvidia,tegra194-hsuart";
reset-names = "serial";
status = "okay";
};

6
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
View File

@@ -289,9 +289,9 @@
clock-names = "xclk";
clock-frequency = <23880000>;
vdddo-supply = <&camera_vdddo_1v8>;
vdda-supply = <&camera_vdda_2v8>;
vddd-supply = <&camera_vddd_1v5>;
DOVDD-supply = <&camera_vdddo_1v8>;
AVDD-supply = <&camera_vdda_2v8>;
DVDD-supply = <&camera_vddd_1v5>;
/* No camera mezzanine by default */
status = "disabled";

2
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
View File

@@ -163,7 +163,7 @@
pinctrl-0 = <&light_int_default>;
vdd-supply = <&pm8916_l17>;
vio-supply = <&pm8916_l6>;
vddio-supply = <&pm8916_l6>;
};
gyroscope@68 {

2
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts
View File

@@ -81,7 +81,7 @@
#size-cells = <0>;
interrupt-parent = <&tlmm>;
interrupts = <125 IRQ_TYPE_LEVEL_LOW>;
vdda-supply = <&vreg_l6a_1p8>;
vio-supply = <&vreg_l6a_1p8>;
vdd-supply = <&vdd_3v2_tp>;
reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;

5
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@@ -1063,7 +1063,7 @@
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
interrupts = <5>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_BYTE1_CLK>,
@@ -3292,6 +3292,9 @@
#size-cells = <1>;
ranges;
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq";
clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
<&gcc GCC_USB20_MASTER_CLK>,
<&gcc GCC_USB20_MOCK_UTMI_CLK>,

8
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@@ -2418,10 +2418,10 @@
clocks = <&mmcc MNOC_AHB_CLK>,
<&mmcc BIMC_SMMU_AHB_CLK>,
<&rpmcc RPM_SMD_MMAXI_CLK>,
<&mmcc BIMC_SMMU_AXI_CLK>;
clock-names = "iface-mm", "iface-smmu",
"bus-mm", "bus-smmu";
clock-names = "iface-mm",
"iface-smmu",
"bus-smmu";
#global-interrupts = <0>;
interrupts =
@@ -2445,6 +2445,8 @@
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc BIMC_SMMU_GDSC>;
};
remoteproc_adsp: remoteproc@17300000 {

5
arch/arm64/boot/dts/qcom/pm6150l.dtsi
View File

@@ -75,8 +75,9 @@
pm6150l_wled: leds@d800 {
compatible = "qcom,pm6150l-wled";
reg = <0xd800>, <0xd900>;
interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp";
interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x5 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
label = "backlight";
status = "disabled";

5
arch/arm64/boot/dts/qcom/pm660l.dtsi
View File

@@ -74,8 +74,9 @@
pm660l_wled: leds@d800 {
compatible = "qcom,pm660l-wled";
reg = <0xd800>, <0xd900>;
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp";
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
label = "backlight";
status = "disabled";

2
arch/arm64/boot/dts/qcom/pm8350.dtsi
View File

@@ -8,7 +8,7 @@
/ {
thermal-zones {
pm8350_thermal: pm8350c-thermal {
pm8350_thermal: pm8350-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350_temp_alarm>;

2
arch/arm64/boot/dts/qcom/pm8350b.dtsi
View File

@@ -8,7 +8,7 @@
/ {
thermal-zones {
pm8350b_thermal: pm8350c-thermal {
pm8350b_thermal: pm8350b-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350b_temp_alarm>;

5
arch/arm64/boot/dts/qcom/pmi8994.dtsi
View File

@@ -54,8 +54,9 @@
pmi8994_wled: wled@d800 {
compatible = "qcom,pmi8994-wled";
reg = <0xd800>, <0xd900>;
interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "short";
interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
<0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp", "short";
qcom,cabc;
qcom,external-pfet;
status = "disabled";

2
arch/arm64/boot/dts/qcom/pmk8350.dtsi
View File

@@ -44,7 +44,7 @@
};
pmk8350_adc_tm: adc-tm@3400 {
compatible = "qcom,adc-tm7";
compatible = "qcom,spmi-adc-tm5-gen2";
reg = <0x3400>;
interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;

2
arch/arm64/boot/dts/qcom/pmr735b.dtsi
View File

@@ -8,7 +8,7 @@
/ {
thermal-zones {
pmr735a_thermal: pmr735a-thermal {
pmr735b_thermal: pmr735b-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmr735b_temp_alarm>;

4
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
View File

@@ -57,7 +57,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>;
gpio = <&pmc8280_1_gpios 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
@@ -364,7 +364,7 @@
};
misc_3p3_reg_en: misc-3p3-reg-en-state {
pins = "gpio1";
pins = "gpio2";
function = "normal";
};
};

2
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@@ -347,7 +347,7 @@
};
&tlmm {
gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
gpio-reserved-ranges = <70 2>, <74 6>, <125 2>, <128 2>, <154 4>;
kybd_default: kybd-default-state {
disable {

1
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@@ -396,6 +396,7 @@
firmware {
scm: scm {
compatible = "qcom,scm-sc8280xp", "qcom,scm";
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
};
};

9
arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi
View File

@@ -14,6 +14,15 @@
qcom,msm-id = <321 0x20001>; /* SDM845 v2.1 */
qcom,board-id = <8 0>;
aliases {
serial0 = &uart6;
serial1 = &uart9;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";

3
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@@ -1099,6 +1099,7 @@
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SDM845_CX>;
};
qfprom@784000 {
@@ -2520,7 +2521,7 @@
<0 0>,
<0 0>,
<0 0>,
<0 300000000>;
<75000000 300000000>;
status = "disabled";
};

10
arch/arm64/boot/dts/qcom/sm6350.dtsi
View File

@@ -306,11 +306,6 @@
no-map;
};
pil_gpu_mem: memory@8b715400 {
reg = <0 0x8b715400 0 0x2000>;
no-map;
};
pil_modem_mem: memory@8b800000 {
reg = <0 0x8b800000 0 0xf800000>;
no-map;
@@ -331,6 +326,11 @@
no-map;
};
pil_gpu_mem: memory@f0d00000 {
reg = <0 0xf0d00000 0 0x1000>;
no-map;
};
debug_region: memory@ffb00000 {
reg = <0 0xffb00000 0 0xc0000>;
no-map;

2
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@@ -1196,7 +1196,7 @@
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c7_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";

233
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts
View File

@@ -14,3 +14,236 @@
};
/delete-node/ &vreg_l7f_1p8;
&pm8009_gpios {
gpio-line-names = "NC", /* GPIO_1 */
"CAM_PWR_LD_EN",
"WIDEC_PWR_EN",
"NC";
};
&pm8150_gpios {
gpio-line-names = "VOL_DOWN_N", /* GPIO_1 */
"OPTION_2",
"NC",
"PM_SLP_CLK_IN",
"OPTION_1",
"NC",
"NC",
"SP_ARI_PWR_ALARM",
"NC",
"NC"; /* GPIO_10 */
};
&pm8150b_gpios {
gpio-line-names = "SNAPSHOT_N", /* GPIO_1 */
"FOCUS_N",
"NC",
"NC",
"RF_LCD_ID_EN",
"NC",
"NC",
"LCD_ID",
"NC",
"WLC_EN_N", /* GPIO_10 */
"NC",
"RF_ID";
};
&pm8150l_gpios {
gpio-line-names = "NC", /* GPIO_1 */
"PM3003A_EN",
"NC",
"NC",
"NC",
"AUX2_THERM",
"BB_HP_EN",
"FP_LDO_EN",
"PMX_RESET_N",
"AUX3_THERM", /* GPIO_10 */
"DTV_PWR_EN",
"PM3003A_MODE";
};
&tlmm {
gpio-line-names = "AP_CTI_IN", /* GPIO_0 */
"MDM2AP_ERR_FATAL",
"AP_CTI_OUT",
"MDM2AP_STATUS",
"NFC_I2C_SDA",
"NFC_I2C_SCL",
"NFC_EN",
"NFC_CLK_REQ",
"NFC_ESE_PWR_REQ",
"DVDT_WRT_DET_AND",
"SPK_AMP_RESET_N", /* GPIO_10 */
"SPK_AMP_INT_N",
"APPS_I2C_1_SDA",
"APPS_I2C_1_SCL",
"NC",
"TX_GTR_THRES_IN",
"HST_BT_UART_CTS",
"HST_BT_UART_RFR",
"HST_BT_UART_TX",
"HST_BT_UART_RX",
"HST_WLAN_EN", /* GPIO_20 */
"HST_BT_EN",
"RGBC_IR_PWR_EN",
"FP_INT_N",
"NC",
"NC",
"NC",
"NC",
"NFC_ESE_SPI_MISO",
"NFC_ESE_SPI_MOSI",
"NFC_ESE_SPI_SCLK", /* GPIO_30 */
"NFC_ESE_SPI_CS_N",
"WCD_RST_N",
"NC",
"SDM_DEBUG_UART_TX",
"SDM_DEBUG_UART_RX",
"TS_I2C_SDA",
"TS_I2C_SCL",
"TS_INT_N",
"FP_SPI_MISO", /* GPIO_40 */
"FP_SPI_MOSI",
"FP_SPI_SCLK",
"FP_SPI_CS_N",
"APPS_I2C_0_SDA",
"APPS_I2C_0_SCL",
"DISP_ERR_FG",
"UIM2_DETECT_EN",
"NC",
"NC",
"NC", /* GPIO_50 */
"NC",
"MDM_UART_CTS",
"MDM_UART_RFR",
"MDM_UART_TX",
"MDM_UART_RX",
"AP2MDM_STATUS",
"AP2MDM_ERR_FATAL",
"MDM_IPC_HS_UART_TX",
"MDM_IPC_HS_UART_RX",
"NC", /* GPIO_60 */
"NC",
"NC",
"NC",
"NC",
"USB_CC_DIR",
"DISP_VSYNC",
"NC",
"NC",
"CAM_PWR_B_CS",
"NC", /* GPIO_70 */
"CAM_PWR_A_CS",
"SBU_SW_SEL",
"SBU_SW_OE",
"FP_RESET_N",
"FP_RESET_N",
"DISP_RESET_N",
"DEBUG_GPIO0",
"TRAY_DET",
"CAM2_RST_N",
"PCIE0_RST_N",
"PCIE0_CLK_REQ_N", /* GPIO_80 */
"PCIE0_WAKE_N",
"DVDT_ENABLE",
"DVDT_WRT_DET_OR",
"NC",
"PCIE2_RST_N",
"PCIE2_CLK_REQ_N",
"PCIE2_WAKE_N",
"MDM_VFR_IRQ0",
"MDM_VFR_IRQ1",
"SW_SERVICE", /* GPIO_90 */
"CAM_SOF",
"CAM1_RST_N",
"CAM0_RST_N",
"CAM0_MCLK",
"CAM1_MCLK",
"CAM2_MCLK",
"CAM3_MCLK",
"CAM4_MCLK",
"TOF_RST_N",
"NC", /* GPIO_100 */
"CCI0_I2C_SDA",
"CCI0_I2C_SCL",
"CCI1_I2C_SDA",
"CCI1_I2C_SCL_",
"CCI2_I2C_SDA",
"CCI2_I2C_SCL",
"CCI3_I2C_SDA",
"CCI3_I2C_SCL",
"CAM3_RST_N",
"NFC_DWL_REQ", /* GPIO_110 */
"NFC_IRQ",
"XVS",
"NC",
"RF_ID_EXTENSION",
"SPK_AMP_I2C_SDA",
"SPK_AMP_I2C_SCL",
"NC",
"NC",
"WLC_I2C_SDA",
"WLC_I2C_SCL", /* GPIO_120 */
"ACC_COVER_OPEN",
"ALS_PROX_INT_N",
"ACCEL_INT",
"WLAN_SW_CTRL",
"CAMSENSOR_I2C_SDA",
"CAMSENSOR_I2C_SCL",
"UDON_SWITCH_SEL",
"WDOG_DISABLE",
"BAROMETER_INT",
"NC", /* GPIO_130 */
"NC",
"FORCED_USB_BOOT",
"NC",
"NC",
"WLC_INT_N",
"NC",
"NC",
"RGBC_IR_INT",
"NC",
"NC", /* GPIO_140 */
"NC",
"BT_SLIMBUS_CLK",
"BT_SLIMBUS_DATA",
"HW_ID_0",
"HW_ID_1",
"WCD_SWR_TX_CLK",
"WCD_SWR_TX_DATA0",
"WCD_SWR_TX_DATA1",
"WCD_SWR_RX_CLK",
"WCD_SWR_RX_DATA0", /* GPIO_150 */
"WCD_SWR_RX_DATA1",
"SDM_DMIC_CLK1",
"SDM_DMIC_DATA1",
"SDM_DMIC_CLK2",
"SDM_DMIC_DATA2",
"SPK_AMP_I2S_CLK",
"SPK_AMP_I2S_WS",
"SPK_AMP_I2S_ASP_DIN",
"SPK_AMP_I2S_ASP_DOUT",
"COMPASS_I2C_SDA", /* GPIO_160 */
"COMPASS_I2C_SCL",
"NC",
"NC",
"SSC_SPI_1_MISO",
"SSC_SPI_1_MOSI",
"SSC_SPI_1_CLK",
"SSC_SPI_1_CS_N",
"NC",
"NC",
"SSC_SENSOR_I2C_SDA", /* GPIO_170 */
"SSC_SENSOR_I2C_SCL",
"NC",
"NC",
"NC",
"NC",
"HST_BLE_SNS_UART6_TX",
"HST_BLE_SNS_UART6_RX",
"HST_WLAN_UART_TX",
"HST_WLAN_UART_RX";
};

243
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts
View File

@@ -20,6 +20,8 @@
};
&gpio_keys {
pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &g_assist_n>;
g-assist-key {
label = "Google Assistant Key";
linux,code = <KEY_LEFTMETA>;
@@ -30,6 +32,247 @@
};
};
&pm8009_gpios {
gpio-line-names = "NC", /* GPIO_1 */
"NC",
"WIDEC_PWR_EN",
"NC";
};
&pm8150_gpios {
gpio-line-names = "VOL_DOWN_N", /* GPIO_1 */
"OPTION_2",
"NC",
"PM_SLP_CLK_IN",
"OPTION_1",
"G_ASSIST_N",
"NC",
"SP_ARI_PWR_ALARM",
"NC",
"NC"; /* GPIO_10 */
g_assist_n: g-assist-n-state {
pins = "gpio6";
function = "normal";
power-source = <1>;
bias-pull-up;
input-enable;
};
};
&pm8150b_gpios {
gpio-line-names = "SNAPSHOT_N", /* GPIO_1 */
"FOCUS_N",
"NC",
"NC",
"RF_LCD_ID_EN",
"NC",
"NC",
"LCD_ID",
"NC",
"NC", /* GPIO_10 */
"NC",
"RF_ID";
};
&pm8150l_gpios {
gpio-line-names = "NC", /* GPIO_1 */
"PM3003A_EN",
"NC",
"NC",
"NC",
"AUX2_THERM",
"BB_HP_EN",
"FP_LDO_EN",
"PMX_RESET_N",
"NC", /* GPIO_10 */
"NC",
"PM3003A_MODE";
};
&tlmm {
gpio-line-names = "AP_CTI_IN", /* GPIO_0 */
"MDM2AP_ERR_FATAL",
"AP_CTI_OUT",
"MDM2AP_STATUS",
"NFC_I2C_SDA",
"NFC_I2C_SCL",
"NFC_EN",
"NFC_CLK_REQ",
"NFC_ESE_PWR_REQ",
"DVDT_WRT_DET_AND",
"SPK_AMP_RESET_N", /* GPIO_10 */
"SPK_AMP_INT_N",
"APPS_I2C_1_SDA",
"APPS_I2C_1_SCL",
"NC",
"TX_GTR_THRES_IN",
"HST_BT_UART_CTS",
"HST_BT_UART_RFR",
"HST_BT_UART_TX",
"HST_BT_UART_RX",
"HST_WLAN_EN", /* GPIO_20 */
"HST_BT_EN",
"RGBC_IR_PWR_EN",
"FP_INT_N",
"NC",
"NC",
"NC",
"NC",
"NFC_ESE_SPI_MISO",
"NFC_ESE_SPI_MOSI",
"NFC_ESE_SPI_SCLK", /* GPIO_30 */
"NFC_ESE_SPI_CS_N",
"WCD_RST_N",
"NC",
"SDM_DEBUG_UART_TX",
"SDM_DEBUG_UART_RX",
"TS_I2C_SDA",
"TS_I2C_SCL",
"TS_INT_N",
"FP_SPI_MISO", /* GPIO_40 */
"FP_SPI_MOSI",
"FP_SPI_SCLK",
"FP_SPI_CS_N",
"APPS_I2C_0_SDA",
"APPS_I2C_0_SCL",
"DISP_ERR_FG",
"UIM2_DETECT_EN",
"NC",
"NC",
"NC", /* GPIO_50 */
"NC",
"MDM_UART_CTS",
"MDM_UART_RFR",
"MDM_UART_TX",
"MDM_UART_RX",
"AP2MDM_STATUS",
"AP2MDM_ERR_FATAL",
"MDM_IPC_HS_UART_TX",
"MDM_IPC_HS_UART_RX",
"NC", /* GPIO_60 */
"NC",
"NC",
"NC",
"NC",
"USB_CC_DIR",
"DISP_VSYNC",
"NC",
"NC",
"CAM_PWR_B_CS",
"NC", /* GPIO_70 */
"FRONTC_PWR_EN",
"SBU_SW_SEL",
"SBU_SW_OE",
"FP_RESET_N",
"FP_RESET_N",
"DISP_RESET_N",
"DEBUG_GPIO0",
"TRAY_DET",
"CAM2_RST_N",
"PCIE0_RST_N",
"PCIE0_CLK_REQ_N", /* GPIO_80 */
"PCIE0_WAKE_N",
"DVDT_ENABLE",
"DVDT_WRT_DET_OR",
"NC",
"PCIE2_RST_N",
"PCIE2_CLK_REQ_N",
"PCIE2_WAKE_N",
"MDM_VFR_IRQ0",
"MDM_VFR_IRQ1",
"SW_SERVICE", /* GPIO_90 */
"CAM_SOF",
"CAM1_RST_N",
"CAM0_RST_N",
"CAM0_MCLK",
"CAM1_MCLK",
"CAM2_MCLK",
"CAM3_MCLK",
"NC",
"NC",
"NC", /* GPIO_100 */
"CCI0_I2C_SDA",
"CCI0_I2C_SCL",
"CCI1_I2C_SDA",
"CCI1_I2C_SCL_",
"CCI2_I2C_SDA",
"CCI2_I2C_SCL",
"CCI3_I2C_SDA",
"CCI3_I2C_SCL",
"CAM3_RST_N",
"NFC_DWL_REQ", /* GPIO_110 */
"NFC_IRQ",
"XVS",
"NC",
"RF_ID_EXTENSION",
"SPK_AMP_I2C_SDA",
"SPK_AMP_I2C_SCL",
"NC",
"NC",
"NC",
"NC",
"ACC_COVER_OPEN",
"ALS_PROX_INT_N",
"ACCEL_INT",
"WLAN_SW_CTRL",
"CAMSENSOR_I2C_SDA",
"CAMSENSOR_I2C_SCL",
"UDON_SWITCH_SEL",
"WDOG_DISABLE",
"BAROMETER_INT",
"NC", /* GPIO_130 */
"NC",
"FORCED_USB_BOOT",
"NC",
"NC",
"NC",
"NC",
"NC",
"RGBC_IR_INT",
"NC",
"NC", /* GPIO_140 */
"NC",
"BT_SLIMBUS_CLK",
"BT_SLIMBUS_DATA",
"HW_ID_0",
"HW_ID_1",
"WCD_SWR_TX_CLK",
"WCD_SWR_TX_DATA0",
"WCD_SWR_TX_DATA1",
"WCD_SWR_RX_CLK",
"WCD_SWR_RX_DATA0", /* GPIO_150 */
"WCD_SWR_RX_DATA1",
"SDM_DMIC_CLK1",
"SDM_DMIC_DATA1",
"SDM_DMIC_CLK2",
"SDM_DMIC_DATA2",
"SPK_AMP_I2S_CLK",
"SPK_AMP_I2S_WS",
"SPK_AMP_I2S_ASP_DIN",
"SPK_AMP_I2S_ASP_DOUT",
"COMPASS_I2C_SDA", /* GPIO_160 */
"COMPASS_I2C_SCL",
"NC",
"NC",
"SSC_SPI_1_MISO",
"SSC_SPI_1_MOSI",
"SSC_SPI_1_CLK",
"SSC_SPI_1_CS_N",
"NC",
"NC",
"SSC_SENSOR_I2C_SDA", /* GPIO_170 */
"SSC_SENSOR_I2C_SCL",
"NC",
"NC",
"NC",
"NC",
"HST_BLE_SNS_UART6_TX",
"HST_BLE_SNS_UART6_RX",
"HST_WLAN_UART_TX",
"HST_WLAN_UART_RX";
};
&vreg_l2f_1p3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;

54
arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi
View File

@@ -51,12 +51,26 @@
gpio_keys: gpio-keys {
compatible = "gpio-keys";
/*
* Camera focus (light press) and camera snapshot (full press)
* seem not to work properly.. Adding the former one stalls the CPU
* and the latter kills the volume down key for whatever reason. In any
* case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1).
*/
pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>;
pinctrl-names = "default";
key-camera-focus {
label = "Camera Focus";
linux,code = <KEY_CAMERA_FOCUS>;
gpios = <&pm8150b_gpios 2 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
key-camera-snapshot {
label = "Camera Snapshot";
linux,code = <KEY_CAMERA>;
gpios = <&pm8150b_gpios 1 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
linux,can-disable;
wakeup-source;
};
key-vol-down {
label = "Volume Down";
@@ -546,6 +560,34 @@
vdda-pll-supply = <&vreg_l9a_1p2>;
};
&pm8150_gpios {
vol_down_n: vol-down-n-state {
pins = "gpio1";
function = "normal";
power-source = <0>;
bias-pull-up;
input-enable;
};
};
&pm8150b_gpios {
snapshot_n: snapshot-n-state {
pins = "gpio1";
function = "normal";
power-source = <0>;
bias-pull-up;
input-enable;
};
focus_n: focus-n-state {
pins = "gpio2";
function = "normal";
power-source = <0>;
bias-pull-up;
input-enable;
};
};
&pon_pwrkey {
status = "okay";
};

11
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@@ -99,7 +99,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
@@ -123,7 +123,7 @@
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
@@ -144,7 +144,7 @@
reg = <0x0 0x200>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
@@ -165,7 +165,7 @@
reg = <0x0 0x300>;
enable-method = "psci";
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
dynamic-power-coefficient = <105>;
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
@@ -1862,6 +1862,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
dma-coherent;
status = "disabled";
};
@@ -1968,6 +1969,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
dma-coherent;
status = "disabled";
};
@@ -2076,6 +2078,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
dma-coherent;
status = "disabled";
};

31
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@@ -63,7 +63,7 @@
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo685";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
@@ -82,7 +82,7 @@
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo685";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
@@ -98,7 +98,7 @@
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo685";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
@@ -114,7 +114,7 @@
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo685";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
@@ -130,7 +130,7 @@
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo685";
compatible = "arm,cortex-a78";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
@@ -146,7 +146,7 @@
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo685";
compatible = "arm,cortex-a78";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
@@ -163,7 +163,7 @@
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo685";
compatible = "arm,cortex-a78";
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
@@ -179,7 +179,7 @@
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo685";
compatible = "arm,cortex-x1";
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
@@ -236,8 +236,8 @@
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <355>;
exit-latency-us = <909>;
entry-latency-us = <360>;
exit-latency-us = <531>;
min-residency-us = <3934>;
local-timer-stop;
};
@@ -246,8 +246,8 @@
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <241>;
exit-latency-us = <1461>;
entry-latency-us = <702>;
exit-latency-us = <1061>;
min-residency-us = <4488>;
local-timer-stop;
};
@@ -2072,6 +2072,13 @@
<0 0x18593000 0 0x1000>;
reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh-irq-0",
"dcvsh-irq-1",
"dcvsh-irq-2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";

6
arch/arm64/include/asm/sdei.h
View File

@@ -17,6 +17,9 @@
#include <asm/virt.h>
DECLARE_PER_CPU(struct sdei_registered_event *, sdei_active_normal_event);
DECLARE_PER_CPU(struct sdei_registered_event *, sdei_active_critical_event);
extern unsigned long sdei_exit_mode;
/* Software Delegated Exception entry point from firmware*/
@@ -29,6 +32,9 @@ asmlinkage void __sdei_asm_entry_trampoline(unsigned long event_num,
unsigned long pc,
unsigned long pstate);
/* Abort a running handler. Context is discarded. */
void __sdei_handler_abort(void);
/*
* The above entry point does the minimum to call C code. This function does
* anything else, before calling the driver.

27
arch/arm64/kernel/entry.S
View File

@@ -993,9 +993,13 @@ SYM_CODE_START(__sdei_asm_handler)
mov x19, x1
#if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK)
/* Store the registered-event for crash_smp_send_stop() */
ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
#endif
cbnz w4, 1f
adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6
b 2f
1: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6
2: str x19, [x5]
#ifdef CONFIG_VMAP_STACK
/*
@@ -1062,6 +1066,14 @@ SYM_CODE_START(__sdei_asm_handler)
ldr_l x2, sdei_exit_mode
/* Clear the registered-event seen by crash_smp_send_stop() */
ldrb w3, [x4, #SDEI_EVENT_PRIORITY]
cbnz w3, 1f
adr_this_cpu dst=x5, sym=sdei_active_normal_event, tmp=x6
b 2f
1: adr_this_cpu dst=x5, sym=sdei_active_critical_event, tmp=x6
2: str xzr, [x5]
alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
sdei_handler_exit exit_mode=x2
alternative_else_nop_endif
@@ -1072,4 +1084,15 @@ alternative_else_nop_endif
#endif
SYM_CODE_END(__sdei_asm_handler)
NOKPROBE(__sdei_asm_handler)
SYM_CODE_START(__sdei_handler_abort)
mov_q x0, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
adr x1, 1f
ldr_l x2, sdei_exit_mode
sdei_handler_exit exit_mode=x2
// exit the handler and jump to the next instruction.
// Exit will stomp x0-x17, PSTATE, ELR_ELx, and SPSR_ELx.
1: ret
SYM_CODE_END(__sdei_handler_abort)
NOKPROBE(__sdei_handler_abort)
#endif /* CONFIG_ARM_SDE_INTERFACE */

25
arch/arm64/kernel/fpsimd.c
View File

@@ -1133,9 +1133,6 @@ void sve_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
*/
u64 read_zcr_features(void)
{
u64 zcr;
unsigned int vq_max;
/*
* Set the maximum possible VL, and write zeroes to all other
* bits to see if they stick.
@@ -1143,12 +1140,8 @@ u64 read_zcr_features(void)
sve_kernel_enable(NULL);
write_sysreg_s(ZCR_ELx_LEN_MASK, SYS_ZCR_EL1);
zcr = read_sysreg_s(SYS_ZCR_EL1);
zcr &= ~(u64)ZCR_ELx_LEN_MASK; /* find sticky 1s outside LEN field */
vq_max = sve_vq_from_vl(sve_get_vl());
zcr |= vq_max - 1; /* set LEN field to maximum effective value */
return zcr;
/* Return LEN value that would be written to get the maximum VL */
return sve_vq_from_vl(sve_get_vl()) - 1;
}
void __init sve_setup(void)
@@ -1292,11 +1285,7 @@ void fa64_kernel_enable(const struct arm64_cpu_capabilities *__always_unused p)
*/
u64 read_smcr_features(void)
{
u64 smcr;
unsigned int vq_max;
sme_kernel_enable(NULL);
sme_smstart_sm();
/*
* Set the maximum possible VL.
@@ -1304,14 +1293,8 @@ u64 read_smcr_features(void)
write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_LEN_MASK,
SYS_SMCR_EL1);
smcr = read_sysreg_s(SYS_SMCR_EL1);
smcr &= ~(u64)SMCR_ELx_LEN_MASK; /* Only the LEN field */
vq_max = sve_vq_from_vl(sve_get_vl());
smcr |= vq_max - 1; /* set LEN field to maximum effective value */
sme_smstop_sm();
return smcr;
/* Return LEN value that would be written to get the maximum VL */
return sve_vq_from_vl(sme_get_vl()) - 1;
}
void __init sme_setup(void)

3
arch/arm64/kernel/ptrace.c
View File

@@ -896,7 +896,8 @@ static int sve_set_common(struct task_struct *target,
break;
default:
WARN_ON_ONCE(1);
return -EINVAL;
ret = -EINVAL;
goto out;
}
/*

3
arch/arm64/kernel/sdei.c
View File

@@ -47,6 +47,9 @@ DEFINE_PER_CPU(unsigned long *, sdei_shadow_call_stack_normal_ptr);
DEFINE_PER_CPU(unsigned long *, sdei_shadow_call_stack_critical_ptr);
#endif
DEFINE_PER_CPU(struct sdei_registered_event *, sdei_active_normal_event);
DEFINE_PER_CPU(struct sdei_registered_event *, sdei_active_critical_event);
static void _free_sdei_stack(unsigned long * __percpu *ptr, int cpu)
{
unsigned long *p;

8
arch/arm64/kernel/smp.c
View File

@@ -1047,10 +1047,8 @@ void crash_smp_send_stop(void)
* If this cpu is the only one alive at this point in time, online or
* not, there are no stop messages to be sent around, so just back out.
*/
if (num_other_online_cpus() == 0) {
sdei_mask_local_cpu();
return;
}
if (num_other_online_cpus() == 0)
goto skip_ipi;
cpumask_copy(&mask, cpu_online_mask);
cpumask_clear_cpu(smp_processor_id(), &mask);
@@ -1069,7 +1067,9 @@ void crash_smp_send_stop(void)
pr_warn("SMP: failed to stop secondary CPUs %*pbl\n",
cpumask_pr_args(&mask));
skip_ipi:
sdei_mask_local_cpu();
sdei_handler_abort();
}
bool smp_crash_stop_failed(void)

2
arch/arm64/lib/csum.c
View File

@@ -24,7 +24,7 @@ unsigned int __no_sanitize_address do_csum(const unsigned char *buff, int len)
const u64 *ptr;
u64 data, sum64 = 0;
if (unlikely(len == 0))
if (unlikely(len <= 0))
return 0;
offset = (unsigned long)buff & 7;

2
arch/arm64/mm/hugetlbpage.c
View File

@@ -236,7 +236,7 @@ static void clear_flush(struct mm_struct *mm,
unsigned long i, saddr = addr;
for (i = 0; i < ncontig; i++, addr += pgsize, ptep++)
pte_clear(mm, addr, ptep);
ptep_clear(mm, addr, ptep);
flush_tlb_range(&vma, saddr, addr);
}

2
arch/loongarch/include/asm/loongarch.h
View File

@@ -1488,7 +1488,7 @@ __BUILD_CSR_OP(tlbidx)
#define write_fcsr(dest, val) \
do { \
__asm__ __volatile__( \
" movgr2fcsr %0, "__stringify(dest)" \n" \
" movgr2fcsr "__stringify(dest)", %0 \n" \
: : "r" (val)); \
} while (0)

2
arch/loongarch/include/asm/pgtable-bits.h
View File

@@ -21,12 +21,14 @@
#define _PAGE_HGLOBAL_SHIFT 12 /* HGlobal is a PMD bit */
#define _PAGE_PFN_SHIFT 12
#define _PAGE_PFN_END_SHIFT 48
#define _PAGE_PRESENT_INVALID_SHIFT 60
#define _PAGE_NO_READ_SHIFT 61
#define _PAGE_NO_EXEC_SHIFT 62
#define _PAGE_RPLV_SHIFT 63
/* Used by software */
#define _PAGE_PRESENT (_ULCAST_(1) << _PAGE_PRESENT_SHIFT)
#define _PAGE_PRESENT_INVALID (_ULCAST_(1) << _PAGE_PRESENT_INVALID_SHIFT)
#define _PAGE_WRITE (_ULCAST_(1) << _PAGE_WRITE_SHIFT)
#define _PAGE_ACCESSED (_ULCAST_(1) << _PAGE_ACCESSED_SHIFT)
#define _PAGE_MODIFIED (_ULCAST_(1) << _PAGE_MODIFIED_SHIFT)

6
arch/loongarch/include/asm/pgtable.h
View File

@@ -208,7 +208,7 @@ static inline int pmd_bad(pmd_t pmd)
static inline int pmd_present(pmd_t pmd)
{
if (unlikely(pmd_val(pmd) & _PAGE_HUGE))
return !!(pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE));
return !!(pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROTNONE | _PAGE_PRESENT_INVALID));
return pmd_val(pmd) != (unsigned long)invalid_pte_table;
}
@@ -525,6 +525,7 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
static inline pmd_t pmd_mkinvalid(pmd_t pmd)
{
pmd_val(pmd) |= _PAGE_PRESENT_INVALID;
pmd_val(pmd) &= ~(_PAGE_PRESENT | _PAGE_VALID | _PAGE_DIRTY | _PAGE_PROTNONE);
return pmd;
@@ -559,6 +560,9 @@ static inline long pmd_protnone(pmd_t pmd)
}
#endif /* CONFIG_NUMA_BALANCING */
#define pmd_leaf(pmd) ((pmd_val(pmd) & _PAGE_HUGE) != 0)
#define pud_leaf(pud) ((pud_val(pud) & _PAGE_HUGE) != 0)
/*
* We provide our own get_unmapped area to cope with the virtual aliasing
* constraints placed on us by the cache architecture.

4
arch/m68k/fpsp040/skeleton.S
View File

@@ -499,13 +499,13 @@ in_ea:
dbf %d0,morein
rts
.section .fixup,#alloc,#execinstr
.section .fixup,"ax"
.even
1:
jbsr fpsp040_die
jbra .Lnotkern
.section __ex_table,#alloc
.section __ex_table,"a"
.align 4
.long in_ea,1b

4
arch/m68k/ifpsp060/os.S
View File

@@ -379,11 +379,11 @@ _060_real_access:
| Execption handling for movs access to illegal memory
.section .fixup,#alloc,#execinstr
.section .fixup,"ax"
.even
1: moveq #-1,%d1
rts
.section __ex_table,#alloc
.section __ex_table,"a"
.align 4
.long dmrbuae,1b
.long dmrwuae,1b

4
arch/m68k/kernel/relocate_kernel.S
View File

@@ -26,7 +26,7 @@ ENTRY(relocate_new_kernel)
lea %pc@(.Lcopy),%a4
2: addl #0x00000000,%a4 /* virt_to_phys() */
.section ".m68k_fixup","aw"
.section .m68k_fixup,"aw"
.long M68K_FIXUP_MEMOFFSET, 2b+2
.previous
@@ -49,7 +49,7 @@ ENTRY(relocate_new_kernel)
lea %pc@(.Lcont040),%a4
5: addl #0x00000000,%a4 /* virt_to_phys() */
.section ".m68k_fixup","aw"
.section .m68k_fixup,"aw"
.long M68K_FIXUP_MEMOFFSET, 5b+2
.previous

1
arch/mips/Kconfig
View File

@@ -83,7 +83,6 @@ config MIPS
select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
select HAVE_MOD_ARCH_SPECIFIC
select HAVE_NMI
select HAVE_PATA_PLATFORM
select HAVE_PERF_EVENTS
select HAVE_PERF_REGS
select HAVE_PERF_USER_STACK_DUMP

13
arch/parisc/kernel/processor.c
View File

@@ -372,10 +372,18 @@ int
show_cpuinfo (struct seq_file *m, void *v)
{
unsigned long cpu;
char cpu_name[60], *p;
/* strip PA path from CPU name to not confuse lscpu */
strlcpy(cpu_name, per_cpu(cpu_data, 0).dev->name, sizeof(cpu_name));
p = strrchr(cpu_name, '[');
if (p)
*(--p) = 0;
for_each_online_cpu(cpu) {
const struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
#ifdef CONFIG_SMP
const struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
if (0 == cpuinfo->hpa)
continue;
#endif
@@ -420,8 +428,7 @@ show_cpuinfo (struct seq_file *m, void *v)
seq_printf(m, "model\t\t: %s - %s\n",
boot_cpu_data.pdc.sys_model_name,
cpuinfo->dev ?
cpuinfo->dev->name : "Unknown");
cpu_name);
seq_printf(m, "hversion\t: 0x%08x\n"
"sversion\t: 0x%08x\n",

6
arch/powerpc/boot/Makefile
View File

@@ -34,8 +34,6 @@ endif
BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
-fno-strict-aliasing -O2 -msoft-float -mno-altivec -mno-vsx \
$(call cc-option,-mno-prefixed) $(call cc-option,-mno-pcrel) \
$(call cc-option,-mno-mma) \
$(call cc-option,-mno-spe) $(call cc-option,-mspe=no) \
-pipe -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
$(LINUXINCLUDE)
@@ -71,6 +69,10 @@ BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -nostdinc
BOOTARFLAGS := -crD
BOOTCFLAGS += $(call cc-option,-mno-prefixed) \
$(call cc-option,-mno-pcrel) \
$(call cc-option,-mno-mma)
ifdef CONFIG_CC_IS_CLANG
BOOTCFLAGS += $(CLANG_FLAGS)
BOOTAFLAGS += $(CLANG_FLAGS)

13
arch/powerpc/include/asm/lppaca.h
View File

@@ -45,6 +45,7 @@
#include <asm/types.h>
#include <asm/mmu.h>
#include <asm/firmware.h>
#include <asm/paca.h>
/*
* The lppaca is the "virtual processor area" registered with the hypervisor,
@@ -127,13 +128,23 @@ struct lppaca {
*/
#define LPPACA_OLD_SHARED_PROC 2
static inline bool lppaca_shared_proc(struct lppaca *l)
#ifdef CONFIG_PPC_PSERIES
/*
* All CPUs should have the same shared proc value, so directly access the PACA
* to avoid false positives from DEBUG_PREEMPT.
*/
static inline bool lppaca_shared_proc(void)
{
struct lppaca *l = local_paca->lppaca_ptr;
if (!firmware_has_feature(FW_FEATURE_SPLPAR))
return false;
return !!(l->__old_status & LPPACA_OLD_SHARED_PROC);
}
#define get_lppaca() (get_paca()->lppaca_ptr)
#endif
/*
* SLB shadow buffer structure as defined in the PAPR. The save_area
* contains adjacent ESID and VSID pairs for each shadowed SLB. The

6
arch/powerpc/include/asm/paca.h
View File

@@ -15,7 +15,6 @@
#include <linux/cache.h>
#include <linux/string.h>
#include <asm/types.h>
#include <asm/lppaca.h>
#include <asm/mmu.h>
#include <asm/page.h>
#ifdef CONFIG_PPC_BOOK3E_64
@@ -47,14 +46,11 @@ extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
#define get_paca() local_paca
#endif
#ifdef CONFIG_PPC_PSERIES
#define get_lppaca() (get_paca()->lppaca_ptr)
#endif
#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
struct task_struct;
struct rtas_args;
struct lppaca;
/*
* Defines the layout of the paca.

1
arch/powerpc/include/asm/paravirt.h
View File

@@ -6,6 +6,7 @@
#include <asm/smp.h>
#ifdef CONFIG_PPC64
#include <asm/paca.h>
#include <asm/lppaca.h>
#include <asm/hvcall.h>
#endif

1
arch/powerpc/include/asm/plpar_wrappers.h
View File

@@ -9,6 +9,7 @@
#include <asm/hvcall.h>
#include <asm/paca.h>
#include <asm/lppaca.h>
#include <asm/page.h>
static inline long poll_pending(void)

1
arch/powerpc/kernel/fadump.c
View File

@@ -654,6 +654,7 @@ int __init fadump_reserve_mem(void)
return ret;
error_out:
fw_dump.fadump_enabled = 0;
fw_dump.reserve_dump_area_size = 0;
return 0;
}

17
arch/powerpc/kernel/iommu.c
View File

@@ -171,17 +171,28 @@ static int fail_iommu_bus_notify(struct notifier_block *nb,
return 0;
}
static struct notifier_block fail_iommu_bus_notifier = {
/*
* PCI and VIO buses need separate notifier_block structs, since they're linked
* list nodes. Sharing a notifier_block would mean that any notifiers later
* registered for PCI buses would also get called by VIO buses and vice versa.
*/
static struct notifier_block fail_iommu_pci_bus_notifier = {
.notifier_call = fail_iommu_bus_notify
};
#ifdef CONFIG_IBMVIO
static struct notifier_block fail_iommu_vio_bus_notifier = {
.notifier_call = fail_iommu_bus_notify
};
#endif
static int __init fail_iommu_setup(void)
{
#ifdef CONFIG_PCI
bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier);
bus_register_notifier(&pci_bus_type, &fail_iommu_pci_bus_notifier);
#endif
#ifdef CONFIG_IBMVIO
bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier);
bus_register_notifier(&vio_bus_type, &fail_iommu_vio_bus_notifier);
#endif
return 0;

1
arch/powerpc/kvm/book3s_hv_ras.c
View File

@@ -9,6 +9,7 @@
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <linux/kernel.h>
#include <asm/lppaca.h>
#include <asm/opal.h>
#include <asm/mce.h>
#include <asm/machdep.h>

240
arch/powerpc/mm/book3s64/radix_tlb.c
View File

@@ -127,21 +127,6 @@ static __always_inline void __tlbie_pid(unsigned long pid, unsigned long ric)
trace_tlbie(0, 0, rb, rs, ric, prs, r);
}
static __always_inline void __tlbie_pid_lpid(unsigned long pid,
unsigned long lpid,
unsigned long ric)
{
unsigned long rb, rs, prs, r;
rb = PPC_BIT(53); /* IS = 1 */
rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
prs = 1; /* process scoped */
r = 1; /* radix format */
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
trace_tlbie(0, 0, rb, rs, ric, prs, r);
}
static __always_inline void __tlbie_lpid(unsigned long lpid, unsigned long ric)
{
unsigned long rb,rs,prs,r;
@@ -202,23 +187,6 @@ static __always_inline void __tlbie_va(unsigned long va, unsigned long pid,
trace_tlbie(0, 0, rb, rs, ric, prs, r);
}
static __always_inline void __tlbie_va_lpid(unsigned long va, unsigned long pid,
unsigned long lpid,
unsigned long ap, unsigned long ric)
{
unsigned long rb, rs, prs, r;
rb = va & ~(PPC_BITMASK(52, 63));
rb |= ap << PPC_BITLSHIFT(58);
rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
prs = 1; /* process scoped */
r = 1; /* radix format */
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
trace_tlbie(0, 0, rb, rs, ric, prs, r);
}
static __always_inline void __tlbie_lpid_va(unsigned long va, unsigned long lpid,
unsigned long ap, unsigned long ric)
{
@@ -264,22 +232,6 @@ static inline void fixup_tlbie_va_range(unsigned long va, unsigned long pid,
}
}
static inline void fixup_tlbie_va_range_lpid(unsigned long va,
unsigned long pid,
unsigned long lpid,
unsigned long ap)
{
if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
asm volatile("ptesync" : : : "memory");
__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
}
if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
asm volatile("ptesync" : : : "memory");
__tlbie_va_lpid(va, pid, lpid, ap, RIC_FLUSH_TLB);
}
}
static inline void fixup_tlbie_pid(unsigned long pid)
{
/*
@@ -299,26 +251,6 @@ static inline void fixup_tlbie_pid(unsigned long pid)
}
}
static inline void fixup_tlbie_pid_lpid(unsigned long pid, unsigned long lpid)
{
/*
* We can use any address for the invalidation, pick one which is
* probably unused as an optimisation.
*/
unsigned long va = ((1UL << 52) - 1);
if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
asm volatile("ptesync" : : : "memory");
__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
}
if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
asm volatile("ptesync" : : : "memory");
__tlbie_va_lpid(va, pid, lpid, mmu_get_ap(MMU_PAGE_64K),
RIC_FLUSH_TLB);
}
}
static inline void fixup_tlbie_lpid_va(unsigned long va, unsigned long lpid,
unsigned long ap)
{
@@ -416,31 +348,6 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
static inline void _tlbie_pid_lpid(unsigned long pid, unsigned long lpid,
unsigned long ric)
{
asm volatile("ptesync" : : : "memory");
/*
* Workaround the fact that the "ric" argument to __tlbie_pid
* must be a compile-time contraint to match the "i" constraint
* in the asm statement.
*/
switch (ric) {
case RIC_FLUSH_TLB:
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_TLB);
fixup_tlbie_pid_lpid(pid, lpid);
break;
case RIC_FLUSH_PWC:
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
break;
case RIC_FLUSH_ALL:
default:
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_ALL);
fixup_tlbie_pid_lpid(pid, lpid);
}
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
}
struct tlbiel_pid {
unsigned long pid;
unsigned long ric;
@@ -566,20 +473,6 @@ static inline void __tlbie_va_range(unsigned long start, unsigned long end,
fixup_tlbie_va_range(addr - page_size, pid, ap);
}
static inline void __tlbie_va_range_lpid(unsigned long start, unsigned long end,
unsigned long pid, unsigned long lpid,
unsigned long page_size,
unsigned long psize)
{
unsigned long addr;
unsigned long ap = mmu_get_ap(psize);
for (addr = start; addr < end; addr += page_size)
__tlbie_va_lpid(addr, pid, lpid, ap, RIC_FLUSH_TLB);
fixup_tlbie_va_range_lpid(addr - page_size, pid, lpid, ap);
}
static __always_inline void _tlbie_va(unsigned long va, unsigned long pid,
unsigned long psize, unsigned long ric)
{
@@ -660,18 +553,6 @@ static inline void _tlbie_va_range(unsigned long start, unsigned long end,
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
static inline void _tlbie_va_range_lpid(unsigned long start, unsigned long end,
unsigned long pid, unsigned long lpid,
unsigned long page_size,
unsigned long psize, bool also_pwc)
{
asm volatile("ptesync" : : : "memory");
if (also_pwc)
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
__tlbie_va_range_lpid(start, end, pid, lpid, page_size, psize);
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
}
static inline void _tlbiel_va_range_multicast(struct mm_struct *mm,
unsigned long start, unsigned long end,
unsigned long pid, unsigned long page_size,
@@ -1476,6 +1357,127 @@ void radix__flush_tlb_all(void)
}
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
static __always_inline void __tlbie_pid_lpid(unsigned long pid,
unsigned long lpid,
unsigned long ric)
{
unsigned long rb, rs, prs, r;
rb = PPC_BIT(53); /* IS = 1 */
rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
prs = 1; /* process scoped */
r = 1; /* radix format */
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
trace_tlbie(0, 0, rb, rs, ric, prs, r);
}
static __always_inline void __tlbie_va_lpid(unsigned long va, unsigned long pid,
unsigned long lpid,
unsigned long ap, unsigned long ric)
{
unsigned long rb, rs, prs, r;
rb = va & ~(PPC_BITMASK(52, 63));
rb |= ap << PPC_BITLSHIFT(58);
rs = (pid << PPC_BITLSHIFT(31)) | (lpid & ~(PPC_BITMASK(0, 31)));
prs = 1; /* process scoped */
r = 1; /* radix format */
asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
trace_tlbie(0, 0, rb, rs, ric, prs, r);
}
static inline void fixup_tlbie_pid_lpid(unsigned long pid, unsigned long lpid)
{
/*
* We can use any address for the invalidation, pick one which is
* probably unused as an optimisation.
*/
unsigned long va = ((1UL << 52) - 1);
if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
asm volatile("ptesync" : : : "memory");
__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
}
if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
asm volatile("ptesync" : : : "memory");
__tlbie_va_lpid(va, pid, lpid, mmu_get_ap(MMU_PAGE_64K),
RIC_FLUSH_TLB);
}
}
static inline void _tlbie_pid_lpid(unsigned long pid, unsigned long lpid,
unsigned long ric)
{
asm volatile("ptesync" : : : "memory");
/*
* Workaround the fact that the "ric" argument to __tlbie_pid
* must be a compile-time contraint to match the "i" constraint
* in the asm statement.
*/
switch (ric) {
case RIC_FLUSH_TLB:
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_TLB);
fixup_tlbie_pid_lpid(pid, lpid);
break;
case RIC_FLUSH_PWC:
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
break;
case RIC_FLUSH_ALL:
default:
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_ALL);
fixup_tlbie_pid_lpid(pid, lpid);
}
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
}
static inline void fixup_tlbie_va_range_lpid(unsigned long va,
unsigned long pid,
unsigned long lpid,
unsigned long ap)
{
if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
asm volatile("ptesync" : : : "memory");
__tlbie_pid_lpid(0, lpid, RIC_FLUSH_TLB);
}
if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
asm volatile("ptesync" : : : "memory");
__tlbie_va_lpid(va, pid, lpid, ap, RIC_FLUSH_TLB);
}
}
static inline void __tlbie_va_range_lpid(unsigned long start, unsigned long end,
unsigned long pid, unsigned long lpid,
unsigned long page_size,
unsigned long psize)
{
unsigned long addr;
unsigned long ap = mmu_get_ap(psize);
for (addr = start; addr < end; addr += page_size)
__tlbie_va_lpid(addr, pid, lpid, ap, RIC_FLUSH_TLB);
fixup_tlbie_va_range_lpid(addr - page_size, pid, lpid, ap);
}
static inline void _tlbie_va_range_lpid(unsigned long start, unsigned long end,
unsigned long pid, unsigned long lpid,
unsigned long page_size,
unsigned long psize, bool also_pwc)
{
asm volatile("ptesync" : : : "memory");
if (also_pwc)
__tlbie_pid_lpid(pid, lpid, RIC_FLUSH_PWC);
__tlbie_va_range_lpid(start, end, pid, lpid, page_size, psize);
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
}
/*
* Performs process-scoped invalidations for a given LPID
* as part of H_RPT_INVALIDATE hcall.

1
arch/powerpc/mm/book3s64/slb.c
View File

@@ -13,6 +13,7 @@
#include <asm/mmu.h>
#include <asm/mmu_context.h>
#include <asm/paca.h>
#include <asm/lppaca.h>
#include <asm/ppc-opcode.h>
#include <asm/cputable.h>
#include <asm/cacheflush.h>

8
arch/powerpc/perf/core-fsl-emb.c
View File

@@ -645,7 +645,6 @@ static void perf_event_interrupt(struct pt_regs *regs)
struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
struct perf_event *event;
unsigned long val;
int found = 0;
for (i = 0; i < ppmu->n_counter; ++i) {
event = cpuhw->event[i];
@@ -654,7 +653,6 @@ static void perf_event_interrupt(struct pt_regs *regs)
if ((int)val < 0) {
if (event) {
/* event has overflowed */
found = 1;
record_and_restart(event, val, regs);
} else {
/*
@@ -672,11 +670,13 @@ static void perf_event_interrupt(struct pt_regs *regs)
isync();
}
void hw_perf_event_setup(int cpu)
static int fsl_emb_pmu_prepare_cpu(unsigned int cpu)
{
struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
memset(cpuhw, 0, sizeof(*cpuhw));
return 0;
}
int register_fsl_emb_pmu(struct fsl_emb_pmu *pmu)
@@ -689,6 +689,8 @@ int register_fsl_emb_pmu(struct fsl_emb_pmu *pmu)
pmu->name);
perf_pmu_register(&fsl_emb_pmu, "cpu", PERF_TYPE_RAW);
cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare",
fsl_emb_pmu_prepare_cpu, NULL);
return 0;
}

6
arch/powerpc/platforms/powermac/time.c
View File

@@ -26,8 +26,8 @@
#include <linux/rtc.h>
#include <linux/of_address.h>
#include <asm/early_ioremap.h>
#include <asm/sections.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/time.h>
#include <asm/nvram.h>
@@ -182,7 +182,7 @@ static int __init via_calibrate_decr(void)
return 0;
}
of_node_put(vias);
via = ioremap(rsrc.start, resource_size(&rsrc));
via = early_ioremap(rsrc.start, resource_size(&rsrc));
if (via == NULL) {
printk(KERN_ERR "Failed to map VIA for timer calibration !\n");
return 0;
@@ -207,7 +207,7 @@ static int __init via_calibrate_decr(void)
ppc_tb_freq = (dstart - dend) * 100 / 6;
iounmap(via);
early_iounmap((void *)via, resource_size(&rsrc));
return 1;
}

1
arch/powerpc/platforms/pseries/hvCall.S
View File

@@ -89,6 +89,7 @@ BEGIN_FTR_SECTION; \
b 1f; \
END_FTR_SECTION(0, 1); \
LOAD_REG_ADDR(r12, hcall_tracepoint_refcount) ; \
ld r12,0(r12); \
std r12,32(r1); \
cmpdi r12,0; \
bne- LABEL; \

10
arch/powerpc/platforms/pseries/lpar.c
View File

@@ -638,16 +638,8 @@ static const struct proc_ops vcpudispatch_stats_freq_proc_ops = {
static int __init vcpudispatch_stats_procfs_init(void)
{
/*
* Avoid smp_processor_id while preemptible. All CPUs should have
* the same value for lppaca_shared_proc.
*/
preempt_disable();
if (!lppaca_shared_proc(get_lppaca())) {
preempt_enable();
if (!lppaca_shared_proc())
return 0;
}
preempt_enable();
if (!proc_create("powerpc/vcpudispatch_stats", 0600, NULL,
&vcpudispatch_stats_proc_ops))

4
arch/powerpc/platforms/pseries/lparcfg.c
View File

@@ -205,7 +205,7 @@ static void parse_ppp_data(struct seq_file *m)
ppp_data.active_system_procs);
/* pool related entries are appropriate for shared configs */
if (lppaca_shared_proc(get_lppaca())) {
if (lppaca_shared_proc()) {
unsigned long pool_idle_time, pool_procs;
seq_printf(m, "pool=%d\n", ppp_data.pool_num);
@@ -616,7 +616,7 @@ static int pseries_lparcfg_data(struct seq_file *m, void *v)
partition_potential_processors);
seq_printf(m, "shared_processor_mode=%d\n",
lppaca_shared_proc(get_lppaca()));
lppaca_shared_proc());
#ifdef CONFIG_PPC_64S_HASH_MMU
if (!radix_enabled())

2
arch/powerpc/platforms/pseries/setup.c
View File

@@ -846,7 +846,7 @@ static void __init pSeries_setup_arch(void)
if (firmware_has_feature(FW_FEATURE_LPAR)) {
vpa_init(boot_cpuid);
if (lppaca_shared_proc(get_lppaca())) {
if (lppaca_shared_proc()) {
static_branch_enable(&shared_processor);
pv_spinlocks_init();
#ifdef CONFIG_PARAVIRT_TIME_ACCOUNTING

4
arch/powerpc/sysdev/mpc5xxx_clocks.c
View File

@@ -25,8 +25,10 @@ unsigned long mpc5xxx_fwnode_get_bus_frequency(struct fwnode_handle *fwnode)
fwnode_for_each_parent_node(fwnode, parent) {
ret = fwnode_property_read_u32(parent, "bus-frequency", &bus_freq);
if (!ret)
if (!ret) {
fwnode_handle_put(parent);
return bus_freq;
}
}
return 0;

1
arch/powerpc/xmon/xmon.c
View File

@@ -58,6 +58,7 @@
#ifdef CONFIG_PPC64
#include <asm/hvcall.h>
#include <asm/paca.h>
#include <asm/lppaca.h>
#endif
#include "nonstdio.h"

2
arch/s390/crypto/paes_s390.c
View File

@@ -35,7 +35,7 @@
* and padding is also possible, the limits need to be generous.
*/
#define PAES_MIN_KEYSIZE 16
#define PAES_MAX_KEYSIZE 320
#define PAES_MAX_KEYSIZE MAXEP11AESKEYBLOBSIZE
static u8 *ctrblk;
static DEFINE_MUTEX(ctrblk_lock);

2
arch/s390/include/uapi/asm/pkey.h
View File

@@ -26,7 +26,7 @@
#define MAXCLRKEYSIZE 32 /* a clear key value may be up to 32 bytes */
#define MAXAESCIPHERKEYSIZE 136 /* our aes cipher keys have always 136 bytes */
#define MINEP11AESKEYBLOBSIZE 256 /* min EP11 AES key blob size */
#define MAXEP11AESKEYBLOBSIZE 320 /* max EP11 AES key blob size */
#define MAXEP11AESKEYBLOBSIZE 336 /* max EP11 AES key blob size */
/* Minimum size of a key blob */
#define MINKEYBLOBSIZE SECKEYBLOBSIZE

2
arch/s390/kernel/ipl.c
View File

@@ -503,6 +503,8 @@ static struct attribute_group ipl_ccw_attr_group_lpar = {
static struct attribute *ipl_unknown_attrs[] = {
&sys_ipl_type_attr.attr,
&sys_ipl_secure_attr.attr,
&sys_ipl_has_secure_attr.attr,
NULL,
};

1
arch/um/configs/i386_defconfig
View File

@@ -35,6 +35,7 @@ CONFIG_TTY_CHAN=y
CONFIG_XTERM_CHAN=y
CONFIG_CON_CHAN="pts"
CONFIG_SSL_CHAN="pts"
CONFIG_SOUND=m
CONFIG_UML_SOUND=m
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y

1
arch/um/configs/x86_64_defconfig
View File

@@ -33,6 +33,7 @@ CONFIG_TTY_CHAN=y
CONFIG_XTERM_CHAN=y
CONFIG_CON_CHAN="pts"
CONFIG_SSL_CHAN="pts"
CONFIG_SOUND=m
CONFIG_UML_SOUND=m
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y

16
arch/um/drivers/Kconfig
View File

@@ -111,24 +111,14 @@ config SSL_CHAN
config UML_SOUND
tristate "Sound support"
depends on SOUND
select SOUND_OSS_CORE
help
This option enables UML sound support. If enabled, it will pull in
soundcore and the UML hostaudio relay, which acts as a intermediary
the UML hostaudio relay, which acts as a intermediary
between the host's dsp and mixer devices and the UML sound system.
It is safe to say 'Y' here.
config SOUND
tristate
default UML_SOUND
config SOUND_OSS_CORE
bool
default UML_SOUND
config HOSTAUDIO
tristate
default UML_SOUND
endmenu
menu "UML Network Devices"

2
arch/um/drivers/Makefile
View File

@@ -54,7 +54,7 @@ obj-$(CONFIG_UML_NET) += net.o
obj-$(CONFIG_MCONSOLE) += mconsole.o
obj-$(CONFIG_MMAPPER) += mmapper_kern.o
obj-$(CONFIG_BLK_DEV_UBD) += ubd.o
obj-$(CONFIG_HOSTAUDIO) += hostaudio.o
obj-$(CONFIG_UML_SOUND) += hostaudio.o
obj-$(CONFIG_NULL_CHAN) += null.o
obj-$(CONFIG_PORT_CHAN) += port.o
obj-$(CONFIG_PTY_CHAN) += pty.o

30
arch/x86/boot/compressed/head_64.S
View File

@@ -485,11 +485,25 @@ SYM_CODE_START(startup_64)
/* Save the trampoline address in RCX */
movq %rax, %rcx
/* Set up 32-bit addressable stack */
leaq TRAMPOLINE_32BIT_STACK_END(%rcx), %rsp
/*
* Load the address of trampoline_return() into RDI.
* It will be used by the trampoline to return to the main code.
* Preserve live 64-bit registers on the stack: this is necessary
* because the architecture does not guarantee that GPRs will retain
* their full 64-bit values across a 32-bit mode switch.
*/
pushq %rbp
pushq %rbx
pushq %rsi
/*
* Push the 64-bit address of trampoline_return() onto the new stack.
* It will be used by the trampoline to return to the main code. Due to
* the 32-bit mode switch, it cannot be kept it in a register either.
*/
leaq trampoline_return(%rip), %rdi
pushq %rdi
/* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */
pushq $__KERNEL32_CS
@@ -497,6 +511,11 @@ SYM_CODE_START(startup_64)
pushq %rax
lretq
trampoline_return:
/* Restore live 64-bit registers */
popq %rsi
popq %rbx
popq %rbp
/* Restore the stack, the 32-bit trampoline uses its own stack */
leaq rva(boot_stack_end)(%rbx), %rsp
@@ -606,7 +625,7 @@ SYM_FUNC_END(.Lrelocated)
/*
* This is the 32-bit trampoline that will be copied over to low memory.
*
* RDI contains the return address (might be above 4G).
* Return address is at the top of the stack (might be above 4G).
* ECX contains the base address of the trampoline memory.
* Non zero RDX means trampoline needs to enable 5-level paging.
*/
@@ -616,9 +635,6 @@ SYM_CODE_START(trampoline_32bit_src)
movl %eax, %ds
movl %eax, %ss
/* Set up new stack */
leal TRAMPOLINE_32BIT_STACK_END(%ecx), %esp
/* Disable paging */
movl %cr0, %eax
btrl $X86_CR0_PG_BIT, %eax
@@ -695,7 +711,7 @@ SYM_CODE_END(trampoline_32bit_src)
.code64
SYM_FUNC_START_LOCAL_NOALIGN(.Lpaging_enabled)
/* Return from the trampoline */
jmp *%rdi
retq
SYM_FUNC_END(.Lpaging_enabled)
/*

12
arch/x86/events/intel/uncore_snbep.c
View File

@@ -6078,8 +6078,18 @@ void spr_uncore_cpu_init(void)
type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA);
if (type) {
/*
* The value from the discovery table (stored in the type->num_boxes
* of UNCORE_SPR_CHA) is incorrect on some SPR variants because of a
* firmware bug. Using the value from SPR_MSR_UNC_CBO_CONFIG to replace it.
*/
rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo);
type->num_boxes = num_cbo;
/*
* The MSR doesn't work on the EMR XCC, but the firmware bug doesn't impact
* the EMR XCC. Don't let the value from the MSR replace the existing value.
*/
if (num_cbo)
type->num_boxes = num_cbo;
}
spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO);
}

6
arch/x86/include/asm/mem_encrypt.h
View File

@@ -50,8 +50,8 @@ void __init sme_enable(struct boot_params *bp);
int __init early_set_memory_decrypted(unsigned long vaddr, unsigned long size);
int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long size);
void __init early_set_mem_enc_dec_hypercall(unsigned long vaddr, int npages,
bool enc);
void __init early_set_mem_enc_dec_hypercall(unsigned long vaddr,
unsigned long size, bool enc);
void __init mem_encrypt_free_decrypted_mem(void);
@@ -84,7 +84,7 @@ early_set_memory_decrypted(unsigned long vaddr, unsigned long size) { return 0;
static inline int __init
early_set_memory_encrypted(unsigned long vaddr, unsigned long size) { return 0; }
static inline void __init
early_set_mem_enc_dec_hypercall(unsigned long vaddr, int npages, bool enc) {}
early_set_mem_enc_dec_hypercall(unsigned long vaddr, unsigned long size, bool enc) {}
static inline void mem_encrypt_free_decrypted_mem(void) { }

11
arch/x86/include/asm/pgtable_types.h
View File

@@ -125,11 +125,12 @@
* instance, and is *not* included in this mask since
* pte_modify() does modify it.
*/
#define _PAGE_CHG_MASK (PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT | \
_PAGE_SPECIAL | _PAGE_ACCESSED | _PAGE_DIRTY | \
_PAGE_SOFT_DIRTY | _PAGE_DEVMAP | _PAGE_ENC | \
_PAGE_UFFD_WP)
#define _HPAGE_CHG_MASK (_PAGE_CHG_MASK | _PAGE_PSE)
#define _COMMON_PAGE_CHG_MASK (PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT | \
_PAGE_SPECIAL | _PAGE_ACCESSED | _PAGE_DIRTY |\
_PAGE_SOFT_DIRTY | _PAGE_DEVMAP | _PAGE_ENC | \
_PAGE_UFFD_WP)
#define _PAGE_CHG_MASK (_COMMON_PAGE_CHG_MASK | _PAGE_PAT)
#define _HPAGE_CHG_MASK (_COMMON_PAGE_CHG_MASK | _PAGE_PSE | _PAGE_PAT_LARGE)
/*
* The cache modes defined here are used to translate between pure SW usage

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