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clk: rockchip: rk3588: Add pll rate table for 955Mhz and 785Mhz

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Signed-off-by: Weng Tao <tao.weng@rock-chips.com>
Change-Id: I669f79667fce318cc0ae919a52babd3cdbb52610
This commit is contained in:
Weng Tao
2022-03-16 15:57:04 +08:00
committed by Tao Huang
parent 84c39b1c84
commit e0f5e518d4
1 changed files with 2 additions and 0 deletions
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2
drivers/clk/rockchip/clk-rk3588.c
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@@ -78,11 +78,13 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
RK3588_PLL_RATE(955520000, 3, 477, 2, 49806),
RK3588_PLL_RATE(903168000, 6, 903, 2, 11009),
RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
RK3588_PLL_RATE(785560000, 3, 392, 2, 51117),
RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
RK3588_PLL_RATE(594000000, 2, 198, 2, 0),