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osd: adjust threshold by using active_begin_line [2/2]

Browse Source 
PD#SWPL-11936

Problem:
set screen position frequently
frame flashes white stripes

Solution:
modify threshold for updating all registers
on vsync coming

Verify:
Verfied on u212

Change-Id: Iac1ec8b5ec36809d5f5ffe2fe8e79c182e9c126b
Signed-off-by: Cao Jian <jian.cao@amlogic.com>
This commit is contained in:
Cao Jian
2019-09-10 12:39:41 +08:00
committed by Luke Go
parent ef0a8629e3
commit e155a3e2ef
1 changed files with 36 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
drivers/amlogic/media/osd/osd_hw.c
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@@ -893,10 +893,40 @@ static void f2v_get_vertical_phase(
static bool osd_hdr_on;
#endif
static int get_active_begin_line(u32 viu_type)
{
int active_line_begin = 0;
u32 viu = VIU1;
if (viu_type == VIU1)
viu = osd_reg_read(VPU_VIU_VENC_MUX_CTRL) & 0x3;
else if (viu_type == VIU2)
viu = (osd_reg_read(VPU_VIU_VENC_MUX_CTRL) >> 2) & 0x3;
switch (viu) {
case 0:
active_line_begin =
osd_reg_read(ENCL_VIDEO_VAVON_BLINE);
break;
case 1:
active_line_begin =
osd_reg_read(ENCI_VFIFO2VD_LINE_TOP_START);
break;
case 2:
active_line_begin =
osd_reg_read(ENCP_VIDEO_VAVON_BLINE);
break;
case 3:
active_line_begin =
osd_reg_read(ENCT_VIDEO_VAVON_BLINE);
break;
}
return active_line_begin;
}
static int get_encp_line(u32 viu_type)
{
int enc_line = 0;
int active_line_begin = 0;
unsigned int reg = 0;
u32 viu = VIU1;
@@ -907,27 +937,19 @@ static int get_encp_line(u32 viu_type)
switch (viu) {
case 0:
reg = osd_reg_read(ENCL_INFO_READ);
active_line_begin =
osd_reg_read(ENCL_VIDEO_VAVON_BLINE);
break;
case 1:
reg = osd_reg_read(ENCI_INFO_READ);
active_line_begin =
osd_reg_read(ENCI_VFIFO2VD_LINE_TOP_START);
break;
case 2:
reg = osd_reg_read(ENCP_INFO_READ);
active_line_begin =
osd_reg_read(ENCP_VIDEO_VAVON_BLINE);
break;
case 3:
reg = osd_reg_read(ENCT_INFO_READ);
active_line_begin =
osd_reg_read(ENCT_VIDEO_VAVON_BLINE);
break;
}
enc_line = (reg >> 16) & 0x1fff;
enc_line -= active_line_begin;
return enc_line;
}
@@ -8504,7 +8526,7 @@ static int osd_setting_order(u32 output_index)
bool update = false;
int line1;
int line2;
int vinfo_height;
int active_begin_line;
u32 val;
blending = &osd_blending;
@@ -8544,12 +8566,10 @@ static int osd_setting_order(u32 output_index)
set_blend_path_new(blending);
else
set_blend_path(blending);
active_begin_line = get_active_begin_line(VIU1);
line1 = get_enter_encp_line(VIU1);
vinfo_height = osd_hw.field_out_en[output_index] ?
(osd_hw.vinfo_height[output_index] * 2) :
osd_hw.vinfo_height[output_index];
/* if nearly vsync signal, wait vsync here */
if (line1 >= vinfo_height * line_threshold / 100) {
if (line1 <= active_begin_line * line_threshold / 100) {
osd_log_dbg(MODULE_RENDER,
"enter osd_setting_order:encp line=%d\n",
line1);
@@ -8604,6 +8624,7 @@ static int osd_setting_order(u32 output_index)
[OSD_FREESCALE_COEF].update_func(i);
osd_hw.reg[DISP_FREESCALE_ENABLE]
.update_func(i);
osd_update_window_axis = false;
}
if (osd_hw.premult_en[i] && !osd_hw.blend_bypass)
VSYNCOSD_WR_MPEG_REG_BITS(