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drm/rockchip: vop2: filter display mode by vop aclk

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When the pixelclk is more than 600MHz but aclk is equal or
less than 500MHz, it will cause error. So filter the display
mode whose pixelclk is more than 600Mhz when the aclk is
equal or less than 500MHz.

Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I04216b661ddfdf8aa5d6de9b14e430ecbf8c4d22
This commit is contained in:
Zhang Yubing
2022-06-27 15:50:59 +08:00
committed by Tao Huang
parent 9302a4f61b
commit e16a4b0a15
1 changed files with 8 additions and 0 deletions
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8
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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@@ -152,6 +152,8 @@
#define VOP2_MAX_VP_OUTPUT_WIDTH 4096
/* KHZ */
#define VOP2_MAX_DCLK_RATE 600000
/* KHZ */
#define VOP2_COMMON_ACLK_RATE 500000
enum vop2_data_format {
VOP2_FMT_ARGB8888 = 0,
@@ -5419,6 +5421,7 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
int request_clock = mode->clock;
int clock;
unsigned long aclk_rate;
/*
* For RK3588, VP0 and VP1 will be both used in splice mode. All display
@@ -5434,6 +5437,11 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
request_clock *= 2;
aclk_rate = clk_get_rate(vop2->aclk) / 1000;
if (request_clock > VOP2_MAX_DCLK_RATE && aclk_rate <= VOP2_COMMON_ACLK_RATE)
return MODE_BAD;
if ((request_clock <= VOP2_MAX_DCLK_RATE) &&
(vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll") ||
vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll"))) {