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PCI: rockchip: dw: Support PM L1 clock removing

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The application logic is ready to have reference clock removed through
either L1 PM Sub-states or L1 CPM.

Change-Id: I1622416fcff716b2b342746fb3f93f61d4092101
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This commit is contained in:
Jon Lin
2022-04-29 18:20:33 +08:00
committed by Tao Huang
parent 0a082fd9da
commit e18dfa93d0
1 changed files with 11 additions and 1 deletions
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12
drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@@ -124,7 +124,7 @@ enum rk_pcie_device_mode {
#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
#define PCIE_CLIENT_DBF_EN 0xffff0003
#define PCIE_CLIENT_DBF_EN 0xffff0007
#define PCIE_PHY_LINKUP BIT(0)
#define PCIE_DATA_LINKUP BIT(1)
@@ -174,6 +174,7 @@ struct rk_pcie {
bool is_rk1808;
bool is_signal_test;
bool bifurcation;
bool supports_clkreq;
struct regulator *vpcie3v3;
struct irq_domain *irq_domain;
int legacy_parent_irq;
@@ -628,6 +629,13 @@ static inline void rk_pcie_set_mode(struct rk_pcie *rk_pcie)
rk_pcie_writel_apb(rk_pcie, 0x0, 0xf00000);
break;
case RK_PCIE_RC_TYPE:
if (rk_pcie->supports_clkreq) {
/* Application is ready to have reference clock removed */
rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_POWER, 0x00010001);
} else {
/* Pull down CLKREQ# to assert the connecting CLOCK_GEN OE */
rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_POWER, 0x30011000);
}
rk_pcie_writel_apb(rk_pcie, 0x0, 0xf00040);
/*
* Disable order rule for CPL can't pass halted P queue.
@@ -1797,6 +1805,8 @@ static int rk_pcie_really_probe(void *p)
}
}
rk_pcie->supports_clkreq = device_property_read_bool(dev, "supports-clkreq");
retry_regulator:
/* DON'T MOVE ME: must be enable before phy init */
rk_pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");