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di: speed up input mif read efficiency

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PD#159864: di: speed up input mif read efficiency

1) change input mif read pass ratio from 50% to 66.6% according
   to vlsi's suggestment
2) pass ratio = (pass_cnt + 1)/(pass_cnt + 1 + hold_cnt + 1)

Change-Id: Ib5bc274f40e3e085c22f807effbac436a02b0d76
Signed-off-by: kele bai <kele.bai@amlogic.com>
This commit is contained in:
kele bai
2018-01-31 10:10:38 +08:00
committed by Jianxin Pan
parent 35464c4784
commit e1d6405555
1 changed files with 22 additions and 2 deletions
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24
drivers/amlogic/media/deinterlace/deinterlace_hw.c
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@@ -387,6 +387,27 @@ void calc_lmv_base_mcinfo(unsigned int vf_height, unsigned long mcinfo_adr)
Wr(MCDI_LMVLCKEDEXT_1, lmv_lckedext[2]);
}
/*
* config pre hold ratio & mif request block len
* pass_ratio = (pass_cnt + 1)/(pass_cnt + 1 + hold_cnt + 1)
*/
static void pre_hold_block_mode_config(void)
{
if (is_meson_txlx_cpu()) {
/* setup pre process ratio to 66.6%*/
DI_Wr(DI_PRE_HOLD, (1 << 31) | (1 << 16) | 3);
/* block len, after block insert null req to balance reqs */
DI_Wr_reg_bits(DI_INP_GEN_REG3, 0, 4, 3);
DI_Wr_reg_bits(DI_MEM_GEN_REG3, 0, 4, 3);
DI_Wr_reg_bits(DI_CHAN2_GEN_REG3, 0, 4, 3);
DI_Wr_reg_bits(DI_IF1_GEN_REG3, 0, 4, 3);
DI_Wr_reg_bits(DI_IF2_GEN_REG3, 0, 4, 3);
DI_Wr_reg_bits(VD1_IF0_GEN_REG3, 0, 4, 3);
} else {
DI_Wr(DI_PRE_HOLD, (1 << 31) | (31 << 16) | 31);
}
}
void di_hw_init(bool pd_enable, bool mc_enable)
{
unsigned short fifo_size_vpp = 0xc0;
@@ -428,8 +449,7 @@ void di_hw_init(bool pd_enable, bool mc_enable)
di_pre_gate_control(true, true);
di_post_gate_control(true);
}
DI_Wr(DI_PRE_HOLD, (1 << 31) | (31 << 16) | 31);
pre_hold_block_mode_config();
ma_di_init();
ei_hw_init();
nr_hw_init();