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arm64: dts: rockchip: rk3588s: add pcie2 controller

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RK3588s supports 2 pcie2 controllers which use the phy combo to sata and
usb3.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: Id97957ef5341e9ab61af861b2b6194c056ad5835
This commit is contained in:
Kever Yang
2021-09-08 22:22:20 +08:00
committed by Tao Huang
parent 311ddf7bab
commit e1fdb69cd8
1 changed files with 102 additions and 0 deletions
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102
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -1098,6 +1098,108 @@
status = "disabled";
};
pcie2x1l1: pcie@fe180000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x30 0x3f>;
clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
<&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
<&cru CLK_PCIE_AUX3>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
device_type = "pci";
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
<0 0 0 2 &pcie2x1l1_intc 1>,
<0 0 0 3 &pcie2x1l1_intc 2>,
<0 0 0 4 &pcie2x1l1_intc 3>;
linux,pci-domain = <3>;
num-ib-windows = <8>;
num-ob-windows = <8>;
max-link-speed = <2>;
msi-map = <0x3000 &its 0x3000 0x1000>;
num-lanes = <1>;
phys = <&combphy2_psu PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3588_PD_PHP>;
ranges = <0x00000800 0x0 0xc0000000 0x9 0xc0000000 0x0 0x100000
0x81000000 0x0 0xc0100000 0x9 0xc0100000 0x0 0x100000
0x83000000 0x0 0xc0200000 0x9 0xc0200000 0x0 0x3fe00000>;
reg = <0xa 0x40c00000 0x0 0x400000>,
<0x0 0xfe180000 0x0 0x10000>;
reg-names = "pcie-dbi", "pcie-apb";
resets = <&cru SRST_PCIE3_POWER_UP>;
reset-names = "pipe";
status = "disabled";
pcie2x1l1_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>;
};
};
pcie2x1l2: pcie@fe190000 {
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x40 0x4f>;
clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
<&cru CLK_PCIE_AUX4>;
clock-names = "aclk_mst", "aclk_slv",
"aclk_dbi", "pclk", "aux";
device_type = "pci";
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
<0 0 0 2 &pcie2x1l2_intc 1>,
<0 0 0 3 &pcie2x1l2_intc 2>,
<0 0 0 4 &pcie2x1l2_intc 3>;
linux,pci-domain = <4>;
num-ib-windows = <8>;
num-ob-windows = <8>;
max-link-speed = <2>;
msi-map = <0x4000 &its 0x4000 0x1000>;
num-lanes = <1>;
phys = <&combphy0_ps PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3588_PD_PHP>;
ranges = <0x00000800 0x0 0xe0000000 0xa 0x00000000 0x0 0x100000
0x81000000 0x0 0xe0100000 0xa 0x00100000 0x0 0x100000
0x83000000 0x0 0xe0200000 0xa 0x00200000 0x0 0x3fe00000>;
reg = <0xa 0x41000000 0x0 0x400000>,
<0x0 0xfe190000 0x0 0x10000>;
reg-names = "pcie-dbi", "pcie-apb";
resets = <&cru SRST_PCIE4_POWER_UP>;
reset-names = "pipe";
status = "disabled";
pcie2x1l2_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>;
};
};
gmac1: ethernet@fe1c0000 {
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe1c0000 0x0 0x10000>;