codec: *** miss codec files again ***

2026-06-09 04:10:18 +09:00 · 2013-08-02 14:55:21 +08:00
parent bb2b61e6a5
commit e24cfebf1d
3 changed files with 3011 additions and 0 deletions
--- a/sound/soc/codecs/rk3026_codec.c
+++ b/sound/soc/codecs/rk3026_codec.c
--- a/sound/soc/codecs/rk3026_codec.h
+++ b/sound/soc/codecs/rk3026_codec.h
@@ -0,0 +1,547 @@
+/*
+ * rk3026.h  --  RK3026 CODEC ALSA SoC audio driver
+ *
+ * Copyright 2013 Rockship
+ * Author: chenjq <chenjq@rock-chips.com>
+ *
+ */
+
+#ifndef __RK3026_CODEC_H__
+#define __RK3026_CODEC_H__
+
+
+
+/* codec register */
+#define RK3026_CODEC_BASE			(0x0)
+
+#define RK3026_RESET				(RK3026_CODEC_BASE + 0x00)
+#define RK3026_ADC_INT_CTL1			(RK3026_CODEC_BASE + 0x08)
+#define RK3026_ADC_INT_CTL2			(RK3026_CODEC_BASE + 0x0c)
+#define RK3026_DAC_INT_CTL1			(RK3026_CODEC_BASE + 0x10)
+#define RK3026_DAC_INT_CTL2			(RK3026_CODEC_BASE + 0x14)
+#define RK3026_ADC_MIC_CTL			(RK3026_CODEC_BASE + 0x88)
+#define RK3026_BST_CTL				(RK3026_CODEC_BASE + 0x8c)
+#define RK3026_ALC_MUNIN_CTL			(RK3026_CODEC_BASE + 0x90)
+#define RK3026_BSTL_ALCL_CTL			(RK3026_CODEC_BASE + 0x94)
+#define RK3026_ALCR_GAIN_CTL			(RK3026_CODEC_BASE + 0x98)
+#define RK3026_ADC_ENABLE			(RK3026_CODEC_BASE + 0x9c)
+#define RK3026_DAC_CTL				(RK3026_CODEC_BASE + 0xa0)
+#define RK3026_DAC_ENABLE			(RK3026_CODEC_BASE + 0xa4)
+#define RK3026_HPMIX_CTL			(RK3026_CODEC_BASE + 0xa8)
+#define RK3026_HPMIX_S_SELECT			(RK3026_CODEC_BASE + 0xac)
+#define RK3026_HPOUT_CTL			(RK3026_CODEC_BASE + 0xB0)
+#define RK3026_HPOUTL_GAIN			(RK3026_CODEC_BASE + 0xB4)
+#define RK3026_HPOUTR_GAIN			(RK3026_CODEC_BASE + 0xB8)
+#define RK3026_SELECT_CURRENT			(RK3026_CODEC_BASE + 0xBC)
+#define RK3026_PGAL_AGC_CTL1			(RK3026_CODEC_BASE + 0xc0)
+#define RK3026_PGAL_AGC_CTL2			(RK3026_CODEC_BASE + 0xc4)
+#define RK3026_PGAL_AGC_CTL3			(RK3026_CODEC_BASE + 0xc8)
+#define RK3026_PGAL_AGC_CTL4			(RK3026_CODEC_BASE + 0xcc)
+#define RK3026_PGAL_ASR_CTL			(RK3026_CODEC_BASE + 0xd0)
+#define RK3026_PGAL_AGC_MAX_H			(RK3026_CODEC_BASE + 0xd4)
+#define RK3026_PGAL_AGC_MAX_L			(RK3026_CODEC_BASE + 0xd8)
+#define RK3026_PGAL_AGC_MIN_H			(RK3026_CODEC_BASE + 0xdc)
+#define RK3026_PGAL_AGC_MIN_L			(RK3026_CODEC_BASE + 0xe0)
+#define RK3026_PGAL_AGC_CTL5			(RK3026_CODEC_BASE + 0xe4)
+#define RK3026_PGAR_AGC_CTL1			(RK3026_CODEC_BASE + 0x100)
+#define RK3026_PGAR_AGC_CTL2			(RK3026_CODEC_BASE + 0x104)
+#define RK3026_PGAR_AGC_CTL3			(RK3026_CODEC_BASE + 0x108)
+#define RK3026_PGAR_AGC_CTL4			(RK3026_CODEC_BASE + 0x10c)
+#define RK3026_PGAR_ASR_CTL			(RK3026_CODEC_BASE + 0x110)
+#define RK3026_PGAR_AGC_MAX_H			(RK3026_CODEC_BASE + 0x114)
+#define RK3026_PGAR_AGC_MAX_L			(RK3026_CODEC_BASE + 0x118)
+#define RK3026_PGAR_AGC_MIN_H			(RK3026_CODEC_BASE + 0x11c)
+#define RK3026_PGAR_AGC_MIN_L			(RK3026_CODEC_BASE + 0x120)
+#define RK3026_PGAR_AGC_CTL5			(RK3026_CODEC_BASE + 0x124)
+
+/* ADC Interface Control 1 (0x08) */
+#define RK3026_ALRCK_POL_MASK			(0x1 << 7)
+#define RK3026_ALRCK_POL_SFT			7
+#define RK3026_ALRCK_POL_EN			(0x1 << 7)
+#define RK3026_ALRCK_POL_DIS			(0x0 << 7)
+
+#define RK3026_ADC_VWL_MASK			(0x3 << 5)
+#define RK3026_ADC_VWL_SFT			5
+#define RK3026_ADC_VWL_32			(0x3 << 5)
+#define RK3026_ADC_VWL_24			(0x2 << 5)
+#define RK3026_ADC_VWL_20			(0x1 << 5)
+#define RK3026_ADC_VWL_16			(0x0 << 5)
+
+#define RK3026_ADC_DF_MASK			(0x3 << 3)
+#define RK3026_ADC_DF_SFT			3
+#define RK3026_ADC_DF_PCM			(0x3 << 3)
+#define RK3026_ADC_DF_I2S			(0x2 << 3)
+#define RK3026_ADC_DF_LJ				(0x1 << 3)
+#define RK3026_ADC_DF_RJ				(0x0 << 3)
+
+#define RK3026_ADC_SWAP_MASK			(0x1 << 1)
+#define RK3026_ADC_SWAP_SFT			1
+#define RK3026_ADC_SWAP_EN			(0x1 << 1)
+#define RK3026_ADC_SWAP_DIS			(0x0 << 1)
+
+#define RK3026_ADC_TYPE_MASK			0x1
+#define RK3026_ADC_TYPE_SFT			0
+#define RK3026_ADC_TYPE_MONO			0x1
+#define RK3026_ADC_TYPE_STEREO			0x0
+
+/* ADC Interface Control 2 (0x0c) */
+#define RK3026_I2S_MODE_MASK			(0x1 << 4)
+#define RK3026_I2S_MODE_SFT			(4)
+#define RK3026_I2S_MODE_MST			(0x1 << 4)
+#define RK3026_I2S_MODE_SLV			(0x0 << 4)
+
+#define RK3026_ADC_WL_MASK			(0x3 << 2)
+#define RK3026_ADC_WL_SFT			(2)
+#define RK3026_ADC_WL_32				(0x3 << 2)
+#define RK3026_ADC_WL_24				(0x2 << 2)
+#define RK3026_ADC_WL_20				(0x1 << 2)
+#define RK3026_ADC_WL_16				(0x0 << 2)
+
+#define RK3026_ADC_RST_MASK			(0x1 << 1)
+#define RK3026_ADC_RST_SFT			91)
+#define RK3026_ADC_RST_DIS			(0x1 << 1)
+#define RK3026_ADC_RST_EN			(0x0 << 1)
+
+#define RK3026_ABCLK_POL_MASK			0x1
+#define RK3026_ABCLK_POL_SFT			0
+#define RK3026_ABCLK_POL_EN			0x1
+#define RK3026_ABCLK_POL_DIS			0x0
+
+/* DAC Interface Control 1 (0x10) */
+#define RK3026_DLRCK_POL_MASK			(0x1 << 7)
+#define RK3026_DLRCK_POL_SFT			7
+#define RK3026_DLRCK_POL_EN			(0x1 << 7)
+#define RK3026_DLRCK_POL_DIS			(0x0 << 7)
+
+#define RK3026_DAC_VWL_MASK			(0x3 << 5)
+#define RK3026_DAC_VWL_SFT			5
+#define RK3026_DAC_VWL_32			(0x3 << 5)
+#define RK3026_DAC_VWL_24			(0x2 << 5)
+#define RK3026_DAC_VWL_20			(0x1 << 5)
+#define RK3026_DAC_VWL_16			(0x0 << 5)
+
+#define RK3026_DAC_DF_MASK			(0x3 << 3)
+#define RK3026_DAC_DF_SFT			3
+#define RK3026_DAC_DF_PCM			(0x3 << 3)
+#define RK3026_DAC_DF_I2S			(0x2 << 3)
+#define RK3026_DAC_DF_LJ				(0x1 << 3)
+#define RK3026_DAC_DF_RJ				(0x0 << 3)
+
+#define RK3026_DAC_SWAP_MASK			(0x1 << 2)
+#define RK3026_DAC_SWAP_SFT			2
+#define RK3026_DAC_SWAP_EN			(0x1 << 2)
+#define RK3026_DAC_SWAP_DIS			(0x0 << 2)
+
+/* DAC Interface Control 2 (0x14) */
+#define RK3026_DAC_WL_MASK			(0x3 << 2)
+#define RK3026_DAC_WL_SFT			2
+#define RK3026_DAC_WL_32				(0x3 << 2)
+#define RK3026_DAC_WL_24				(0x2 << 2)
+#define RK3026_DAC_WL_20				(0x1 << 2)
+#define RK3026_DAC_WL_16				(0x0 << 2)
+
+#define RK3026_DAC_RST_MASK			(0x1 << 1)
+#define RK3026_DAC_RST_SFT			1
+#define RK3026_DAC_RST_DIS			(0x1 << 1)
+#define RK3026_DAC_RST_EN			(0x0 << 1)
+
+#define RK3026_DBCLK_POL_MASK			0x1
+#define RK3026_DBCLK_POL_SFT			0
+#define RK3026_DBCLK_POL_EN			0x1
+#define RK3026_DBCLK_POL_DIS			0x0
+
+/* ADC & MICBIAS (0x88) */
+#define  RK3026_ADC_CURRENT_ENABLE              (0x1 << 7)
+#define  RK3026_ADC_CURRENT_DISABLE             (0x0 << 7)
+
+#define  RK3026_MICBIAS_VOL_ENABLE              (0x1 << 6)
+#define  RK3026_MICBIAS_VOL_DISABLE             (0x0 << 6)
+
+#define  RK3026_ADCL_ZERO_DET_EN                (0x1 << 5)
+#define  RK3026_ADCL_ZERO_DET_DIS               (0x0 << 5)
+
+#define  RK3026_ADCR_ZERO_DET_EN                (0x1 << 4)
+#define  RK3026_ADCR_ZERO_DET_DIS               (0x0 << 4)
+
+#define  RK3026_MICBIAS_VOL_SHT                  0
+#define  RK3026_MICBIAS_VOL_MSK                  7
+#define  RK3026_MICBIAS_VOL_MIN                  (0x0 << 0)  
+#define  RK3026_MICBIAS_VOL_MAX                  (0x7 << 0)
+
+/* BST_L  BST_R  CONTROL (0x8C)  */
+#define  RK3026_BSTL_PWRD_SFT		    (6)
+#define  RK3026_BSTL_EN                     (0x1 << 6)
+#define  RK3026_BSTL_DIS                    (0x0 << 6)  
+#define  RK3026_BSTL_GAIN_SHT               (5)
+#define  RK3026_BSTL_GAIN_20                (0x1 << 5)
+#define  RK3026_BSTL_GAIN_0                 (0x0 << 5)
+#define  RK3026_BSTL_MUTE_SHT	             (4)
+
+#define  RK3026_BSTR_PWRD_SFT		    (2)
+#define  RK3026_BSTR_EN                     (0x1 << 2)
+#define  RK3026_BSTR_DIS                    (0x0 << 2)
+#define  RK3026_BSTR_GAIN_SHT               (1)
+#define  RK3026_BSTR_GAIN_20                (0x1 << 1)
+#define  RK3026_BSTR_GAIN_0                 (0x0 << 1)
+#define  RK3026_BSTR_MUTE_SHT	               (0)
+
+
+/* MUXINL ALCL MUXINR ALCR  (0x90)  */
+#define  RK3026_MUXINL_F_SHT		   (6)
+#define  RK3026_MUXINL_F_INL                (0x02 << 6)
+#define  RK3026_MUXINL_F_BSTL               (0x01 << 6)
+#define  RK3026_ALCL_PWR_SHT                     (5)
+#define  RK3026_ALCL_EN                     (0x1 << 5)
+#define  RK3026_ALCL_DIS                    (0x0 << 5)
+#define  RK3026_ALCL_MUTE_SHT                (4)
+#define  RK3026_MUXINR_F_SHT		   (2)
+#define  RK3026_MUXINR_F_INR                (0x02 << 2)
+#define  RK3026_MUXINR_F_BSTR               (0x01 << 2)
+#define  RK3026_ALCR_PWR_SHT                     (1)
+#define  RK3026_ALCR_EN                     (0x1 << 1)
+#define  RK3026_ALCR_DIS                    (0x0 << 1)
+#define  RK3026_ALCR_MUTE_SHT                (0)
+
+/* BST_L MODE & ALC_L GAIN (0x94) */
+#define  RK3026_BSTL_MODE_SFT          (5)
+#define  RK3026_BSTL_MODE_SINGLE        (0x1 << 5)
+#define  RK3026_BSTL_MODE_DIFF          (0x0 << 5)
+
+#define  RK3026_ALCL_GAIN_SHT               (0)
+#define  RK3026_ALCL_GAIN_MSK               (0x1f)
+
+/* ALC_R GAIN (0x98) */
+#define  RK3026_ALCR_GAIN_SHT               (0)
+#define  RK3026_ALCR_GAIN_MSK               (0x1f)
+
+/* ADC control (0x9C) */
+#define RK3026_ADCL_REF_VOL_EN			(0x1 << 7)
+#define RK3026_ADCL_REF_VOL_DIS			(0x0 << 7)
+
+#define RK3026_ADCL_CLK_EN		       (0x1 << 6)
+#define RK3026_ADCL_CLK_DIS		       (0x0 << 6)
+
+#define RK3026_ADCL_AMP_EN			(0x1 << 5)
+#define RK3026_ADCL_AMP_DIS			(0x0 << 5)
+
+#define  RK3026_ADCL_RST_EN                     (0x1 << 4)
+#define  RK3026_ADCL_RST_DIS                     (0x0 << 4)
+
+#define RK3026_ADCR_REF_VOL_EN			(0x1 << 3)
+#define RK3026_ADCR_REF_VOL_DIS			(0x0 << 3)
+
+#define RK3026_ADCR_CLK_EN		       (0x1 << 2)
+#define RK3026_ADCR_CLK_DIS		       (0x0 << 2)
+
+#define RK3026_ADCR_AMP_EN			(0x1 << 1)
+#define RK3026_ADCR_AMP_DIS			(0x0 << 1)
+
+#define  RK3026_ADCR_RST_EN                     (0x1 << 0)
+#define  RK3026_ADCR_RST_DIS                     (0x0 << 0)
+
+/* DAC & VOUT Control (0xa0)  */
+#define  RK3026_CURRENT_EN                  (0x1 << 6)
+#define  RK3026_CURRENT_DIS                  (0x0 << 6)
+#define  RK3026_REF_VOL_DACL_EN                  (0x1 << 5)
+#define  RK3026_REF_VOL_DACL_DIS                 (0x0 << 5)
+#define  RK3026_ZO_DET_VOUTL_EN                 (0x1 << 4)
+#define  RK3026_ZO_DET_VOUTL_DIS                  (0x0 << 4)
+#define  RK3026_DET_ERAPHONE_DIS                  (0x0 << 3)
+#define  RK3026_DET_ERAPHONE_EN                  (0x1 << 3)
+#define  RK3026_REF_VOL_DACR_EN                  (0x1 << 1)
+#define  RK3026_REF_VOL_DACR_DIS                 (0x0 << 1)
+#define  RK3026_ZO_DET_VOUTR_EN                 (0x1 << 0)
+#define  RK3026_ZO_DET_VOUTR_DIS                  (0x0 << 0)
+
+/* DAC control (0xa4) */
+#define RK3026_DACL_REF_VOL_EN			(0x1 << 7)
+#define RK3026_DACL_REF_VOL_DIS			(0x0 << 7)
+
+#define RK3026_DACL_CLK_EN		       (0x1 << 6)
+#define RK3026_DACL_CLK_DIS		       (0x0 << 6)
+
+#define RK3026_DACL_EN			(0x1 << 5)
+#define RK3026_DACL_DIS			(0x0 << 5)
+
+#define  RK3026_DACL_INIT                     (0x0 << 4)
+#define  RK3026_DACL_WORK                    (0x1 << 4)
+
+#define RK3026_DACR_REF_VOL_EN			(0x1 << 3)
+#define RK3026_DACR_REF_VOL_DIS			(0x0 << 3)
+
+#define RK3026_DACR_CLK_EN		       (0x1 << 2)
+#define RK3026_DACR_CLK_DIS		       (0x0 << 2)
+
+#define RK3026_DACR_EN			(0x1 << 1)
+#define RK3026_DACR_DIS			(0x0 << 1)
+
+#define  RK3026_DACR_INIT                        (0x0 << 0)
+#define  RK3026_DACR_WORK                    (0x1 << 0)
+
+/* HPMIXL  HPMIXR Control (0xa8)  */
+#define RK3026_HPMIXL_SFT                         (6)
+#define RK3026_HPMIXL_EN                         (0x1 << 6)
+#define RK3026_HPMIXL_DIS                      (0x0 << 6)
+#define RK3026_HPMIXL_INIT1              (0x0 << 5)
+#define RK3026_HPMIXL_WORK1               (0x1 << 5)
+#define RK3026_HPMIXL_INIT2              (0x0 << 4)
+#define RK3026_HPMIXL_WORK2                (0x1 << 4)
+#define RK3026_HPMIXR_SFT                         (6)
+#define RK3026_HPMIXR_EN                         (0x1 << 2)
+#define RK3026_HPMIXR_DIS                      (0x0 << 2)
+#define RK3026_HPMIXR_INIT1               (0x0 << 1)
+#define RK3026_HPMIXR_WORK1               (0x1 << 1)
+#define RK3026_HPMIXR_INIT2              (0x0 << 0)
+#define RK3026_HPMIXR_WORK2                (0x1 << 0)
+
+/* HPMIXL Control  (0xac) */
+#define RK3026_HPMIXL_BYPASS_SFT             (0x1 << 7)
+#define RK3026_HPMIXL_SEL_ALCL_SFT              (0x1 << 6)
+#define RK3026_HPMIXL_SEL_ALCR_SFT              (0x1 << 5)
+#define RK3026_HPMIXL_SEL_DACL_SFT             (0x1 << 4)
+#define RK3026_HPMIXR_BYPASS_SFT             (0x1 << 3)
+#define RK3026_HPMIXR_SEL_ALCL_SFT              (0x1 << 2)
+#define RK3026_HPMIXR_SEL_ALCR_SFT              (0x1 << 1)
+#define RK3026_HPMIXR_SEL_DACR_SFT             (0x1 << 0)
+
+/* HPOUT Control  (0xb0) */
+#define RK3026_HPOUTL_PWR_SHT			(7)
+#define RK3026_HPOUTL_MSK                      (0x1 << 7)
+#define RK3026_HPOUTL_EN                       (0x1 << 7)
+#define RK3026_HPOUTL_DIS			(0x0 << 7)
+#define RK3026_HPOUTL_INIT_MSK			(0x1 << 6)
+#define RK3026_HPOUTL_INIT			(0x0 << 6)
+#define RK3026_HPOUTL_WORK			(0x1 << 6)
+#define RK3026_HPOUTL_MUTE_SHT			(5)
+#define RK3026_HPOUTL_MUTE_MSK			(0x1 << 5)
+#define RK3026_HPOUTL_MUTE_EN			(0x0 << 5)
+#define RK3026_HPOUTL_MUTE_DIS			(0x1 << 5)
+#define RK3026_HPOUTR_PWR_SHT			(4)
+#define RK3026_HPOUTR_MSK                      (0x1 << 4)
+#define RK3026_HPOUTR_EN         		(0x1 << 4)
+#define RK3026_HPOUTR_DIS			(0x0 << 4)
+#define RK3026_HPOUTR_INIT_MSK			(0x1 << 3)
+#define RK3026_HPOUTR_WORK			(0x1 << 3)
+#define RK3026_HPOUTR_INIT			(0x0 << 3)
+#define RK3026_HPOUTR_MUTE_SHT			(2)
+#define RK3026_HPOUTR_MUTE_MSK			(0x1 << 2)
+#define RK3026_HPOUTR_MUTE_EN			(0x0 << 2)
+#define RK3026_HPOUTR_MUTE_DIS			(0x1 << 2)
+
+#define RK3026_HPVREF_PWR_SHT			(1)
+#define RK3026_HPVREF_EN			(0x1 << 1)
+#define RK3026_HPVREF_DIS			(0x0 << 1)
+#define RK3026_HPVREF_WORK			(0x1 << 0)
+#define RK3026_HPVREF_INIT			(0x0 << 0)
+
+/* HPOUT GAIN (0xb4 0xb8) */
+#define  RK3026_HPOUT_GAIN_SFT			(0)
+
+/* SELECT CURR prechagrge/discharge (0xbc) */
+#define RK3026_PRE_HPOUT			(0x1 << 5)
+#define RK3026_DIS_HPOUT			(0x0 << 5)
+#define RK3026_CUR_10UA_EN			(0x0 << 4)
+#define RK3026_CUR_10UA_DIS			(0x1 << 4)
+#define RK3026_CUR_I_EN				(0x0 << 3)
+#define RK3026_CUR_I_DIS			(0x1 << 3)	
+#define RK3026_CUR_2I_EN			(0x0 << 2)
+#define RK3026_CUR_2I_DIS			(0x1 << 2)
+#define RK3026_CUR_4I_EN			(0x0 << 0)
+#define RK3026_CUR_4I_DIS			(0x3 << 0)
+
+/* PGA AGC control 1 (0xc0 0x100) */
+#define RK3026_PGA_AGC_WAY_MASK			(0x1 << 6)
+#define RK3026_PGA_AGC_WAY_SFT			6
+#define RK3026_PGA_AGC_WAY_JACK			(0x1 << 6)
+#define RK3026_PGA_AGC_WAY_NOR			(0x0 << 6)
+
+#define RK3026_PGA_AGC_BK_WAY_SFT			4
+#define RK3026_PGA_AGC_BK_WAY_JACK1		(0x1 << 4)
+#define RK3026_PGA_AGC_BK_WAY_NOR			(0x0 << 4)
+#define RK3026_PGA_AGC_BK_WAY_JACK2		(0x2 << 4)
+#define RK3026_PGA_AGC_BK_WAY_JACK3		(0x3 << 4)
+
+#define RK3026_PGA_AGC_HOLD_T_MASK		0xf
+#define RK3026_PGA_AGC_HOLD_T_SFT		0
+#define RK3026_PGA_AGC_HOLD_T_1024		0xa
+#define RK3026_PGA_AGC_HOLD_T_512		0x9
+#define RK3026_PGA_AGC_HOLD_T_256		0x8
+#define RK3026_PGA_AGC_HOLD_T_128		0x7
+#define RK3026_PGA_AGC_HOLD_T_64			0x6
+#define RK3026_PGA_AGC_HOLD_T_32			0x5
+#define RK3026_PGA_AGC_HOLD_T_16			0x4
+#define RK3026_PGA_AGC_HOLD_T_8			0x3
+#define RK3026_PGA_AGC_HOLD_T_4			0x2
+#define RK3026_PGA_AGC_HOLD_T_2			0x1
+#define RK3026_PGA_AGC_HOLD_T_0			0x0
+
+/* PGA AGC control 2 (0xc4 0x104) */
+#define RK3026_PGA_AGC_GRU_T_MASK		(0xf << 4)
+#define RK3026_PGA_AGC_GRU_T_SFT			4
+#define RK3026_PGA_AGC_GRU_T_512			(0xa << 4)
+#define RK3026_PGA_AGC_GRU_T_256			(0x9 << 4)
+#define RK3026_PGA_AGC_GRU_T_128			(0x8 << 4)
+#define RK3026_PGA_AGC_GRU_T_64			(0x7 << 4)
+#define RK3026_PGA_AGC_GRU_T_32			(0x6 << 4)
+#define RK3026_PGA_AGC_GRU_T_16			(0x5 << 4)
+#define RK3026_PGA_AGC_GRU_T_8			(0x4 << 4)
+#define RK3026_PGA_AGC_GRU_T_4			(0x3 << 4)
+#define RK3026_PGA_AGC_GRU_T_2			(0x2 << 4)
+#define RK3026_PGA_AGC_GRU_T_1			(0x1 << 4)
+#define RK3026_PGA_AGC_GRU_T_0_5			(0x0 << 4)
+
+#define RK3026_PGA_AGC_GRD_T_MASK		0xf
+#define RK3026_PGA_AGC_GRD_T_SFT			0
+#define RK3026_PGA_AGC_GRD_T_128_32		0xa
+#define RK3026_PGA_AGC_GRD_T_64_16		0x9
+#define RK3026_PGA_AGC_GRD_T_32_8		0x8
+#define RK3026_PGA_AGC_GRD_T_16_4		0x7
+#define RK3026_PGA_AGC_GRD_T_8_2			0x6
+#define RK3026_PGA_AGC_GRD_T_4_1			0x5
+#define RK3026_PGA_AGC_GRD_T_2_0_512		0x4
+#define RK3026_PGA_AGC_GRD_T_1_0_256		0x3
+#define RK3026_PGA_AGC_GRD_T_0_500_128		0x2
+#define RK3026_PGA_AGC_GRD_T_0_250_64		0x1
+#define RK3026_PGA_AGC_GRD_T_0_125_32		0x0
+
+/* PGA AGC control 3 (0xc8 0x108) */
+#define RK3026_PGA_AGC_MODE_MASK			(0x1 << 7)
+#define RK3026_PGA_AGC_MODE_SFT			7
+#define RK3026_PGA_AGC_MODE_LIMIT		(0x1 << 7)
+#define RK3026_PGA_AGC_MODE_NOR			(0x0 << 7)
+
+#define RK3026_PGA_AGC_ZO_MASK			(0x1 << 6)
+#define RK3026_PGA_AGC_ZO_SFT			6
+#define RK3026_PGA_AGC_ZO_EN			(0x1 << 6)
+#define RK3026_PGA_AGC_ZO_DIS			(0x0 << 6)
+
+#define RK3026_PGA_AGC_REC_MODE_MASK		(0x1 << 5)
+#define RK3026_PGA_AGC_REC_MODE_SFT		5
+#define RK3026_PGA_AGC_REC_MODE_AC		(0x1 << 5)
+#define RK3026_PGA_AGC_REC_MODE_RN		(0x0 << 5)
+
+#define RK3026_PGA_AGC_FAST_D_MASK		(0x1 << 4)
+#define RK3026_PGA_AGC_FAST_D_SFT		4
+#define RK3026_PGA_AGC_FAST_D_EN			(0x1 << 4)
+#define RK3026_PGA_AGC_FAST_D_DIS		(0x0 << 4)
+
+#define RK3026_PGA_AGC_NG_MASK			(0x1 << 3)
+#define RK3026_PGA_AGC_NG_SFT			3
+#define RK3026_PGA_AGC_NG_EN			(0x1 << 3)
+#define RK3026_PGA_AGC_NG_DIS			(0x0 << 3)
+
+#define RK3026_PGA_AGC_NG_THR_MASK		0x7
+#define RK3026_PGA_AGC_NG_THR_SFT		0
+#define RK3026_PGA_AGC_NG_THR_N81DB		0x7
+#define RK3026_PGA_AGC_NG_THR_N75DB		0x6
+#define RK3026_PGA_AGC_NG_THR_N69DB		0x5
+#define RK3026_PGA_AGC_NG_THR_N63DB		0x4
+#define RK3026_PGA_AGC_NG_THR_N57DB		0x3
+#define RK3026_PGA_AGC_NG_THR_N51DB		0x2
+#define RK3026_PGA_AGC_NG_THR_N45DB		0x1
+#define RK3026_PGA_AGC_NG_THR_N39DB		0x0
+
+/* PGA AGC Control 4 (0xcc 0x10c) */
+#define RK3026_PGA_AGC_ZO_MODE_MASK		(0x1 << 5)
+#define RK3026_PGA_AGC_ZO_MODE_SFT		5
+#define RK3026_PGA_AGC_ZO_MODE_UWRC		(0x1 << 5)
+#define RK3026_PGA_AGC_ZO_MODE_UARC		(0x0 << 5)
+
+#define RK3026_PGA_AGC_VOL_MASK			0x1f
+#define RK3026_PGA_AGC_VOL_SFT			0
+
+/* PGA ASR Control (0xd0 0x110) */
+#define RK3026_PGA_SLOW_CLK_MASK			(0x1 << 3)
+#define RK3026_PGA_SLOW_CLK_SFT			3
+#define RK3026_PGA_SLOW_CLK_EN			(0x1 << 3)
+#define RK3026_PGA_SLOW_CLK_DIS			(0x0 << 3)
+
+#define RK3026_PGA_ASR_MASK			0x7
+#define RK3026_PGA_ASR_SFT			0
+#define RK3026_PGA_ASR_8KHz			0x7
+#define RK3026_PGA_ASR_12KHz			0x6
+#define RK3026_PGA_ASR_16KHz			0x5
+#define RK3026_PGA_ASR_24KHz			0x4
+#define RK3026_PGA_ASR_32KHz			0x3
+#define RK3026_PGA_ASR_441KHz			0x2
+#define RK3026_PGA_ASR_48KHz			0x1
+#define RK3026_PGA_ASR_96KHz			0x0
+
+/* PGA AGC Control 5 (0xe4 0x124) */
+#define RK3026_PGA_AGC_MASK			(0x1 << 6)
+#define RK3026_PGA_AGC_SFT			6
+#define RK3026_PGA_AGC_EN			(0x1 << 6)
+#define RK3026_PGA_AGC_DIS			(0x0 << 6)
+
+#define RK3026_PGA_AGC_MAX_G_MASK		(0x7 << 3)
+#define RK3026_PGA_AGC_MAX_G_SFT			3
+#define RK3026_PGA_AGC_MAX_G_28_5DB		(0x7 << 3)
+#define RK3026_PGA_AGC_MAX_G_22_5DB		(0x6 << 3)
+#define RK3026_PGA_AGC_MAX_G_16_5DB		(0x5 << 3)
+#define RK3026_PGA_AGC_MAX_G_10_5DB		(0x4 << 3)
+#define RK3026_PGA_AGC_MAX_G_4_5DB		(0x3 << 3)
+#define RK3026_PGA_AGC_MAX_G_N1_5DB		(0x2 << 3)
+#define RK3026_PGA_AGC_MAX_G_N7_5DB		(0x1 << 3)
+#define RK3026_PGA_AGC_MAX_G_N13_5DB		(0x0 << 3)
+
+#define RK3026_PGA_AGC_MIN_G_MASK		0x7
+#define RK3026_PGA_AGC_MIN_G_SFT			0
+#define RK3026_PGA_AGC_MIN_G_24DB		0x7
+#define RK3026_PGA_AGC_MIN_G_18DB		0x6
+#define RK3026_PGA_AGC_MIN_G_12DB		0x5
+#define RK3026_PGA_AGC_MIN_G_6DB			0x4
+#define RK3026_PGA_AGC_MIN_G_0DB			0x3
+#define RK3026_PGA_AGC_MIN_G_N6DB		0x2
+#define RK3026_PGA_AGC_MIN_G_N12DB		0x1
+#define RK3026_PGA_AGC_MIN_G_N18DB		0x0
+
+enum {
+	RK3026_HIFI,
+	RK3026_VOICE,
+};
+
+enum {
+	RK3026_MONO = 1,
+	RK3026_STEREO,
+};
+
+enum {
+	OFF,
+	RCV,
+	SPK_PATH,
+	HP_PATH,
+	HP_NO_MIC,
+	BT,
+	SPK_HP,
+	RING_SPK,
+	RING_HP,
+	RING_HP_NO_MIC,
+	RING_SPK_HP,
+};
+
+enum {
+	MIC_OFF,
+	Main_Mic,
+	Hands_Free_Mic,
+	BT_Sco_Mic,
+};
+
+struct rk3026_reg_val_typ {
+	unsigned int reg;
+	unsigned int value;
+};
+
+struct rk3026_init_bit_typ {
+	unsigned int reg;
+	unsigned int power_bit;
+	unsigned int init_bit;
+};
+
+bool get_hdmi_state(void);
+
+struct rk3026_codec_pdata {
+	int spk_ctl_gpio;
+	int hp_ctl_gpio;	
+};
+
+#endif //__RK3026_CODEC_H__
--- a/sound/soc/rk29/rk_rk3026.c
+++ b/sound/soc/rk29/rk_rk3026.c
@@ -0,0 +1,290 @@
+/*
+ * rk_rk3026.c  --  SoC audio for rockchip
+ *
+ * Driver for rockchip rk3026 audio
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <asm/io.h>
+#include <mach/hardware.h>
+#include "../codecs/rk3026_codec.h"
+#include "rk29_pcm.h"
+#include "rk29_i2s.h"
+
+#if 0
+#define	DBG(x...)	printk(KERN_INFO x)
+#else
+#define	DBG(x...)
+#endif
+
+static const struct snd_soc_dapm_widget rk_dapm_widgets[] = {
+	SND_SOC_DAPM_MIC("Mic Jack", NULL),
+	SND_SOC_DAPM_MIC("Headset Jack", NULL),
+	SND_SOC_DAPM_SPK("Ext Spk", NULL),
+	SND_SOC_DAPM_HP("Headphone Jack", NULL),
+};
+
+static const struct snd_soc_dapm_route rk_audio_map[]={
+
+	/* Mic Jack --> MIC_IN*/
+	{"Mic Bias", NULL, "Mic Jack"},
+	{"MICP", NULL, "Mic Bias"},
+	{"MICN", NULL, "Mic Bias"},
+
+	// HP MIC
+	{"Mic Bias", NULL, "Headset Jack"},
+
+	{"Ext Spk", NULL, "HPOUTR"},
+	{"Ext Spk", NULL, "HPOUTL"},
+
+	{"Headphone Jack", NULL, "HPOUTR"},
+	{"Headphone Jack", NULL, "HPOUTL"},
+} ;
+
+static const struct snd_kcontrol_new rk_controls[] = {
+	SOC_DAPM_PIN_SWITCH("Mic Jack"),
+	SOC_DAPM_PIN_SWITCH("Headset Jack"),
+	SOC_DAPM_PIN_SWITCH("Ext Spk"),
+	SOC_DAPM_PIN_SWITCH("Headphone Jack"),
+};
+
+static int rk3026_init(struct snd_soc_pcm_runtime *rtd)
+{
+	struct snd_soc_codec *codec = rtd->codec;
+	struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+	DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+
+	snd_soc_add_controls(codec, rk_controls,
+			ARRAY_SIZE(rk_controls));
+
+	/* Add specific widgets */
+	snd_soc_dapm_new_controls(dapm, rk_dapm_widgets,
+				  ARRAY_SIZE(rk_dapm_widgets));
+	/* Set up specific audio path audio_mapnects */
+	snd_soc_dapm_add_routes(dapm, rk_audio_map, ARRAY_SIZE(rk_audio_map));
+
+	snd_soc_dapm_enable_pin(dapm, "Mic Jack");
+	snd_soc_dapm_enable_pin(dapm, "Headset Jack");
+	snd_soc_dapm_enable_pin(dapm, "Ext Spk");
+	snd_soc_dapm_enable_pin(dapm, "Headphone Jack");
+
+	snd_soc_dapm_sync(dapm);
+
+	return 0;
+}
+
+static int rk_hifi_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	unsigned int pll_out = 0;
+	int ret;
+
+	DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+
+	/* set codec DAI configuration */
+	#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
+
+	ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+	                SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+	#endif
+	#if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
+
+	ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+	                SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM );
+	#endif
+	if (ret < 0)
+		return ret;
+
+	/* set cpu DAI configuration */
+	#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
+	ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+	                SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
+	#endif
+	#if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
+	ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+	                SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
+	#endif
+	if (ret < 0)
+		return ret;
+
+	switch(params_rate(params)) {
+		case 8000:
+		case 16000:
+		case 24000:
+		case 32000:
+		case 48000:
+			pll_out = 12288000;
+			break;
+		case 11025:
+		case 22050:
+		case 44100:
+			pll_out = 11289600;
+			break;
+		default:
+			DBG("Enter:%s, %d, Error rate=%d\n", __FUNCTION__, __LINE__, params_rate(params));
+			return -EINVAL;
+			break;
+	}
+
+	DBG("Enter:%s, %d, rate=%d\n", __FUNCTION__, __LINE__, params_rate(params));
+
+	/*Set the system clk for codec*/
+	ret = snd_soc_dai_set_sysclk(codec_dai, 0, pll_out, SND_SOC_CLOCK_IN);
+	if (ret < 0) {
+		DBG("rk_hifi_hw_params:failed to set the sysclk for codec side\n");
+		return ret;
+	}
+
+	snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0);
+	snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK, (pll_out/4)/params_rate(params)-1);
+	snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 3);
+
+	DBG("Enter:%s, %d, pll_out/4/params_rate(params) = %d \n", __FUNCTION__, __LINE__, (pll_out/4)/params_rate(params));
+
+	return 0;
+}
+
+static int rk_voice_hw_params(struct snd_pcm_substream *substream,
+	struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+	unsigned int pll_out = 0;
+	int ret;
+
+	DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+
+	/* set codec DAI configuration */
+	ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A |
+				SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS);
+
+	switch(params_rate(params)) {
+		case 8000:
+		case 16000:
+		case 24000:
+		case 32000:
+		case 48000:
+			pll_out = 12288000;
+			break;
+		case 11025:
+		case 22050:
+		case 44100:
+			pll_out = 11289600;
+			break;
+		default:
+			DBG("Enter:%s, %d, Error rate=%d\n", __FUNCTION__, __LINE__, params_rate(params));
+			return -EINVAL;
+			break;
+	}
+
+	/*Set the system clk for codec*/
+	ret = snd_soc_dai_set_sysclk(codec_dai, 0, pll_out, SND_SOC_CLOCK_IN);
+
+	if (ret < 0) {
+		printk("rk_voice_hw_params:failed to set the sysclk for codec side\n");
+		return ret;
+	}
+
+	ret = snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0);
+
+	return 0;
+}
+
+static struct snd_soc_ops rk3026_hifi_ops = {
+	.hw_params = rk_hifi_hw_params,
+};
+
+static struct snd_soc_ops rk3026_voice_ops = {
+	.hw_params = rk_voice_hw_params,
+};
+
+static struct snd_soc_dai_link rk_dai[] = {
+	{
+		.name = "RK3026 I2S1",
+		.stream_name = "RK3026 PCM",
+		.codec_name = "rk3026-codec",
+		.platform_name = "rockchip-audio",
+#if defined(CONFIG_SND_RK29_SOC_I2S_8CH)
+		.cpu_dai_name = "rk29_i2s.0",
+#elif defined(CONFIG_SND_RK29_SOC_I2S_2CH)
+		.cpu_dai_name = "rk29_i2s.1",
+#endif
+		.codec_dai_name = "rk3026-hifi",
+		.init = rk3026_init,
+		.ops = &rk3026_hifi_ops,
+	},
+	{
+		.name = "RK3026 I2S2",
+		.stream_name = "RK3026 PCM",
+		.codec_name = "rk3026-codec",
+		.platform_name = "rockchip-audio",
+#if defined(CONFIG_SND_RK29_SOC_I2S_8CH)
+		.cpu_dai_name = "rk29_i2s.0",
+#elif defined(CONFIG_SND_RK29_SOC_I2S_2CH)
+		.cpu_dai_name = "rk29_i2s.1",
+#endif
+		.codec_dai_name = "rk3026-voice",
+		.ops = &rk3026_voice_ops,
+	},
+};
+
+static struct snd_soc_card snd_soc_card_rk = {
+	.name = "RK_RK3026",
+	.dai_link = rk_dai,
+	.num_links = 2,
+};
+
+static struct platform_device *rk_snd_device;
+
+static int __init audio_card_init(void)
+{
+	int ret =0;
+
+	DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
+
+	rk_snd_device = platform_device_alloc("soc-audio", -1);
+	if (!rk_snd_device) {
+		  printk("platform device allocation failed\n");
+		  return -ENOMEM;
+	}
+
+	platform_set_drvdata(rk_snd_device, &snd_soc_card_rk);
+	ret = platform_device_add(rk_snd_device);
+	if (ret) {
+		printk("platform device add failed\n");
+
+		platform_device_put(rk_snd_device);
+		return ret;
+	}
+
+        return ret;
+}
+
+static void __exit audio_card_exit(void)
+{
+	platform_device_unregister(rk_snd_device);
+}
+
+module_init(audio_card_init);
+module_exit(audio_card_exit);
+/* Module information */
+MODULE_AUTHOR("rockchip");
+MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface");
+MODULE_LICENSE("GPL");