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drm/rockchip: Add rk628 display driver

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Change-Id: I7be65c5ed58df2be2cf2cfe819feacf8a610e880
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
This commit is contained in:
Wyon Bi
2019-10-23 14:26:13 +08:00
committed by Tao Huang
parent bd9377a5be
commit e285c9b20e
9 changed files with 2809 additions and 0 deletions
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1
drivers/gpu/drm/rockchip/Kconfig
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@@ -94,5 +94,6 @@ config ROCKCHIP_RGB
say Y to enable its driver.
source "drivers/gpu/drm/rockchip/rk618/Kconfig"
source "drivers/gpu/drm/rockchip/rk628/Kconfig"
endif

1
drivers/gpu/drm/rockchip/Makefile
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@@ -21,3 +21,4 @@ rockchipdrm-$(CONFIG_ROCKCHIP_RGB) += rockchip_rgb.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o
obj-$(CONFIG_DRM_ROCKCHIP_RK618) += rk618/
obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628/

8
drivers/gpu/drm/rockchip/rk628/Kconfig Normal file
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@@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
config DRM_ROCKCHIP_RK628
tristate "Rockchip RK628 display bridge driver"
depends on DRM_ROCKCHIP
depends on MFD_RK628
---help---
Rockchip RK628 display bridge chips driver.

10
drivers/gpu/drm/rockchip/rk628/Makefile Normal file
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@@ -0,0 +1,10 @@
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for the Rockchip RK628 display bridge driver.
#
obj-$(CONFIG_DRM_ROCKCHIP_RK628) += rk628_combtxphy.o \
rk628_dsi.o \
rk628_lvds.o \
rk628_post_process.o \
rk628_rgb.o

465
drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c Normal file
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@@ -0,0 +1,465 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*
* Author: Wyon Bi <bivvy.bi@rock-chips.com>
*/
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/phy/phy.h>
#include <linux/mfd/rk628.h>
#define REG(x) ((x) + 0x90000)
#define COMBTXPHY_CON0 REG(0x0000)
#define SW_TX_IDLE_MASK GENMASK(29, 20)
#define SW_TX_IDLE(x) UPDATE(x, 29, 20)
#define SW_TX_PD_MASK GENMASK(17, 8)
#define SW_TX_PD(x) UPDATE(x, 17, 8)
#define SW_BUS_WIDTH_MASK GENMASK(6, 5)
#define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5)
#define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5)
#define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5)
#define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5)
#define SW_PD_PLL_MASK BIT(4)
#define SW_PD_PLL BIT(4)
#define SW_GVI_LVDS_EN_MASK BIT(3)
#define SW_GVI_LVDS_EN BIT(3)
#define SW_MIPI_DSI_EN_MASK BIT(2)
#define SW_MIPI_DSI_EN BIT(2)
#define SW_MODULEB_EN_MASK BIT(1)
#define SW_MODULEB_EN BIT(1)
#define SW_MODULEA_EN_MASK BIT(0)
#define SW_MODULEA_EN BIT(0)
#define COMBTXPHY_CON1 REG(0x0004)
#define COMBTXPHY_CON2 REG(0x0008)
#define COMBTXPHY_CON3 REG(0x000c)
#define COMBTXPHY_CON4 REG(0x0010)
#define COMBTXPHY_CON5 REG(0x0014)
#define SW_RATE(x) UPDATE(x, 26, 24)
#define SW_REF_DIV(x) UPDATE(x, 20, 16)
#define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10)
#define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0)
#define COMBTXPHY_CON6 REG(0x0018)
#define COMBTXPHY_CON7 REG(0x001c)
#define SW_TX_RTERM_MASK GENMASK(22, 20)
#define SW_TX_RTERM(x) UPDATE(x, 22, 20)
#define SW_TX_MODE_MASK GENMASK(17, 16)
#define SW_TX_MODE(x) UPDATE(x, 17, 16)
#define SW_TX_CTL_CON5_MASK BIT(10)
#define SW_TX_CTL_CON5(x) UPDATE(x, 10, 10)
#define SW_TX_CTL_CON4_MASK GENMASK(9, 8)
#define SW_TX_CTL_CON4(x) UPDATE(x, 9, 8)
#define COMBTXPHY_CON8 REG(0x0020)
#define COMBTXPHY_CON9 REG(0x0024)
#define SW_DSI_FSET_EN_MASK BIT(29)
#define SW_DSI_FSET_EN BIT(29)
#define SW_DSI_RCAL_EN_MASK BIT(28)
#define SW_DSI_RCAL_EN BIT(28)
#define COMBTXPHY_CON10 REG(0x0028)
#define TX9_CKDRV_EN BIT(9)
#define TX8_CKDRV_EN BIT(8)
#define TX7_CKDRV_EN BIT(7)
#define TX6_CKDRV_EN BIT(6)
#define TX5_CKDRV_EN BIT(5)
#define TX4_CKDRV_EN BIT(4)
#define TX3_CKDRV_EN BIT(3)
#define TX2_CKDRV_EN BIT(2)
#define TX1_CKDRV_EN BIT(1)
#define TX0_CKDRV_EN BIT(0)
#define COMBTXPHY_MAX_REGISTER COMBTXPHY_CON10
struct rk628_combtxphy {
struct device *dev;
struct rk628 *parent;
struct regmap *grf;
struct regmap *regmap;
struct clk *pclk;
struct reset_control *rstc;
enum phy_mode mode;
unsigned int flags;
u8 ref_div;
u8 fb_div;
u16 frac_div;
u8 rate_div;
};
static int rk628_combtxphy_dsi_power_on(struct rk628_combtxphy *combtxphy)
{
u32 val;
int ret;
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
SW_MIPI_DSI_EN_MASK,
SW_BUS_WIDTH_8BIT | SW_MIPI_DSI_EN);
if (combtxphy->flags & COMBTXPHY_MODULEA_EN)
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_MODULEA_EN_MASK, SW_MODULEA_EN);
if (combtxphy->flags & COMBTXPHY_MODULEB_EN)
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_MODULEB_EN_MASK, SW_MODULEB_EN);
regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
SW_REF_DIV(combtxphy->ref_div - 1) |
SW_PLL_FB_DIV(combtxphy->fb_div) |
SW_PLL_FRAC_DIV(combtxphy->frac_div) |
SW_RATE(combtxphy->rate_div / 2));
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_PD_PLL, 0);
ret = regmap_read_poll_timeout(combtxphy->grf, GRF_DPHY0_STATUS,
val, val & DPHY_PHYLOCK, 0, 1000);
if (ret < 0) {
dev_err(combtxphy->dev, "phy is not lock\n");
return ret;
}
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON9,
SW_DSI_FSET_EN_MASK | SW_DSI_RCAL_EN_MASK,
SW_DSI_FSET_EN | SW_DSI_RCAL_EN);
usleep_range(200, 400);
return 0;
}
static int rk628_combtxphy_lvds_power_on(struct rk628_combtxphy *combtxphy)
{
u32 val;
int ret;
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON7,
SW_TX_MODE_MASK, SW_TX_MODE(3));
regmap_write(combtxphy->regmap, COMBTXPHY_CON10,
TX7_CKDRV_EN | TX2_CKDRV_EN);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
SW_MIPI_DSI_EN_MASK,
SW_BUS_WIDTH_7BIT | SW_GVI_LVDS_EN);
if (combtxphy->flags & COMBTXPHY_MODULEA_EN)
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_MODULEA_EN_MASK, SW_MODULEA_EN);
if (combtxphy->flags & COMBTXPHY_MODULEB_EN)
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_MODULEB_EN_MASK, SW_MODULEB_EN);
regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
SW_REF_DIV(combtxphy->ref_div - 1) |
SW_PLL_FB_DIV(combtxphy->fb_div) |
SW_PLL_FRAC_DIV(combtxphy->frac_div) |
SW_RATE(combtxphy->rate_div / 2));
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_PD_PLL | SW_TX_PD_MASK, 0);
ret = regmap_read_poll_timeout(combtxphy->grf, GRF_DPHY0_STATUS,
val, val & DPHY_PHYLOCK, 0, 1000);
if (ret < 0) {
dev_info(combtxphy->dev, "phy is not lock\n");
return ret;
}
usleep_range(100, 200);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_TX_IDLE_MASK, 0);
return 0;
}
static int rk628_combtxphy_gvi_power_on(struct rk628_combtxphy *combtxphy)
{
regmap_write(combtxphy->regmap, COMBTXPHY_CON5,
SW_REF_DIV(combtxphy->ref_div - 1) |
SW_PLL_FB_DIV(combtxphy->fb_div) |
SW_PLL_FRAC_DIV(combtxphy->frac_div) |
SW_RATE(combtxphy->rate_div / 2));
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_BUS_WIDTH_MASK | SW_GVI_LVDS_EN_MASK |
SW_MIPI_DSI_EN_MASK |
SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK,
SW_BUS_WIDTH_10BIT | SW_GVI_LVDS_EN |
SW_MODULEB_EN | SW_MODULEA_EN);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_PD_PLL | SW_TX_PD_MASK, 0);
usleep_range(100, 200);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_TX_IDLE_MASK, 0);
return 0;
}
static int rk628_combtxphy_power_on(struct phy *phy)
{
struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
clk_prepare_enable(combtxphy->pclk);
reset_control_assert(combtxphy->rstc);
udelay(10);
reset_control_deassert(combtxphy->rstc);
udelay(10);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK,
SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
switch (combtxphy->mode) {
case PHY_MODE_VIDEO_MIPI:
regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
SW_TXPHY_REFCLK_SEL_MASK,
SW_TXPHY_REFCLK_SEL(0));
return rk628_combtxphy_dsi_power_on(combtxphy);
case PHY_MODE_VIDEO_LVDS:
regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
SW_TXPHY_REFCLK_SEL_MASK,
SW_TXPHY_REFCLK_SEL(1));
return rk628_combtxphy_lvds_power_on(combtxphy);
case PHY_MODE_GVI:
regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
SW_TXPHY_REFCLK_SEL_MASK,
SW_TXPHY_REFCLK_SEL(0));
return rk628_combtxphy_gvi_power_on(combtxphy);
default:
return -EINVAL;
}
return 0;
}
static int rk628_combtxphy_power_off(struct phy *phy)
{
struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
regmap_update_bits(combtxphy->regmap, COMBTXPHY_CON0,
SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK |
SW_MODULEB_EN_MASK | SW_MODULEA_EN_MASK,
SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
clk_disable_unprepare(combtxphy->pclk);
return 0;
}
static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode)
{
struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
unsigned int fvco, frac_rate, fin = 24;
switch (mode) {
case PHY_MODE_VIDEO_MIPI:
{
int bus_width = phy_get_bus_width(phy);
unsigned int fhsc = bus_width >> 8;
unsigned int flags = bus_width & 0xff;
fhsc = fin * (fhsc / fin);
if (fhsc < 80 || fhsc > 1500)
return -EINVAL;
else if (fhsc < 375)
combtxphy->rate_div = 4;
else if (fhsc < 750)
combtxphy->rate_div = 2;
else
combtxphy->rate_div = 1;
combtxphy->flags = flags;
fvco = fhsc * 2 * combtxphy->rate_div;
combtxphy->ref_div = 1;
combtxphy->fb_div = fvco / 8 / fin;
frac_rate = fvco - (fin * 8 * combtxphy->fb_div);
if (frac_rate) {
frac_rate <<= 10;
frac_rate /= fin * 8;
combtxphy->frac_div = frac_rate;
} else {
combtxphy->frac_div = 0;
}
fvco = fin * (1024 * combtxphy->fb_div + combtxphy->frac_div);
fvco *= 8;
fvco = DIV_ROUND_UP(fvco, 1024 * combtxphy->ref_div);
fhsc = fvco / 2 / combtxphy->rate_div;
phy_set_bus_width(phy, fhsc);
break;
}
case PHY_MODE_VIDEO_LVDS:
{
int bus_width = phy_get_bus_width(phy);
unsigned int flags = bus_width & 0xff;
unsigned int rate = (bus_width >> 8) * 7;
combtxphy->flags = flags;
combtxphy->ref_div = 1;
combtxphy->fb_div = 14;
combtxphy->frac_div = 0;
if (rate < 500)
combtxphy->rate_div = 4;
else if (rate < 1000)
combtxphy->rate_div = 2;
else
combtxphy->rate_div = 1;
break;
}
case PHY_MODE_GVI:
{
unsigned int fhsc = phy_get_bus_width(phy) & 0xfff;
if (fhsc < 500 || fhsc > 4000)
return -EINVAL;
else if (fhsc < 1000)
combtxphy->rate_div = 4;
else if (fhsc < 2000)
combtxphy->rate_div = 2;
else
combtxphy->rate_div = 1;
fvco = fhsc * combtxphy->rate_div;
combtxphy->ref_div = 1;
combtxphy->fb_div = fvco / 8 / fin;
frac_rate = fvco - (fin * 8 * combtxphy->fb_div);
if (frac_rate) {
frac_rate <<= 10;
frac_rate /= fin * 8;
combtxphy->frac_div = frac_rate;
} else {
combtxphy->frac_div = 0;
}
fvco = fin * (1024 * combtxphy->fb_div + combtxphy->frac_div);
fvco *= 8;
fvco /= 1024 * combtxphy->ref_div;
fhsc = fvco / combtxphy->rate_div;
phy_set_bus_width(phy, fhsc);
break;
}
default:
return -EINVAL;
}
combtxphy->mode = mode;
return 0;
}
static const struct phy_ops rk628_combtxphy_ops = {
.set_mode = rk628_combtxphy_set_mode,
.power_on = rk628_combtxphy_power_on,
.power_off = rk628_combtxphy_power_off,
.owner = THIS_MODULE,
};
static const struct regmap_range rk628_combtxphy_readable_ranges[] = {
regmap_reg_range(COMBTXPHY_CON0, COMBTXPHY_CON10),
};
static const struct regmap_access_table rk628_combtxphy_readable_table = {
.yes_ranges = rk628_combtxphy_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(rk628_combtxphy_readable_ranges),
};
static const struct regmap_config rk628_combtxphy_regmap_cfg = {
.name = "combtxphy",
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.cache_type = REGCACHE_RBTREE,
.max_register = COMBTXPHY_MAX_REGISTER,
.reg_format_endian = REGMAP_ENDIAN_LITTLE,
.val_format_endian = REGMAP_ENDIAN_LITTLE,
.rd_table = &rk628_combtxphy_readable_table,
};
static int rk628_combtxphy_probe(struct platform_device *pdev)
{
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct rk628_combtxphy *combtxphy;
struct phy_provider *phy_provider;
struct phy *phy;
int ret;
combtxphy = devm_kzalloc(dev, sizeof(*combtxphy), GFP_KERNEL);
if (!combtxphy)
return -ENOMEM;
combtxphy->dev = dev;
combtxphy->parent = rk628;
combtxphy->grf = rk628->grf;
platform_set_drvdata(pdev, combtxphy);
combtxphy->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(combtxphy->pclk))
return PTR_ERR(combtxphy->pclk);
combtxphy->rstc = of_reset_control_get(dev->of_node, NULL);
if (IS_ERR(combtxphy->rstc)) {
ret = PTR_ERR(combtxphy->rstc);
dev_err(dev, "failed to get reset control: %d\n", ret);
return ret;
}
combtxphy->regmap = devm_regmap_init_i2c(rk628->client,
&rk628_combtxphy_regmap_cfg);
if (IS_ERR(combtxphy->regmap)) {
ret = PTR_ERR(combtxphy->regmap);
dev_err(dev, "failed to allocate register map: %d\n", ret);
return ret;
}
regmap_write(combtxphy->regmap, COMBTXPHY_CON0,
SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
phy = devm_phy_create(dev, NULL, &rk628_combtxphy_ops);
if (IS_ERR(phy)) {
ret = PTR_ERR(phy);
dev_err(dev, "failed to create phy: %d\n", ret);
return ret;
}
phy_set_drvdata(phy, combtxphy);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
if (IS_ERR(phy_provider)) {
ret = PTR_ERR(phy_provider);
dev_err(dev, "failed to register phy provider: %d\n", ret);
return ret;
}
return 0;
}
static const struct of_device_id rk628_combtxphy_of_match[] = {
{ .compatible = "rockchip,rk628-combtxphy", },
{}
};
MODULE_DEVICE_TABLE(of, rk628_combtxphy_of_match);
static struct platform_driver rk628_combtxphy_driver = {
.driver = {
.name = "rk628-combtxphy",
.of_match_table = of_match_ptr(rk628_combtxphy_of_match),
},
.probe = rk628_combtxphy_probe,
};
module_platform_driver(rk628_combtxphy_driver);
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK628 GVI/LVDS/MIPI Combo TX PHY driver");
MODULE_LICENSE("GPL v2");

1393
drivers/gpu/drm/rockchip/rk628/rk628_dsi.c Normal file
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File diff suppressed because it is too large Load Diff

327
drivers/gpu/drm/rockchip/rk628/rk628_lvds.c Normal file
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@@ -0,0 +1,327 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*
* Author: Wyon Bi <bivvy.bi@rock-chips.com>
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/mfd/rk628.h>
#include <linux/phy/phy.h>
#include <drm/drmP.h>
#include <drm/drm_of.h>
#include <drm/drm_atomic.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_panel.h>
#include <video/of_display_timing.h>
#include <video/videomode.h>
enum lvds_format {
LVDS_FORMAT_VESA_24BIT,
LVDS_FORMAT_JEIDA_24BIT,
LVDS_FORMAT_JEIDA_18BIT,
LVDS_FORMAT_VESA_18BIT,
};
enum lvds_link_type {
LVDS_SINGLE_LINK,
LVDS_DUAL_LINK_ODD_EVEN_PIXELS,
LVDS_DUAL_LINK_EVEN_ODD_PIXELS,
LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS,
LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS,
};
struct rk628_lvds {
struct drm_bridge base;
struct drm_connector connector;
struct drm_panel *panel;
struct drm_display_mode mode;
struct device *dev;
struct regmap *grf;
struct phy *phy;
struct rk628 *parent;
enum lvds_format format;
enum lvds_link_type link_type;
};
static inline struct rk628_lvds *bridge_to_lvds(struct drm_bridge *b)
{
return container_of(b, struct rk628_lvds, base);
}
static inline struct rk628_lvds *connector_to_lvds(struct drm_connector *c)
{
return container_of(c, struct rk628_lvds, connector);
}
static enum lvds_format rk628_lvds_get_format(u32 bus_format)
{
switch (bus_format) {
case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA:
return LVDS_FORMAT_JEIDA_18BIT;
case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
return LVDS_FORMAT_JEIDA_24BIT;
case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
return LVDS_FORMAT_VESA_18BIT;
case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
default:
return LVDS_FORMAT_VESA_24BIT;
}
}
static enum lvds_link_type rk628_lvds_get_link_type(struct rk628_lvds *lvds)
{
struct device *dev = lvds->dev;
const char *str;
int ret;
ret = of_property_read_string(dev->of_node, "rockchip,link-type", &str);
if (ret < 0)
return LVDS_SINGLE_LINK;
if (!strcmp(str, "dual-link-odd-even-pixels"))
return LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
else if (!strcmp(str, "dual-link-even-odd-pixels"))
return LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
else if (!strcmp(str, "dual-link-left-right-pixels"))
return LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS;
else if (!strcmp(str, "dual-link-right-left-pixels"))
return LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS;
else
return LVDS_SINGLE_LINK;
}
static struct drm_encoder *
rk628_lvds_connector_best_encoder(struct drm_connector *connector)
{
struct rk628_lvds *lvds = connector_to_lvds(connector);
return lvds->base.encoder;
}
static int rk628_lvds_connector_get_modes(struct drm_connector *connector)
{
struct rk628_lvds *lvds = connector_to_lvds(connector);
struct drm_display_info *info = &connector->display_info;
int num_modes = 0;
num_modes = drm_panel_get_modes(lvds->panel);
if (info->num_bus_formats)
lvds->format = rk628_lvds_get_format(info->bus_formats[0]);
else
lvds->format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG;
return num_modes;
}
static const struct drm_connector_helper_funcs
rk628_lvds_connector_helper_funcs = {
.get_modes = rk628_lvds_connector_get_modes,
.best_encoder = rk628_lvds_connector_best_encoder,
};
static void rk628_lvds_connector_destroy(struct drm_connector *connector)
{
struct rk628_lvds *lvds = connector_to_lvds(connector);
drm_panel_detach(lvds->panel);
drm_connector_cleanup(connector);
}
static const struct drm_connector_funcs rk628_lvds_connector_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = rk628_lvds_connector_destroy,
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static void rk628_lvds_bridge_enable(struct drm_bridge *bridge)
{
struct rk628_lvds *lvds = bridge_to_lvds(bridge);
const struct drm_display_mode *mode = &lvds->mode;
u32 val, bus_width;
int ret;
regmap_update_bits(lvds->grf, GRF_SYSTEM_CON0, SW_OUTPUT_MODE_MASK,
SW_OUTPUT_MODE(OUTPUT_MODE_LVDS));
switch (lvds->link_type) {
case LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(0) |
SW_LVDS_CON_DUAL_SEL(0);
bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
break;
case LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(1) |
SW_LVDS_CON_DUAL_SEL(0);
bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
break;
case LVDS_DUAL_LINK_LEFT_RIGHT_PIXELS:
val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(0) |
SW_LVDS_CON_DUAL_SEL(1);
regmap_update_bits(lvds->grf, GRF_POST_PROC_CON,
SW_SPLIT_EN, SW_SPLIT_EN);
bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
break;
case LVDS_DUAL_LINK_RIGHT_LEFT_PIXELS:
val = SW_LVDS_CON_CHASEL(1) | SW_LVDS_CON_STARTSEL(1) |
SW_LVDS_CON_DUAL_SEL(1);
regmap_update_bits(lvds->grf, GRF_POST_PROC_CON,
SW_SPLIT_EN, SW_SPLIT_EN);
bus_width = COMBTXPHY_MODULEA_EN | COMBTXPHY_MODULEB_EN;
break;
case LVDS_SINGLE_LINK:
default:
val = SW_LVDS_CON_CHASEL(0) | SW_LVDS_CON_STARTSEL(0) |
SW_LVDS_CON_DUAL_SEL(0);
bus_width = COMBTXPHY_MODULEA_EN;
break;
}
val |= SW_LVDS_CON_SELECT(lvds->format) |
SW_LVDS_CON_MSBSEL(0) |
SW_LVDS_CON_CLKINV(0);
regmap_write(lvds->grf, GRF_LVDS_TX_CON, val);
bus_width |= (mode->clock / 1000) << 8;
phy_set_bus_width(lvds->phy, bus_width);
ret = phy_set_mode(lvds->phy, PHY_MODE_VIDEO_LVDS);
if (ret) {
dev_err(lvds->dev, "failed to set phy mode: %d\n", ret);
return;
}
phy_power_on(lvds->phy);
drm_panel_prepare(lvds->panel);
drm_panel_enable(lvds->panel);
}
static void rk628_lvds_bridge_disable(struct drm_bridge *bridge)
{
struct rk628_lvds *lvds = bridge_to_lvds(bridge);
drm_panel_disable(lvds->panel);
drm_panel_unprepare(lvds->panel);
phy_power_off(lvds->phy);
}
static int rk628_lvds_bridge_attach(struct drm_bridge *bridge)
{
struct rk628_lvds *lvds = bridge_to_lvds(bridge);
struct drm_connector *connector = &lvds->connector;
struct drm_device *drm = bridge->dev;
int ret;
ret = drm_connector_init(drm, connector, &rk628_lvds_connector_funcs,
DRM_MODE_CONNECTOR_LVDS);
if (ret) {
dev_err(lvds->dev, "Failed to initialize connector with drm\n");
return ret;
}
drm_connector_helper_add(connector, &rk628_lvds_connector_helper_funcs);
drm_connector_attach_encoder(connector, bridge->encoder);
ret = drm_panel_attach(lvds->panel, connector);
if (ret) {
dev_err(lvds->dev, "Failed to attach panel\n");
return ret;
}
return 0;
}
static void rk628_lvds_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adj)
{
struct rk628_lvds *lvds = bridge_to_lvds(bridge);
drm_mode_copy(&lvds->mode, mode);
}
static const struct drm_bridge_funcs rk628_lvds_bridge_funcs = {
.attach = rk628_lvds_bridge_attach,
.enable = rk628_lvds_bridge_enable,
.disable = rk628_lvds_bridge_disable,
.mode_set = rk628_lvds_bridge_mode_set,
};
static int rk628_lvds_probe(struct platform_device *pdev)
{
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct rk628_lvds *lvds;
int ret;
if (!of_device_is_available(dev->of_node))
return -ENODEV;
lvds = devm_kzalloc(dev, sizeof(*lvds), GFP_KERNEL);
if (!lvds)
return -ENOMEM;
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
&lvds->panel, NULL);
if (ret)
return ret;
lvds->dev = dev;
lvds->parent = rk628;
lvds->grf = rk628->grf;
lvds->link_type = rk628_lvds_get_link_type(lvds);
platform_set_drvdata(pdev, lvds);
lvds->phy = devm_of_phy_get(dev, dev->of_node, NULL);
if (IS_ERR(lvds->phy)) {
ret = PTR_ERR(lvds->phy);
dev_err(dev, "failed to get phy: %d\n", ret);
return ret;
}
lvds->base.funcs = &rk628_lvds_bridge_funcs;
lvds->base.of_node = dev->of_node;
drm_bridge_add(&lvds->base);
return 0;
}
static int rk628_lvds_remove(struct platform_device *pdev)
{
struct rk628_lvds *lvds = platform_get_drvdata(pdev);
drm_bridge_remove(&lvds->base);
return 0;
}
static const struct of_device_id rk628_lvds_of_match[] = {
{ .compatible = "rockchip,rk628-lvds", },
{},
};
MODULE_DEVICE_TABLE(of, rk628_lvds_of_match);
static struct platform_driver rk628_lvds_driver = {
.driver = {
.name = "rk628-lvds",
.of_match_table = of_match_ptr(rk628_lvds_of_match),
},
.probe = rk628_lvds_probe,
.remove = rk628_lvds_remove,
};
module_platform_driver(rk628_lvds_driver);
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK628 LVDS driver");
MODULE_LICENSE("GPL v2");

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drivers/gpu/drm/rockchip/rk628/rk628_post_process.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*
* Author: Wyon Bi <bivvy.bi@rock-chips.com>
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/mfd/rk628.h>
#include <video/of_display_timing.h>
#include <video/videomode.h>
#include <drm/drm_of.h>
#include <drm/drmP.h>
struct rk628_post_process {
struct drm_bridge base;
struct drm_bridge *bridge;
struct drm_display_mode src_mode;
struct drm_display_mode dst_mode;
struct device *dev;
struct regmap *grf;
struct clk *sclk_vop;
struct clk *clk_rx_read;
struct reset_control *rstc_decoder;
struct reset_control *rstc_clk_rx;
struct reset_control *rstc_vop;
};
static inline struct rk628_post_process *bridge_to_pp(struct drm_bridge *bridge)
{
return container_of(bridge, struct rk628_post_process, base);
}
static void calc_dsp_frm_hst_vst(const struct videomode *src,
const struct videomode *dst,
u32 *dsp_frame_hst, u32 *dsp_frame_vst)
{
u32 bp_in, bp_out;
u32 v_scale_ratio;
u64 t_frm_st;
u64 t_bp_in, t_bp_out, t_delta, tin;
u32 src_pixclock, dst_pixclock;
u32 dsp_htotal, src_htotal, src_vtotal;
src_pixclock = div_u64(1000000000000llu, src->pixelclock);
dst_pixclock = div_u64(1000000000000llu, dst->pixelclock);
src_htotal = src->hsync_len + src->hback_porch + src->hactive +
src->hfront_porch;
src_vtotal = src->vsync_len + src->vback_porch + src->vactive +
src->vfront_porch;
dsp_htotal = dst->hsync_len + dst->hback_porch + dst->hactive +
dst->hfront_porch;
bp_in = (src->vback_porch + src->vsync_len) * src_htotal +
src->hsync_len + src->hback_porch;
bp_out = (dst->vback_porch + dst->vsync_len) * dsp_htotal +
dst->hsync_len + dst->hback_porch;
t_bp_in = bp_in * src_pixclock;
t_bp_out = bp_out * dst_pixclock;
tin = src_vtotal * src_htotal * src_pixclock;
v_scale_ratio = src->vactive / dst->vactive;
if (v_scale_ratio <= 2)
t_delta = 5 * src_htotal * src_pixclock;
else
t_delta = 12 * src_htotal * src_pixclock;
if (t_bp_in + t_delta > t_bp_out)
t_frm_st = (t_bp_in + t_delta - t_bp_out);
else
t_frm_st = tin - (t_bp_out - (t_bp_in + t_delta));
do_div(t_frm_st, src_pixclock);
*dsp_frame_hst = do_div(t_frm_st, src_htotal);
*dsp_frame_vst = t_frm_st;
}
static void rk628_post_process_scaler_init(struct rk628_post_process *pp,
const struct drm_display_mode *s,
const struct drm_display_mode *d)
{
struct videomode src, dst;
u32 dsp_frame_hst, dsp_frame_vst;
u32 scl_hor_mode, scl_ver_mode;
u32 scl_v_factor, scl_h_factor;
u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
u16 bor_right = 0, bor_left = 0, bor_up = 0, bor_down = 0;
u8 hor_down_mode = 0, ver_down_mode = 0;
drm_display_mode_to_videomode(s, &src);
drm_display_mode_to_videomode(d, &dst);
dsp_htotal = dst.hsync_len + dst.hback_porch + dst.hactive +
dst.hfront_porch;
dsp_vtotal = dst.vsync_len + dst.vback_porch + dst.vactive +
dst.vfront_porch;
dsp_hs_end = dst.hsync_len;
dsp_vs_end = dst.vsync_len;
dsp_hbor_end = dst.hsync_len + dst.hback_porch + dst.hactive;
dsp_hbor_st = dst.hsync_len + dst.hback_porch;
dsp_vbor_end = dst.vsync_len + dst.vback_porch + dst.vactive;
dsp_vbor_st = dst.vsync_len + dst.vback_porch;
dsp_hact_st = dsp_hbor_st + bor_left;
dsp_hact_end = dsp_hbor_end - bor_right;
dsp_vact_st = dsp_vbor_st + bor_up;
dsp_vact_end = dsp_vbor_end - bor_down;
calc_dsp_frm_hst_vst(&src, &dst, &dsp_frame_hst, &dsp_frame_vst);
dev_dbg(pp->dev, "dsp_frame_vst=%d, dsp_frame_hst=%d\n",
dsp_frame_vst, dsp_frame_hst);
if (src.hactive > dst.hactive) {
scl_hor_mode = 2;
if (hor_down_mode == 0) {
if ((src.hactive - 1) / (dst.hactive - 1) > 2)
scl_h_factor = ((src.hactive - 1) << 14) /
(dst.hactive - 1);
else
scl_h_factor = ((src.hactive - 2) << 14) /
(dst.hactive - 1);
} else {
scl_h_factor = (dst.hactive << 16) /
(src.hactive - 1);
}
dev_dbg(pp->dev, "horizontal scale down\n");
} else if (src.hactive == dst.hactive) {
scl_hor_mode = 0;
scl_h_factor = 0;
dev_dbg(pp->dev, "horizontal no scale\n");
} else {
scl_hor_mode = 1;
scl_h_factor = ((src.hactive - 1) << 16) / (dst.hactive - 1);
dev_dbg(pp->dev, "horizontal scale up\n");
}
if (src.vactive > dst.vactive) {
scl_ver_mode = 2;
if (ver_down_mode == 0) {
if ((src.vactive - 1) / (dst.vactive - 1) > 2)
scl_v_factor = ((src.vactive - 1) << 14) /
(dst.vactive - 1);
else
scl_v_factor = ((src.vactive - 2) << 14) /
(dst.vactive - 1);
} else {
scl_v_factor = (dst.vactive << 16) /
(src.vactive - 1);
}
dev_dbg(pp->dev, "vertical scale down\n");
} else if (src.vactive == dst.vactive) {
scl_ver_mode = 0;
scl_v_factor = 0;
dev_dbg(pp->dev, "vertical no scale\n");
} else {
scl_ver_mode = 1;
scl_v_factor = ((src.vactive - 1) << 16) / (dst.vactive - 1);
dev_dbg(pp->dev, "vertical scale up\n");
}
regmap_update_bits(pp->grf, GRF_RGB_DEC_CON0,
SW_HRES_MASK, SW_HRES(src.hactive));
regmap_write(pp->grf, GRF_SCALER_CON0,
SCL_VER_DOWN_MODE(ver_down_mode) |
SCL_HOR_DOWN_MODE(hor_down_mode) |
SCL_VER_MODE(scl_ver_mode) | SCL_HOR_MODE(scl_hor_mode));
regmap_write(pp->grf, GRF_SCALER_CON1,
SCL_V_FACTOR(scl_v_factor) | SCL_H_FACTOR(scl_h_factor));
regmap_write(pp->grf, GRF_SCALER_CON2,
DSP_FRAME_VST(dsp_frame_vst) |
DSP_FRAME_HST(dsp_frame_hst));
regmap_write(pp->grf, GRF_SCALER_CON3,
DSP_HS_END(dsp_hs_end) | DSP_HTOTAL(dsp_htotal));
regmap_write(pp->grf, GRF_SCALER_CON4,
DSP_HACT_END(dsp_hact_end) | DSP_HACT_ST(dsp_hact_st));
regmap_write(pp->grf, GRF_SCALER_CON5,
DSP_VS_END(dsp_vs_end) | DSP_VTOTAL(dsp_vtotal));
regmap_write(pp->grf, GRF_SCALER_CON6,
DSP_VACT_END(dsp_vact_end) | DSP_VACT_ST(dsp_vact_st));
regmap_write(pp->grf, GRF_SCALER_CON7,
DSP_HBOR_END(dsp_hbor_end) | DSP_HBOR_ST(dsp_hbor_st));
regmap_write(pp->grf, GRF_SCALER_CON8,
DSP_VBOR_END(dsp_vbor_end) | DSP_VBOR_ST(dsp_vbor_st));
}
static void rk628_post_process_bridge_pre_enable(struct drm_bridge *bridge)
{
struct rk628_post_process *pp = bridge_to_pp(bridge);
const struct drm_display_mode *src = &pp->src_mode;
const struct drm_display_mode *dst = &pp->dst_mode;
reset_control_assert(pp->rstc_decoder);
udelay(10);
reset_control_deassert(pp->rstc_decoder);
udelay(10);
clk_set_rate(pp->clk_rx_read, src->clock * 1000);
clk_prepare_enable(pp->clk_rx_read);
reset_control_assert(pp->rstc_clk_rx);
udelay(10);
reset_control_deassert(pp->rstc_clk_rx);
udelay(10);
clk_set_rate(pp->sclk_vop, dst->clock * 1000);
clk_prepare_enable(pp->sclk_vop);
reset_control_assert(pp->rstc_vop);
udelay(10);
reset_control_deassert(pp->rstc_vop);
udelay(10);
regmap_update_bits(pp->grf, GRF_SYSTEM_CON0, SW_VSYNC_POL_MASK,
SW_VSYNC_POL(1));
regmap_update_bits(pp->grf, GRF_SYSTEM_CON0, SW_HSYNC_POL_MASK,
SW_HSYNC_POL(1));
rk628_post_process_scaler_init(pp, src, dst);
}
static void rk628_post_process_bridge_post_disable(struct drm_bridge *bridge)
{
}
static void rk628_post_process_bridge_enable(struct drm_bridge *bridge)
{
struct rk628_post_process *pp = bridge_to_pp(bridge);
regmap_write(pp->grf, GRF_SCALER_CON0, SCL_EN(1));
}
static void rk628_post_process_bridge_disable(struct drm_bridge *bridge)
{
struct rk628_post_process *pp = bridge_to_pp(bridge);
regmap_write(pp->grf, GRF_SCALER_CON0, SCL_EN(0));
clk_disable_unprepare(pp->sclk_vop);
clk_disable_unprepare(pp->clk_rx_read);
}
static void rk628_post_process_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adj)
{
struct rk628_post_process *pp = bridge_to_pp(bridge);
drm_mode_copy(&pp->src_mode, adj);
if (pp->bridge->driver_private)
drm_mode_copy(&pp->dst_mode, pp->bridge->driver_private);
else
drm_mode_copy(&pp->dst_mode, &pp->src_mode);
}
static int rk628_post_process_bridge_attach(struct drm_bridge *bridge)
{
struct rk628_post_process *pp = bridge_to_pp(bridge);
struct device *dev = pp->dev;
int ret;
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
NULL, &pp->bridge);
if (ret)
return ret;
ret = drm_bridge_attach(bridge->encoder, pp->bridge, bridge);
if (ret) {
dev_err(dev, "failed to attach bridge\n");
return ret;
}
return 0;
}
static bool
rk628_post_process_bridge_mode_fixup(struct drm_bridge *bridge,
const struct drm_display_mode *mode,
struct drm_display_mode *adj)
{
/* Fixup sync polarities, both hsync and vsync are active high */
adj->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
adj->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
return true;
}
static const struct drm_bridge_funcs rk628_post_process_bridge_funcs = {
.pre_enable = rk628_post_process_bridge_pre_enable,
.post_disable = rk628_post_process_bridge_post_disable,
.enable = rk628_post_process_bridge_enable,
.disable = rk628_post_process_bridge_disable,
.mode_set = rk628_post_process_bridge_mode_set,
.mode_fixup = rk628_post_process_bridge_mode_fixup,
.attach = rk628_post_process_bridge_attach,
};
static int rk628_post_process_probe(struct platform_device *pdev)
{
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct rk628_post_process *pp;
int ret;
if (!of_device_is_available(dev->of_node))
return -ENODEV;
pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
if (!pp)
return -ENOMEM;
pp->dev = dev;
pp->grf = rk628->grf;
platform_set_drvdata(pdev, pp);
pp->sclk_vop = devm_clk_get(dev, "sclk_vop");
if (IS_ERR(pp->sclk_vop)) {
ret = PTR_ERR(pp->sclk_vop);
dev_err(dev, "failed to get sclk: %d\n", ret);
return ret;
}
pp->clk_rx_read = devm_clk_get(dev, "rx_read");
if (IS_ERR(pp->clk_rx_read)) {
ret = PTR_ERR(pp->clk_rx_read);
dev_err(dev, "failed to get clk_rx_read: %d\n", ret);
return ret;
}
pp->rstc_decoder = of_reset_control_get(dev->of_node, "decoder");
if (IS_ERR(pp->rstc_decoder)) {
ret = PTR_ERR(pp->rstc_decoder);
dev_err(dev, "failed to get decoder reset: %d\n", ret);
return ret;
}
pp->rstc_clk_rx = of_reset_control_get(dev->of_node, "clk_rx");
if (IS_ERR(pp->rstc_clk_rx)) {
ret = PTR_ERR(pp->rstc_clk_rx);
dev_err(dev, "failed to get clk_rx reset: %d\n", ret);
return ret;
}
pp->rstc_vop = of_reset_control_get(dev->of_node, "vop");
if (IS_ERR(pp->rstc_vop)) {
ret = PTR_ERR(pp->rstc_vop);
dev_err(dev, "failed to get vop reset: %d\n", ret);
return ret;
}
pp->base.funcs = &rk628_post_process_bridge_funcs;
pp->base.of_node = dev->of_node;
drm_bridge_add(&pp->base);
return 0;
}
static int rk628_post_process_remove(struct platform_device *pdev)
{
struct rk628_post_process *pp = platform_get_drvdata(pdev);
drm_bridge_remove(&pp->base);
return 0;
}
static const struct of_device_id rk628_post_process_of_match[] = {
{ .compatible = "rockchip,rk628-post-process", },
{},
};
MODULE_DEVICE_TABLE(of, rk628_post_process_of_match);
static struct platform_driver rk628_post_process_driver = {
.driver = {
.name = "rk628-post-process",
.of_match_table = of_match_ptr(rk628_post_process_of_match),
},
.probe = rk628_post_process_probe,
.remove = rk628_post_process_remove,
};
module_platform_driver(rk628_post_process_driver);
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK628 Post Process driver");
MODULE_LICENSE("GPL v2");

203
drivers/gpu/drm/rockchip/rk628/rk628_rgb.c Normal file
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
*
* Author: Wyon Bi <bivvy.bi@rock-chips.com>
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include <linux/mfd/rk628.h>
#include <linux/phy/phy.h>
#include <drm/drmP.h>
#include <drm/drm_of.h>
#include <drm/drm_atomic.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_panel.h>
#include <video/of_display_timing.h>
#include <video/videomode.h>
struct rk628_rgb {
struct drm_bridge base;
struct drm_connector connector;
struct drm_display_mode mode;
struct drm_panel *panel;
struct device *dev;
struct regmap *grf;
struct rk628 *parent;
};
static inline struct rk628_rgb *bridge_to_rgb(struct drm_bridge *b)
{
return container_of(b, struct rk628_rgb, base);
}
static inline struct rk628_rgb *connector_to_rgb(struct drm_connector *c)
{
return container_of(c, struct rk628_rgb, connector);
}
static struct drm_encoder *
rk628_rgb_connector_best_encoder(struct drm_connector *connector)
{
struct rk628_rgb *rgb = connector_to_rgb(connector);
return rgb->base.encoder;
}
static int rk628_rgb_connector_get_modes(struct drm_connector *connector)
{
struct rk628_rgb *rgb = connector_to_rgb(connector);
return drm_panel_get_modes(rgb->panel);
}
static const struct drm_connector_helper_funcs
rk628_rgb_connector_helper_funcs = {
.get_modes = rk628_rgb_connector_get_modes,
.best_encoder = rk628_rgb_connector_best_encoder,
};
static void rk628_rgb_connector_destroy(struct drm_connector *connector)
{
struct rk628_rgb *rgb = connector_to_rgb(connector);
drm_panel_detach(rgb->panel);
drm_connector_cleanup(connector);
}
static const struct drm_connector_funcs rk628_rgb_connector_funcs = {
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = rk628_rgb_connector_destroy,
.reset = drm_atomic_helper_connector_reset,
.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
static void rk628_rgb_bridge_enable(struct drm_bridge *bridge)
{
struct rk628_rgb *rgb = bridge_to_rgb(bridge);
regmap_update_bits(rgb->grf, GRF_SYSTEM_CON0,
SW_BT_DATA_OEN_MASK | SW_OUTPUT_MODE_MASK,
SW_OUTPUT_MODE(OUTPUT_MODE_RGB));
drm_panel_prepare(rgb->panel);
drm_panel_enable(rgb->panel);
}
static void rk628_rgb_bridge_disable(struct drm_bridge *bridge)
{
struct rk628_rgb *rgb = bridge_to_rgb(bridge);
drm_panel_disable(rgb->panel);
drm_panel_unprepare(rgb->panel);
}
static int rk628_rgb_bridge_attach(struct drm_bridge *bridge)
{
struct rk628_rgb *rgb = bridge_to_rgb(bridge);
struct drm_connector *connector = &rgb->connector;
struct drm_device *drm = bridge->dev;
int ret;
ret = drm_connector_init(drm, connector, &rk628_rgb_connector_funcs,
DRM_MODE_CONNECTOR_DPI);
if (ret) {
dev_err(rgb->dev, "Failed to initialize connector with drm\n");
return ret;
}
drm_connector_helper_add(connector, &rk628_rgb_connector_helper_funcs);
drm_connector_attach_encoder(connector, bridge->encoder);
ret = drm_panel_attach(rgb->panel, connector);
if (ret) {
dev_err(rgb->dev, "Failed to attach panel\n");
return ret;
}
return 0;
}
static void rk628_rgb_bridge_mode_set(struct drm_bridge *bridge,
struct drm_display_mode *mode,
struct drm_display_mode *adj)
{
struct rk628_rgb *rgb = bridge_to_rgb(bridge);
drm_mode_copy(&rgb->mode, adj);
}
static const struct drm_bridge_funcs rk628_rgb_bridge_funcs = {
.attach = rk628_rgb_bridge_attach,
.enable = rk628_rgb_bridge_enable,
.disable = rk628_rgb_bridge_disable,
.mode_set = rk628_rgb_bridge_mode_set,
};
static int rk628_rgb_probe(struct platform_device *pdev)
{
struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
struct device *dev = &pdev->dev;
struct rk628_rgb *rgb;
int ret;
if (!of_device_is_available(dev->of_node))
return -ENODEV;
rgb = devm_kzalloc(dev, sizeof(*rgb), GFP_KERNEL);
if (!rgb)
return -ENOMEM;
rgb->dev = dev;
rgb->parent = rk628;
rgb->grf = rk628->grf;
platform_set_drvdata(pdev, rgb);
ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
&rgb->panel, NULL);
if (ret)
return ret;
rgb->base.funcs = &rk628_rgb_bridge_funcs;
rgb->base.of_node = dev->of_node;
drm_bridge_add(&rgb->base);
return 0;
}
static int rk628_rgb_remove(struct platform_device *pdev)
{
struct rk628_rgb *rgb = platform_get_drvdata(pdev);
drm_bridge_remove(&rgb->base);
return 0;
}
static const struct of_device_id rk628_rgb_of_match[] = {
{ .compatible = "rockchip,rk628-rgb", },
{},
};
MODULE_DEVICE_TABLE(of, rk628_rgb_of_match);
static struct platform_driver rk628_rgb_driver = {
.driver = {
.name = "rk628-rgb",
.of_match_table = of_match_ptr(rk628_rgb_of_match),
},
.probe = rk628_rgb_probe,
.remove = rk628_rgb_remove,
};
module_platform_driver(rk628_rgb_driver);
MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK628 RGB driver");
MODULE_LICENSE("GPL v2");