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vpp: init viu1 path for g12a

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PD#156734: G12A: vpp: init viu1 path for g12a

Change-Id: Ide96b364aa86638597e606c3b53401c84b7e201d
Signed-off-by: Brian Zhu <brian.zhu@amlogic.com>
This commit is contained in:
Brian Zhu
2018-02-24 13:02:45 +08:00
committed by Yixun Lan
parent 7d10644f53
commit e2dcb46d15
13 changed files with 1142 additions and 981 deletions
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27
arch/arm64/boot/dts/amlogic/g12a_pxp.dts
View File

@@ -140,6 +140,15 @@
reg = <0x0 0xff638000 0x0 0x2000>;
};
};
rdma{
compatible = "amlogic, meson, rdma";
dev_name = "amlogic-rdma";
status = "okay";
interrupts = <0 89 1>;
interrupt-names = "rdma";
};
ge2d {
compatible = "amlogic, ge2d-g12a";
dev_name = "ge2d";
@@ -154,6 +163,24 @@
"clk_ge2d_gate";
reg = <0x0 0xff940000 0x0 0x10000>;
};
amlvecm {
compatible = "amlogic, vecm";
dev_name = "aml_vecm";
status = "okay";
gamma_en = <0>;/*1:enabel ;0:disable*/
wb_en = <0>;/*1:enabel ;0:disable*/
cm_en = <0>;/*1:enabel ;0:disable*/
};
meson-amvideom {
compatible = "amlogic, amvideom";
dev_name = "amvideom";
status = "okay";
interrupts = <0 3 1>;
interrupt-names = "vsync";
};
meson-fb {
compatible = "amlogic, meson-g12a";
memory-region = <&logo_reserved>;

15
drivers/amlogic/media/common/rdma/rdma_mgr.c
View File

@@ -787,8 +787,9 @@ static int rdma_probe(struct platform_device *pdev)
info->rdma_ins[i].prev_trigger_type = 0;
info->rdma_ins[i].rdma_write_count = 0;
}
WRITE_MPEG_REG(RESET4_REGISTER,
(1 << 5));
WRITE_MPEG_REG(RESET4_REGISTER, (1 << 5));
#ifdef SKIP_OSD_CHANNEL
info->rdma_ins[3].used = 1; /* OSD driver uses this channel */
#endif
@@ -831,8 +832,8 @@ static int rdma_remove(struct platform_device *pdev)
static const struct of_device_id rdma_dt_match[] = {
{
.compatible = "amlogic, meson, rdma",
},
.compatible = "amlogic, meson, rdma",
},
{},
};
@@ -840,9 +841,9 @@ static struct platform_driver rdma_driver = {
.probe = rdma_probe,
.remove = rdma_remove,
.driver = {
.name = "amlogic-rdma",
.of_match_table = rdma_dt_match,
},
.name = "amlogic-rdma",
.of_match_table = rdma_dt_match,
},
};
static int __init amrdma_init(void)

6
drivers/amlogic/media/deinterlace/deinterlace.c
View File

@@ -374,6 +374,8 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr, unsigned int val,
unsigned int DI_POST_REG_RD(unsigned int addr)
{
if (IS_ERR_OR_NULL(de_devp))
return 0;
if (de_devp->flags & DI_SUSPEND_FLAG) {
pr_err("[DI] REG 0x%x access prohibited.\n", addr);
return 0;
@@ -384,6 +386,8 @@ EXPORT_SYMBOL(DI_POST_REG_RD);
int DI_POST_WR_REG_BITS(u32 adr, u32 val, u32 start, u32 len)
{
if (IS_ERR_OR_NULL(de_devp))
return 0;
if (de_devp->flags & DI_SUSPEND_FLAG) {
pr_err("[DI] REG 0x%x access prohibited.\n", adr);
return -1;
@@ -7042,6 +7046,7 @@ static int di_probe(struct platform_device *pdev)
}
de_devp = di_devp;
memset(di_devp, 0, sizeof(struct di_dev_s));
di_devp->flags |= DI_SUSPEND_FLAG;
cdev_init(&(di_devp->cdev), &di_fops);
di_devp->cdev.owner = THIS_MODULE;
cdev_add(&(di_devp->cdev), di_devno, DI_COUNT);
@@ -7100,6 +7105,7 @@ static int di_probe(struct platform_device *pdev)
di_get_vpu_clkb(&pdev->dev, di_devp);
clk_prepare_enable(di_devp->vpu_clkb);
}
di_devp->flags &= (~DI_SUSPEND_FLAG);
ret = of_property_read_u32(pdev->dev.of_node,
"buffer-size", &(di_devp->buffer_size));
if (ret)

4
drivers/amlogic/media/enhancement/amvecm/amvecm.c
View File

@@ -4246,6 +4246,8 @@ static int aml_vecm_probe(struct platform_device *pdev)
/* amvecm_vpp_mtx_debug(mtx_sel_dbg, 1);*/
} else if (is_meson_txhd_cpu())
vpp_set_10bit_datapath1();
else if (is_meson_g12a_cpu())
vpp_set_12bit_datapath_g12a();
memset(&vpp_hist_param.vpp_histgram[0],
0, sizeof(unsigned short) * 64);
/* box sdr_mode:auto, tv sdr_mode:off */
@@ -4274,7 +4276,7 @@ static int aml_vecm_probe(struct platform_device *pdev)
aml_vecm_dt_parse(pdev);
if (is_meson_gxm_cpu())
dolby_vision_init_receiver();
probe_ok = 1;
probe_ok = 0;/*temp mark for g12a bringup*/
pr_info("%s: ok\n", __func__);
return 0;

13
drivers/amlogic/media/enhancement/amvecm/arch/vpp_regs.h
View File

@@ -211,6 +211,19 @@
#define VD1_IF0_GEN_REG3 0x1aa7
#define VD2_IF0_GEN_REG3 0x1aa8
/*g12a new add reg*/
#define VD1_AFBCD0_MISC_CTRL 0x1a0a
#define VD2_AFBCD1_MISC_CTRL 0x1a0b
#define DOLBY_PATH_CTRL 0x1a0c
#define WR_BACK_MISC_CTRL 0x1a0d
#define VD1_BLEND_SRC_CTRL 0x1dfb
#define VD2_BLEND_SRC_CTRL 0x1dfc
#define OSD1_BLEND_SRC_CTRL 0x1dfd
#define OSD2_BLEND_SRC_CTRL 0x1dfe
#define G12_VD1_IF0_GEN_REG3 0x3216
#define G12_VD2_IF0_GEN_REG3 0x3236
#define VPP2_DUMMY_DATA 0x1900
#define VPP2_LINE_IN_LENGTH 0x1901

175
drivers/amlogic/media/enhancement/amvecm/bitdepth.c
View File

@@ -222,11 +222,17 @@ void vpp_extend_mode_osd2(bool mode)
/**/
void vpp_vd1_if_bits_mode(enum vd_if_bits_mode_e bits_mode)
{
WRITE_VPP_REG_BITS(VD1_IF0_GEN_REG3, (bits_mode & 0x3), 8, 2);
u32 reg = (is_meson_g12a_cpu() ?
G12_VD1_IF0_GEN_REG3 :
VD1_IF0_GEN_REG3);
WRITE_VPP_REG_BITS(reg, (bits_mode & 0x3), 8, 2);
}
void vpp_vd2_if_bits_mode(enum vd_if_bits_mode_e bits_mode)
{
WRITE_VPP_REG_BITS(VD2_IF0_GEN_REG3, (bits_mode & 0x3), 8, 2);
u32 reg = (is_meson_g12a_cpu() ?
G12_VD2_IF0_GEN_REG3 :
VD2_IF0_GEN_REG3);
WRITE_VPP_REG_BITS(reg, (bits_mode & 0x3), 8, 2);
}
void vpp_enable_dither(bool enable)
{
@@ -238,6 +244,155 @@ void vpp_dither_bits_comp_mode(bool mode)
WRITE_VPP_REG_BITS(VPP_DOLBY_CTRL, mode, 14, 1);
}
/*g12a new add begin*/
/*0:axird to vd1;1:axird to afbc1*/
void vpp_set_vd1_mux0(unsigned int flag)
{
WRITE_VPP_REG_BITS(VD1_AFBCD0_MISC_CTRL, flag, 12, 2);
}
/*0:axird to vd2;1:axird to afbc2*/
void vpp_set_vd2_mux0(unsigned int flag)
{
WRITE_VPP_REG_BITS(VD2_AFBCD1_MISC_CTRL, flag, 12, 2);
}
/*vd1 mif config:0:vd1_mif to vpp;1:use afbc_mif*/
void vpp_set_vd1_mux1(bool flag)
{
WRITE_VPP_REG_BITS(VD1_AFBCD0_MISC_CTRL, flag, 10, 1);
}
void vpp_set_vd2_mux1(bool flag)
{
WRITE_VPP_REG_BITS(VD2_AFBCD1_MISC_CTRL, flag, 10, 1);
}
/*0:vd1/afbc to vpp;1:vd1/afbc to di*/
void vpp_set_vd1_mux2(bool flag)
{
WRITE_VPP_REG_BITS(VD1_AFBCD0_MISC_CTRL, flag, 8, 1);
}
/*0:afbc1 to di;1:afbc2 to di*/
void vpp_set_vd2_mux2(bool flag)
{
WRITE_VPP_REG_BITS(VD2_AFBCD1_MISC_CTRL, flag, 8, 1);
}
/*0:afbc to vpp;1:afbc to di*/
void vpp_set_vd1_mux3(bool flag)
{
WRITE_VPP_REG_BITS(VD1_AFBCD0_MISC_CTRL, flag, 9, 1);
}
void vpp_set_vd2_mux3(bool flag)
{
WRITE_VPP_REG_BITS(VD2_AFBCD1_MISC_CTRL, flag, 9, 1);
}
/*0:afbc/vd1 to vd1;1:osd3 to vd1*/
void vpp_set_vd1_mux4(bool flag)
{
WRITE_VPP_REG_BITS(VD1_AFBCD0_MISC_CTRL, flag, 11, 1);
}
/*0:afbc1/vd2 to vd2;1:osd4 to vd2*/
void vpp_set_vd2_mux4(bool flag)
{
WRITE_VPP_REG_BITS(VD2_AFBCD1_MISC_CTRL, flag, 11, 1);
}
/*0:vd1 to dolby;2:vd1 to primel*/
void vpp_set_vd1_mux5(unsigned int flag)
{
WRITE_VPP_REG_BITS(VD1_AFBCD0_MISC_CTRL, flag, 14, 2);
}
/*0:afbc2 to vd2;2:osd4 to vd2*/
void vpp_set_vd2_mux5(bool flag)
{
WRITE_VPP_REG_BITS(VD2_AFBCD1_MISC_CTRL, flag, 14, 2);
}
/*blend src mux==>0:close;1:vd1;2:vd2:3:osd1;4:osd2*/
void vpp_set_vd1_preblend_mux(unsigned int flag)
{
WRITE_VPP_REG_BITS(VD1_BLEND_SRC_CTRL, flag, 0, 4);
}
/*blend src mux==>0:close;1:vd1;2:vd2:3:osd1;4:osd2*/
void vpp_set_vd1_postblend_mux(unsigned int flag)
{
WRITE_VPP_REG_BITS(VD1_BLEND_SRC_CTRL, flag, 8, 4);
}
/*if vpp_misc 0x1d26[7]=1 0x1dfb[16] must set 1*/
void vpp_set_vd1_postblend_en(bool flag)
{
WRITE_VPP_REG_BITS(VD1_BLEND_SRC_CTRL, flag, 16, 1);
}
/*blend src mux==>0:close;1:vd1;2:vd2:3:osd1;4:osd2*/
void vpp_set_vd2_preblend_mux(unsigned int flag)
{
WRITE_VPP_REG_BITS(VD2_BLEND_SRC_CTRL, flag, 0, 4);
}
/*blend src mux==>0:close;1:vd1;2:vd2:3:osd1;4:osd2*/
void vpp_set_vd2_postblend_mux(unsigned int flag)
{
WRITE_VPP_REG_BITS(VD2_BLEND_SRC_CTRL, flag, 8, 4);
}
void vpp_set_vd2_postblend_en(bool flag)
{
WRITE_VPP_REG_BITS(VD2_BLEND_SRC_CTRL, flag, 16, 1);
if (flag)
WRITE_VPP_REG_BITS(VD2_BLEND_SRC_CTRL, 1, 20, 1);
}
/*data ext mod==>0:data << 2;1:data << 0*/
void vpp_set_vd1_ext_mod(bool flag)
{
WRITE_VPP_REG_BITS(DOLBY_PATH_CTRL, flag, 4, 1);
}
/*vd1 dolby bypass==>0:no bypass;1:bypass*/
void vpp_set_vd1_bypass_dolby(bool flag)
{
WRITE_VPP_REG_BITS(DOLBY_PATH_CTRL, flag, 0, 1);
}
/*data ext mod==>0:data << 2;1:data << 0*/
void vpp_set_vd2_ext_mod(bool flag)
{
WRITE_VPP_REG_BITS(DOLBY_PATH_CTRL, flag, 5, 1);
}
/*vd2 dolby bypass==>0:no bypass;1:bypass*/
void vpp_set_vd2_bypass_dolby(bool flag)
{
WRITE_VPP_REG_BITS(DOLBY_PATH_CTRL, flag, 1, 1);
}
void vpp_set_12bit_datapath_g12a(void)
{
/*after this step vd1 output data is U10*/
vpp_vd1_if_bits_mode(BIT_MODE_10BIT_422);
/*after this step vd1 output data is U12,*/
vpp_set_vd1_ext_mod(0);
vpp_set_vd1_bypass_dolby(1);
if (is_meson_g12a_cpu()) {
/*vd1 mux config*/
vpp_set_vd1_mux0(0);
vpp_set_vd1_mux1(0);
vpp_set_vd1_mux4(0);
vpp_set_vd1_mux2(0);
vpp_set_vd1_mux5(0);
vpp_set_vd1_preblend_mux(1);
vpp_set_vd1_postblend_mux(1);
vpp_set_vd1_postblend_en(1);
vpp_set_vd2_preblend_mux(0);
vpp_set_vd2_postblend_mux(2);
vpp_set_vd2_postblend_en(0);
vpp_set_vd2_ext_mod(0);
vpp_set_vd2_bypass_dolby(1);
}
}
/*g12a new add end*/
void vpp_set_12bit_datapath1(void)
{
/*after this step output data is U10*/
@@ -401,6 +556,8 @@ void vpp_bitdepth_config(unsigned int bitdepth)
vpp_set_12bit_datapath1();
else if (bitdepth == 122)
vpp_set_12bit_datapath2();
else if (bitdepth == 123)
vpp_set_12bit_datapath_g12a();
else
vpp_set_datapath();
}
@@ -482,8 +639,18 @@ void vpp_datapath_status(void)
unsigned int chroma_coring_en, black_ext_en, bluestretch_en;
unsigned int vadj1_en, vadj2_en;
vd1_out_format = READ_VPP_REG_BITS(VD1_IF0_GEN_REG3, 8, 2);
vd2_out_format = READ_VPP_REG_BITS(VD2_IF0_GEN_REG3, 8, 2);
if (is_meson_g12a_cpu()) {
vd1_out_format =
READ_VPP_REG_BITS(G12_VD1_IF0_GEN_REG3, 8, 2);
vd2_out_format =
READ_VPP_REG_BITS(G12_VD2_IF0_GEN_REG3, 8, 2);
} else {
vd1_out_format =
READ_VPP_REG_BITS(VD1_IF0_GEN_REG3, 8, 2);
vd2_out_format =
READ_VPP_REG_BITS(VD2_IF0_GEN_REG3, 8, 2);
}
core1_ext_mode = READ_VPP_REG_BITS(VIU_MISC_CTRL1, 20, 1);
core1_bypass = READ_VPP_REG_BITS(VIU_MISC_CTRL1, 16, 1);
pre_blend_switch = READ_VPP_REG_BITS(VPP_DOLBY_CTRL, 0, 1);

1
drivers/amlogic/media/enhancement/amvecm/bitdepth.h
View File

@@ -52,6 +52,7 @@ extern void vpp_set_12bit_datapath1(void);
extern void vpp_set_12bit_datapath2(void);
extern void vpp_set_pre_s2u(enum data_conv_mode_e conv_mode);
extern void vpp_set_10bit_datapath1(void);
extern void vpp_set_12bit_datapath_g12a(void);
#endif

1247
drivers/amlogic/media/video_sink/video.c
View File

File diff suppressed because it is too large Load Diff

552
drivers/amlogic/media/video_sink/vpp.c
View File

@@ -60,6 +60,8 @@
#define VPP_SPEED_FACTOR 0x110ULL
#define SUPER_SCALER_V_FACTOR 100
#define PPS_FRAC_BITS 24
#define PPS_INT_BITS 4
const u32 vpp_filter_coefs_bicubic_sharp[] = {
3,
@@ -402,25 +404,23 @@ static int force_filter_mode = 1;
MODULE_PARM_DESC(force_filter_mode, "force_filter_mode");
module_param(force_filter_mode, int, 0664);
#endif
bool super_scaler;
static unsigned int sr_support;
static u32 sr_reg_offt;
static unsigned int super_debug;
module_param(super_debug, uint, 0664);
MODULE_PARM_DESC(super_debug, "super_debug");
unsigned int super_scaler = 1;
module_param(super_scaler, uint, 0664);
MODULE_PARM_DESC(super_scaler, "super_scaler");
static unsigned int scaler_path_sel;
static unsigned int scaler_path_sel = SCALER_PATH_MAX;
module_param(scaler_path_sel, uint, 0664);
MODULE_PARM_DESC(scaler_path_sel, "scaler_path_sel");
static unsigned int bypass_spscl0;
module_param(bypass_spscl0, uint, 0664);
static bool bypass_spscl0;
module_param(bypass_spscl0, bool, 0664);
MODULE_PARM_DESC(bypass_spscl0, "bypass_spscl0");
static unsigned int bypass_spscl1;
module_param(bypass_spscl1, uint, 0664);
static bool bypass_spscl1;
module_param(bypass_spscl1, bool, 0664);
MODULE_PARM_DESC(bypass_spscl1, "bypass_spscl1");
static unsigned int vert_scaler_filter = 0xff;
@@ -772,7 +772,7 @@ vpp_set_filters2(u32 process_3d_type, u32 width_in,
u32 vpp_flags,
struct vpp_frame_par_s *next_frame_par, struct vframe_s *vf)
{
u32 screen_width, screen_height;
u32 screen_width = 0, screen_height = 0;
s32 start, end;
s32 video_top, video_left, temp;
u32 video_width, video_height;
@@ -800,17 +800,15 @@ vpp_set_filters2(u32 process_3d_type, u32 width_in,
bool skip_policy_check = true;
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) {
if ((likely(w_in >
(video_source_crop_left + video_source_crop_right)))
&& (super_scaler == 0)) {
if (likely(w_in >
(video_source_crop_left + video_source_crop_right))) {
w_in -= video_source_crop_left;
w_in -= video_source_crop_right;
h_crop_enable = true;
}
if ((likely(h_in >
(video_source_crop_top + video_source_crop_bottom)))
&& (super_scaler == 0)) {
if (likely(h_in >
(video_source_crop_top + video_source_crop_bottom))) {
h_in -= video_source_crop_top;
h_in -= video_source_crop_bottom;
v_crop_enable = true;
@@ -830,11 +828,8 @@ vpp_set_filters2(u32 process_3d_type, u32 width_in,
v_crop_enable = true;
}
}
if (is_meson_txlx_cpu()) {
next_frame_par->vpp_postblend_out_width = vinfo->width;
next_frame_par->vpp_postblend_out_height = vinfo->height;
}
next_frame_par->video_input_w = w_in;
next_frame_par->video_input_h = h_in;
#ifndef TV_3D_FUNCTION_OPEN
next_frame_par->vscale_skip_count = 0;
next_frame_par->hscale_skip_count = 0;
@@ -915,22 +910,10 @@ RESTART:
video_height = osd_layer_height;
}
} else {
if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) &&
next_frame_par->supscl_path == sup0_pp_sp1_scpath) {
video_top = (video_layer_top >> next_frame_par->
supsc1_vert_ratio);
video_height = (video_layer_height >> next_frame_par->
supsc1_vert_ratio);
video_left = (video_layer_left >> next_frame_par->
supsc1_hori_ratio);
video_width = (video_layer_width >> next_frame_par->
supsc1_hori_ratio);
} else {
video_top = video_layer_top;
video_left = video_layer_left;
video_width = video_layer_width;
video_height = video_layer_height;
}
video_top = video_layer_top;
video_left = video_layer_left;
video_width = video_layer_width;
video_height = video_layer_height;
if ((video_top == 0) && (video_left == 0) && (video_width <= 1)
&& (video_height <= 1)) {
/* special case to do full screen display */
@@ -1580,7 +1563,7 @@ RESTART:
*VPP_SRSHARP0_CTRL:0x1d91
*[0]srsharp0 enable for sharpness module reg r/w
*[1]if sharpness is enable or vscaler is enable,must set to 1,
*sharpness1;reg can only to be w
*sharpness1;reg can only to be w on gxtvbb;which is fix after txl
*/
int vpp_set_super_scaler_regs(int scaler_path_sel,
int reg_srscl0_enable,
@@ -1599,9 +1582,12 @@ int vpp_set_super_scaler_regs(int scaler_path_sel,
int tmp_data = 0;
int tmp_data2 = 0;
unsigned int data_path_chose;
if (super_scaler == 0)
return 0;
/* top config */
tmp_data = READ_VCBUS_REG(VPP_SRSHARP0_CTRL);
tmp_data = VSYNC_RD_MPEG_REG(VPP_SRSHARP0_CTRL);
if (sr0_sr1_refresh) {
if (reg_srscl0_hsize > SUPER_CORE0_WIDTH_MAX) {
if (((tmp_data >> 1)&0x1) != 0)
@@ -1615,7 +1601,11 @@ int vpp_set_super_scaler_regs(int scaler_path_sel,
if ((tmp_data&0x1) != 1)
VSYNC_WR_MPEG_REG_BITS(VPP_SRSHARP0_CTRL, 1, 0, 1);
}
tmp_data = READ_VCBUS_REG(VPP_SRSHARP1_CTRL);
if (super_scaler == 0) {
VSYNC_WR_MPEG_REG(VPP_SRSHARP0_CTRL, 0);
VSYNC_WR_MPEG_REG(VPP_SRSHARP1_CTRL, 0);
}
tmp_data = VSYNC_RD_MPEG_REG(VPP_SRSHARP1_CTRL);
if (sr0_sr1_refresh) {
if (((tmp_data >> 1)&0x1) != 1)
VSYNC_WR_MPEG_REG_BITS(VPP_SRSHARP1_CTRL, 1, 1, 1);
@@ -1623,38 +1613,46 @@ int vpp_set_super_scaler_regs(int scaler_path_sel,
VSYNC_WR_MPEG_REG_BITS(VPP_SRSHARP1_CTRL, 1, 0, 1);
}
/* core0 config */
tmp_data = READ_VCBUS_REG(SRSHARP0_SHARP_SR2_CTRL);
tmp_data = VSYNC_RD_MPEG_REG(
SRSHARP0_SHARP_SR2_CTRL + sr_reg_offt);
if (sr0_sr1_refresh) {
if (((tmp_data >> 5)&0x1) != (reg_srscl0_vert_ratio&0x1))
VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SHARP_SR2_CTRL,
VSYNC_WR_MPEG_REG_BITS(
SRSHARP0_SHARP_SR2_CTRL + sr_reg_offt,
reg_srscl0_vert_ratio&0x1, 5, 1);
if (((tmp_data >> 4)&0x1) != (reg_srscl0_hori_ratio&0x1))
VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SHARP_SR2_CTRL,
VSYNC_WR_MPEG_REG_BITS(
SRSHARP0_SHARP_SR2_CTRL + sr_reg_offt,
reg_srscl0_hori_ratio&0x1, 4, 1);
if (reg_srscl0_hsize > SUPER_CORE0_WIDTH_MAX) {
if (((tmp_data >> 2)&0x1) != 0)
VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SHARP_SR2_CTRL,
VSYNC_WR_MPEG_REG_BITS(
SRSHARP0_SHARP_SR2_CTRL + sr_reg_offt,
0, 2, 1);
} else {
if (((tmp_data >> 2)&0x1) != 1)
VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SHARP_SR2_CTRL,
VSYNC_WR_MPEG_REG_BITS(
SRSHARP0_SHARP_SR2_CTRL + sr_reg_offt,
1, 2, 1);
}
if ((tmp_data & 0x1) == (reg_srscl0_hori_ratio&0x1))
VSYNC_WR_MPEG_REG_BITS(SRSHARP0_SHARP_SR2_CTRL,
VSYNC_WR_MPEG_REG_BITS(
SRSHARP0_SHARP_SR2_CTRL + sr_reg_offt,
((~(reg_srscl0_hori_ratio&0x1))&0x1), 0, 1);
}
/* core1 config */
tmp_data = sharpness1_sr2_ctrl_32d7;
/*
*if ((((tmp_data >> 5)&0x1) != (reg_srscl1_vert_ratio&0x1)) ||
*(((tmp_data >> 4)&0x1) != (reg_srscl1_hori_ratio&0x1)) ||
*((tmp_data & 0x1) == (reg_srscl1_hori_ratio&0x1)) ||
*(((tmp_data >> 2)&0x1) != 1)) {
*/
if (1) {/* modify for avoid reg not be write@20160505 */
if (is_meson_gxtvbb_cpu())
tmp_data = sharpness1_sr2_ctrl_32d7;
else
tmp_data = VSYNC_RD_MPEG_REG(
SRSHARP1_SHARP_SR2_CTRL + sr_reg_offt);
if (is_meson_gxtvbb_cpu() ||
(((tmp_data >> 5)&0x1) != (reg_srscl1_vert_ratio&0x1)) ||
(((tmp_data >> 4)&0x1) != (reg_srscl1_hori_ratio&0x1)) ||
((tmp_data & 0x1) == (reg_srscl1_hori_ratio&0x1)) ||
(((tmp_data >> 2)&0x1) != 1)) {
tmp_data = tmp_data & (~(1 << 5));
tmp_data = tmp_data & (~(1 << 4));
tmp_data = tmp_data & (~(1 << 2));
@@ -1664,7 +1662,9 @@ int vpp_set_super_scaler_regs(int scaler_path_sel,
tmp_data |= (1 << 2);
tmp_data |= (((~(reg_srscl1_hori_ratio&0x1))&0x1) << 0);
if (sr0_sr1_refresh) {
VSYNC_WR_MPEG_REG(SRSHARP1_SHARP_SR2_CTRL, tmp_data);
VSYNC_WR_MPEG_REG(
SRSHARP1_SHARP_SR2_CTRL + sr_reg_offt,
tmp_data);
sharpness1_sr2_ctrl_32d7 = tmp_data;
}
}
@@ -1672,92 +1672,115 @@ int vpp_set_super_scaler_regs(int scaler_path_sel,
/* size config */
tmp_data = ((reg_srscl0_hsize & 0x1fff) << 16) |
(reg_srscl0_vsize & 0x1fff);
tmp_data2 = READ_VCBUS_REG(SRSHARP0_SHARP_SR2_CTRL);
tmp_data2 = VSYNC_RD_MPEG_REG(
SRSHARP0_SHARP_SR2_CTRL + sr_reg_offt);
if (tmp_data != tmp_data2)
VSYNC_WR_MPEG_REG(SRSHARP0_SHARP_HVSIZE, tmp_data);
tmp_data = ((reg_srscl1_hsize & 0x1fff) << 16) |
(reg_srscl1_vsize & 0x1fff);
if (1) {/*(sharpness1_sr2_ctrl_3280 != tmp_data) {*/
VSYNC_WR_MPEG_REG(SRSHARP1_SHARP_HVSIZE, tmp_data);
sharpness1_sr2_ctrl_3280 = tmp_data;
if (sr_support & SUPER_CORE1_SUPPORT) {
if (get_cpu_type() != MESON_CPU_MAJOR_ID_GXTVBB)
tmp_data2 = VSYNC_RD_MPEG_REG(
SRSHARP1_SHARP_HVSIZE);
if (is_meson_gxtvbb_cpu() || (tmp_data != tmp_data2)) {
VSYNC_WR_MPEG_REG(
SRSHARP1_SHARP_HVSIZE, tmp_data);
if (is_meson_gxtvbb_cpu())
sharpness1_sr2_ctrl_3280 = tmp_data;
}
}
/*ve input size setting*/
tmp_data = ((reg_srscl1_hsize & 0x1fff) << 16) |
(reg_srscl1_vsize & 0x1fff);
tmp_data2 = READ_VCBUS_REG(VPP_VE_H_V_SIZE);
if (is_meson_txhd_cpu() || is_meson_g12a_cpu())
tmp_data = ((reg_srscl0_hsize & 0x1fff) << 16) |
(reg_srscl0_vsize & 0x1fff);
else
tmp_data = ((reg_srscl1_hsize & 0x1fff) << 16) |
(reg_srscl1_vsize & 0x1fff);
tmp_data2 = VSYNC_RD_MPEG_REG(VPP_VE_H_V_SIZE);
if (tmp_data != tmp_data2)
VSYNC_WR_MPEG_REG(VPP_VE_H_V_SIZE, tmp_data);
/*chroma blue stretch size setting*/
if (is_meson_txlx_cpu()) {
if (is_meson_txlx_cpu() || is_meson_txhd_cpu() || is_meson_g12a_cpu()) {
tmp_data = (((vpp_postblend_out_width & 0x1fff) << 16) |
(vpp_postblend_out_height & 0x1fff));
VSYNC_WR_MPEG_REG(VPP_OUT_H_V_SIZE, tmp_data);
} else {
if (scaler_path_sel == sup0_pp_sp1_scpath) {
if (scaler_path_sel == CORE0_PPS_CORE1) {
tmp_data = (((reg_srscl1_hsize & 0x1fff) <<
reg_srscl1_hori_ratio) << 16) |
((reg_srscl1_vsize & 0x1fff) <<
reg_srscl1_vert_ratio);
tmp_data2 = READ_VCBUS_REG(VPP_PSR_H_V_SIZE);
tmp_data2 = VSYNC_RD_MPEG_REG(VPP_PSR_H_V_SIZE);
if (tmp_data != tmp_data2)
VSYNC_WR_MPEG_REG(VPP_PSR_H_V_SIZE, tmp_data);
} else if (scaler_path_sel == sup0_pp_post_blender) {
} else if ((scaler_path_sel == CORE0_CORE1_PPS) ||
(scaler_path_sel == CORE1_BEFORE_PPS) ||
(scaler_path_sel == CORE1_AFTER_PPS)) {
tmp_data = ((reg_srscl1_hsize & 0x1fff) << 16) |
(reg_srscl1_vsize & 0x1fff);
tmp_data2 = READ_VCBUS_REG(VPP_PSR_H_V_SIZE);
tmp_data2 = VSYNC_RD_MPEG_REG(VPP_PSR_H_V_SIZE);
if (tmp_data != tmp_data2)
VSYNC_WR_MPEG_REG(VPP_PSR_H_V_SIZE, tmp_data);
}
}
/* path config */
tmp_data2 = (READ_VCBUS_REG(VPP_VE_ENABLE_CTRL) >> 5)&0x1;
if (tmp_data2 != scaler_path_sel)
VSYNC_WR_MPEG_REG_BITS(VPP_VE_ENABLE_CTRL,
scaler_path_sel, 5, 1);
if (is_meson_txhd_cpu())
data_path_chose = 6;
else
data_path_chose = 5;
if ((scaler_path_sel == CORE0_PPS_CORE1) ||
(scaler_path_sel == CORE1_BEFORE_PPS) ||
(scaler_path_sel == CORE0_BEFORE_PPS)) {
if (is_meson_g12a_cpu())
VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 1, 1, 1);
else
VSYNC_WR_MPEG_REG_BITS(VPP_VE_ENABLE_CTRL,
0, data_path_chose, 1);
} else {
if (is_meson_g12a_cpu())
VSYNC_WR_MPEG_REG_BITS(VPP_MISC, 0, 1, 1);
else
VSYNC_WR_MPEG_REG_BITS(VPP_VE_ENABLE_CTRL,
1, data_path_chose, 1);
}
return 0;
}
static void vpp_set_scaler(u32 process_3d_type, u32 src_width,
u32 src_height,
const struct vinfo_s *vinfo,
u32 vpp_flags,
struct vpp_frame_par_s *next_frame_par,
struct vframe_s *vf)
static void vpp_set_super_scaler(const struct vinfo_s *vinfo,
struct vpp_frame_par_s *next_frame_par)
{
unsigned int spsc1_h_out, spsc1_w_out;
unsigned int ppsc_h_in, ppsc_w_in;
unsigned int ppsc_h_out, ppsc_w_out;
unsigned int hor_sc_multiple_num, ver_sc_multiple_num;
bool h_crop_enable = false, v_crop_enable = false;
u32 width_out = vinfo->width;
u32 height_out = vinfo->height;
u32 width_out = next_frame_par->VPP_hsc_endp -
next_frame_par->VPP_hsc_startp + 1;
u32 height_out = next_frame_par->VPP_vsc_endp -
next_frame_par->VPP_vsc_startp + 1;
u32 src_width = next_frame_par->video_input_w;
u32 src_height = next_frame_par->video_input_h;
if (video_layer_width > 0 && video_layer_width <= vinfo->width
&& ((video_layer_width + video_layer_left) <= vinfo->width))
width_out = video_layer_width;
if (video_layer_height > 0 && video_layer_height <= vinfo->height
&& ((video_layer_height + video_layer_top) <= vinfo->height))
height_out = video_layer_height;
/*for sr adjust*/
vpp_super_scaler_support();
if ((likely(src_width >
(video_source_crop_left + video_source_crop_right)))
&& (super_scaler == 1)) {
src_width -= video_source_crop_left + video_source_crop_right;
h_crop_enable = true;
/*patch for width align 2*/
if (super_scaler && (width_out%2)) {
next_frame_par->VPP_hsc_endp++;
width_out++;
}
if ((likely(
src_height >
(video_source_crop_top + video_source_crop_bottom)))
&& (super_scaler == 1)) {
src_height -= video_source_crop_top + video_source_crop_bottom;
v_crop_enable = true;
/*patch for height align 2*/
if (super_scaler && (height_out%2)) {
next_frame_par->VPP_vsc_endp++;
height_out++;
}
hor_sc_multiple_num = width_out / src_width;
ver_sc_multiple_num = height_out*SUPER_SCALER_V_FACTOR / src_height;
hor_sc_multiple_num = (1 << PPS_FRAC_BITS) /
next_frame_par->vpp_filter.vpp_hsc_start_phase_step;
ver_sc_multiple_num = SUPER_SCALER_V_FACTOR*(1 << PPS_FRAC_BITS)/
next_frame_par->vpp_filter.vpp_vsc_start_phase_step;
/* just calcuate the enable sclaer module */
/*
@@ -1786,7 +1809,8 @@ static void vpp_set_scaler(u32 process_3d_type, u32 src_width,
next_frame_par->supsc1_vert_ratio = 0;
}
/* step2: judge core0&core1 horizontal enable or disable*/
if (hor_sc_multiple_num >= 2) {
if ((hor_sc_multiple_num >= 2) &&
(vpp_wide_mode != VIDEO_WIDEOPTION_NONLINEAR)) {
if ((src_width > SUPER_CORE0_WIDTH_MAX) ||
((src_width > SUPER_CORE0_WIDTH_MAX/2) &&
next_frame_par->supsc0_vert_ratio) ||
@@ -1803,11 +1827,6 @@ static void vpp_set_scaler(u32 process_3d_type, u32 src_width,
next_frame_par->supsc1_hori_ratio = 0;
else
next_frame_par->supsc1_hori_ratio = 1;
/* disble sp1 for this case */
if ((vpp_wide_mode == VIDEO_WIDEOPTION_NONLINEAR)
&& (next_frame_par->supscl_path
== sup0_pp_sp1_scpath))
next_frame_par->supsc1_hori_ratio = 0;
next_frame_par->supsc0_enable =
(next_frame_par->supsc0_hori_ratio ||
next_frame_par->supsc0_enable) ? 1 : 0;
@@ -1843,160 +1862,119 @@ static void vpp_set_scaler(u32 process_3d_type, u32 src_width,
next_frame_par->supsc0_vert_ratio = 0;
next_frame_par->supsc1_vert_ratio = 1;
}
if (bypass_spscl0) {
if (bypass_spscl0 || !(sr_support & SUPER_CORE0_SUPPORT)) {
next_frame_par->supsc0_enable = 0;
next_frame_par->supsc0_hori_ratio = 0;
next_frame_par->supsc0_vert_ratio = 0;
}
if (bypass_spscl1) {
if (bypass_spscl1 || !(sr_support & SUPER_CORE1_SUPPORT)) {
next_frame_par->supsc1_enable = 0;
next_frame_par->supsc1_hori_ratio = 0;
next_frame_par->supsc1_vert_ratio = 0;
}
next_frame_par->spsc0_h_in = src_height;
next_frame_par->spsc0_w_in = src_width;
if (super_debug)
pr_info(
"supsc0_hori=%d,supsc1_hori=%d,supsc0_v=%d,supsc1_v=%d\n",
next_frame_par->supsc0_hori_ratio,
next_frame_par->supsc1_hori_ratio,
next_frame_par->supsc0_vert_ratio,
next_frame_par->supsc1_vert_ratio);
/*
*select the scaler path:[core0 =>>
/* new add according to pq test @20170808 on gxlx*/
if (scaler_path_sel >= SCALER_PATH_MAX) {
if (is_meson_gxlx_cpu()) {
if (next_frame_par->supsc1_hori_ratio &&
next_frame_par->supsc1_vert_ratio)
next_frame_par->supscl_path = CORE1_BEFORE_PPS;
else
next_frame_par->supscl_path = CORE1_AFTER_PPS;
} else if (is_meson_txhd_cpu() || is_meson_g12a_cpu()) {
next_frame_par->supscl_path = CORE0_BEFORE_PPS;
} else
next_frame_par->supscl_path = CORE0_PPS_CORE1;
} else
next_frame_par->supscl_path = scaler_path_sel;
/* select the scaler path:[core0 =>>
*ppscaler =>> core1] or
*[core0 =>> ppscaler =>> postblender =>> core1]
*[core0 =>> ppscaler =>> postblender =>> core1]
*gxlx only have core1,so the path:[core1 ==> pps ==> postblend]
*or pps ==> core1 ==> postblend
*txhd only have core0,so the path:[core0 ==> pps ==> postblend]
*or pps ==> core0 ==> postblend
*/
ppsc_h_in = (next_frame_par->spsc0_h_in <<
next_frame_par->supsc0_vert_ratio);
ppsc_w_in = (next_frame_par->spsc0_w_in <<
next_frame_par->supsc0_hori_ratio);
spsc1_h_out = height_out;
spsc1_w_out = width_out;
ppsc_h_out =
(spsc1_h_out >> next_frame_par->supsc1_vert_ratio);
ppsc_w_out =
(spsc1_w_out >> next_frame_par->supsc1_hori_ratio);
next_frame_par->spsc1_h_in = ppsc_h_out;
next_frame_par->spsc1_w_in = ppsc_w_out;
vpp_set_filters2(process_3d_type, ppsc_w_in,
ppsc_h_in, ppsc_w_out, ppsc_h_out, vinfo,
vpp_flags, next_frame_par, vf);
if (next_frame_par->supscl_path == sup0_pp_sp1_scpath) {
next_frame_par->spsc1_h_in = next_frame_par->VPP_vsc_endp -
next_frame_par->VPP_vsc_startp + 1;
/*
*(ppsc_h_in<<18)/
*(next_frame_par->vpp_filter.vpp_vsc_start_phase_step>>6);
*/
next_frame_par->spsc1_w_in = next_frame_par->VPP_hsc_endp -
next_frame_par->VPP_hsc_startp + 1;
/*
*(ppsc_w_in<<18)/
*(next_frame_par->vpp_filter.vpp_hsc_start_phase_step>>6);
*/
if (next_frame_par->supscl_path == CORE0_AFTER_PPS) {
next_frame_par->spsc0_h_in =
height_out >> next_frame_par->supsc0_vert_ratio;
next_frame_par->spsc0_w_in =
width_out >> next_frame_par->supsc0_hori_ratio;
} else {
next_frame_par->spsc0_h_in = src_height;
next_frame_par->spsc0_w_in = src_width;
}
if ((next_frame_par->supscl_path == CORE0_PPS_CORE1) ||
(next_frame_par->supscl_path == CORE0_CORE1_PPS) ||
(next_frame_par->supscl_path == CORE1_AFTER_PPS) ||
(next_frame_par->supscl_path == CORE0_BEFORE_PPS)) {
next_frame_par->spsc1_h_in =
(height_out >> next_frame_par->supsc1_vert_ratio);
next_frame_par->spsc1_w_in =
(width_out >> next_frame_par->supsc1_hori_ratio);
} else if (next_frame_par->supscl_path == CORE1_BEFORE_PPS) {
next_frame_par->spsc1_h_in = src_height;
next_frame_par->spsc1_w_in = src_width;
} else if (next_frame_par->supscl_path == CORE0_AFTER_PPS) {
next_frame_par->spsc1_h_in =
(height_out >> next_frame_par->supsc0_vert_ratio);
next_frame_par->spsc1_w_in =
(width_out >> next_frame_par->supsc0_hori_ratio);
} else {
next_frame_par->spsc1_h_in = height_out;
next_frame_par->spsc1_w_in = width_out;
}
/*recalc phase step and pps input&output size param*/
/*phase*/
if (next_frame_par->supsc0_hori_ratio) {
next_frame_par->vpp_filter.vpp_hsc_start_phase_step <<= 1;
next_frame_par->vpp_filter.vpp_hf_start_phase_step <<= 1;
}
if (next_frame_par->supsc1_hori_ratio) {
next_frame_par->vpp_filter.vpp_hsc_start_phase_step <<= 1;
next_frame_par->vpp_filter.vpp_hf_start_phase_step <<= 1;
}
if (next_frame_par->supsc0_vert_ratio)
next_frame_par->vpp_filter.vpp_vsc_start_phase_step <<= 1;
if (next_frame_par->supsc1_vert_ratio)
next_frame_par->vpp_filter.vpp_vsc_start_phase_step <<= 1;
/*pps input size*/
if (((next_frame_par->supscl_path == CORE0_PPS_CORE1) ||
(next_frame_par->supscl_path == CORE0_CORE1_PPS) ||
(next_frame_par->supscl_path == CORE0_BEFORE_PPS))) {
next_frame_par->VPP_line_in_length_ <<=
next_frame_par->supsc0_hori_ratio;
next_frame_par->VPP_pic_in_height_ <<=
next_frame_par->supsc0_vert_ratio;
}
if (((next_frame_par->supscl_path == CORE0_CORE1_PPS) ||
(next_frame_par->supscl_path == CORE1_BEFORE_PPS))) {
next_frame_par->VPP_line_in_length_ <<=
next_frame_par->supsc1_hori_ratio;
next_frame_par->VPP_pic_in_height_ <<=
next_frame_par->supsc1_vert_ratio;
}
/*
*vpp_set_super_sclaer_regs(next_frame_par->supscl_path,
*next_frame_par->supsc0_enable,
*next_frame_par->spsc0_w_in,
*next_frame_par->spsc0_h_in,
*next_frame_par->supsc0_hori_ratio,
*next_frame_par->supsc0_vert_ratio,
*next_frame_par->supsc1_enable,
*next_frame_par->spsc1_w_in,
*next_frame_par->spsc1_h_in,
*next_frame_par->supsc1_hori_ratio,
*next_frame_par->supsc1_vert_ratio);
*/
if (super_debug) {
pr_info
("ppsc_w_in=%u, ppsc_h_in=%u, ppsc_w_out=%u, ppsc_h_out=%u.\n",
ppsc_w_in, ppsc_h_in, ppsc_w_out, ppsc_h_out);
pr_info("spsc0_w_in=%u, spsc0_h_in=%u, spsc1_w_in=%u, spsc1_h_in=%u.\n",
next_frame_par->spsc0_w_in, next_frame_par->spsc0_h_in,
next_frame_par->spsc1_w_in, next_frame_par->spsc1_h_in);
next_frame_par->spsc0_w_in, next_frame_par->spsc0_h_in,
next_frame_par->spsc1_w_in, next_frame_par->spsc1_h_in);
pr_info("supsc0_hori=%d,supsc1_hori=%d,supsc0_v=%d,supsc1_v=%d\n",
next_frame_par->supsc0_hori_ratio,
next_frame_par->supsc1_hori_ratio,
next_frame_par->supsc0_vert_ratio,
next_frame_par->supsc1_vert_ratio);
pr_info("VPP_hd_start_lines= %d,%d,%d,%d, %d,%d,%d,%d, %d,%d\n",
next_frame_par->VPP_hd_start_lines_,
next_frame_par->VPP_hd_end_lines_,
next_frame_par->VPP_vd_start_lines_,
next_frame_par->VPP_vd_end_lines_,
next_frame_par->VPP_hsc_startp,
next_frame_par->VPP_hsc_endp,
next_frame_par->VPP_hsc_linear_startp,
next_frame_par->VPP_hsc_linear_endp,
next_frame_par->VPP_vsc_startp,
next_frame_par->VPP_vsc_endp);
}
/*
*vpp_set_ppsclaer(src_width,src_height,ppsc_w_in,
* ppsc_h_in,vinfo,vpp_flags,next_frame_par);
* cause the next_frame_par amlost were set at ppsclaer,
*and new supper scaler maybe need to change the param .
*/
if ((next_frame_par->supscl_path == sup0_pp_post_blender)
&& (next_frame_par->supsc1_enable)) {
next_frame_par->VPP_hd_start_lines_ >>=
next_frame_par->supsc1_hori_ratio;
next_frame_par->VPP_hd_end_lines_ >>=
next_frame_par->supsc1_hori_ratio;
next_frame_par->VPP_vd_start_lines_ >>=
next_frame_par->supsc1_vert_ratio;
next_frame_par->VPP_vd_end_lines_ >>=
next_frame_par->supsc1_vert_ratio;
}
if (next_frame_par->supsc0_enable) {
/* zoom out the under parm because*/
/*the ppscaler according to the parm that zoom in. */
next_frame_par->VPP_hd_start_lines_ >>=
next_frame_par->supsc0_hori_ratio;
next_frame_par->VPP_hd_end_lines_ >>=
next_frame_par->supsc0_hori_ratio;
next_frame_par->VPP_vd_start_lines_ >>=
next_frame_par->supsc0_vert_ratio;
next_frame_par->VPP_vd_end_lines_ >>=
next_frame_par->supsc0_vert_ratio;
}
if (next_frame_par->supscl_path == sup0_pp_sp1_scpath) {
/* zoom in the under parm because super scaler1 is open */
next_frame_par->VPP_hsc_startp <<=
next_frame_par->supsc1_hori_ratio;
next_frame_par->VPP_hsc_endp = (next_frame_par->VPP_hsc_endp <<
next_frame_par->supsc1_hori_ratio) +
next_frame_par->supsc1_hori_ratio;
next_frame_par->VPP_hsc_linear_startp =
next_frame_par->VPP_hsc_linear_startp <<
next_frame_par->supsc1_hori_ratio;
next_frame_par->VPP_hsc_linear_endp =
(next_frame_par->VPP_hsc_linear_endp <<
next_frame_par->supsc1_hori_ratio) +
next_frame_par->supsc1_hori_ratio;
next_frame_par->VPP_vsc_startp <<=
next_frame_par->supsc1_vert_ratio;
next_frame_par->VPP_vsc_endp =
(next_frame_par->VPP_vsc_endp <<
next_frame_par->supsc1_vert_ratio) +
next_frame_par->supsc1_vert_ratio;
}
if ((vpp_wide_mode == VIDEO_WIDEOPTION_NONLINEAR) &&
(next_frame_par->VPP_hsc_endp >
next_frame_par->VPP_hsc_startp)) {
s32 start, end;
struct vppfilter_mode_s *filter =
&next_frame_par->vpp_filter;
start = next_frame_par->VPP_hsc_startp;
end = next_frame_par->VPP_hsc_endp;
calculate_non_linear_ratio(
(filter->vpp_hsc_start_phase_step >> 6),
end - start,
next_frame_par);
next_frame_par->VPP_hsc_linear_startp =
next_frame_par->VPP_hsc_linear_endp = (start + end) / 2;
}
if (h_crop_enable) {
next_frame_par->VPP_hd_start_lines_ += video_source_crop_left;
next_frame_par->VPP_hd_end_lines_ += video_source_crop_left;
}
if (v_crop_enable) {
next_frame_par->VPP_vd_start_lines_ += video_source_crop_top;
next_frame_par->VPP_vd_end_lines_ += video_source_crop_top;
}
}
#ifdef TV_3D_FUNCTION_OPEN
void get_vpp_3d_mode(u32 process_3d_type, u32 trans_fmt, u32 *vpp_3d_mode)
{
@@ -2314,51 +2292,11 @@ vpp_set_filters(u32 process_3d_type, u32 wide_mode,
next_frame_par->VPP_post_blend_vd_v_end_ = vinfo->field_height - 1;
next_frame_par->VPP_post_blend_vd_h_end_ = vinfo->width - 1;
next_frame_par->VPP_post_blend_h_size_ = vinfo->width;
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXTVBB) {
if (super_scaler &&
(vpp_wide_mode != VIDEO_WIDEOPTION_NORMAL_NOSCALEUP)
&& (!(vf->type & VIDTYPE_PIC))
&& ((video_layer_width + video_layer_left) <= vinfo->width)) {
next_frame_par->supscl_path = scaler_path_sel;
vpp_set_scaler(process_3d_type, src_width, src_height,
vinfo, vpp_flags, next_frame_par, vf);
} else {
next_frame_par->supsc0_enable = 0;
next_frame_par->supsc0_hori_ratio = 0;
next_frame_par->supsc0_vert_ratio = 0;
next_frame_par->supsc1_enable = 0;
next_frame_par->supsc1_hori_ratio = 0;
next_frame_par->supsc1_vert_ratio = 0;
next_frame_par->spsc0_w_in = src_width;
next_frame_par->spsc0_h_in = src_height;
next_frame_par->spsc1_w_in = vinfo->width;
next_frame_par->spsc1_h_in = vinfo->height;
vpp_set_filters2(process_3d_type, src_width,
src_height, vinfo->width,
vinfo->height, vinfo, vpp_flags,
next_frame_par, vf);
}
if (super_debug)
pr_info("VPP_hd_start_lines= %d,%d,%d,%d, %d,%d,%d,%d, %d,%d\n",
next_frame_par->VPP_hd_start_lines_,
next_frame_par->VPP_hd_end_lines_,
next_frame_par->VPP_vd_start_lines_,
next_frame_par->VPP_vd_end_lines_,
next_frame_par->VPP_hsc_startp,
next_frame_par->VPP_hsc_endp,
next_frame_par->VPP_hsc_linear_startp,
next_frame_par->VPP_hsc_linear_endp,
next_frame_par->VPP_vsc_startp,
next_frame_par->VPP_vsc_endp);
} else {
vpp_set_filters2(process_3d_type, src_width, src_height,
vinfo->width, vinfo->height,
vinfo, vpp_flags, next_frame_par, vf);
}
vpp_set_filters2(process_3d_type, src_width, src_height,
vinfo->width, vinfo->height,
vinfo, vpp_flags, next_frame_par, vf);
/*config super scaler after set next_frame_par is calc ok for pps*/
vpp_set_super_scaler(vinfo, next_frame_par);
}
void prot_get_parameter(u32 wide_mode,
@@ -2541,13 +2479,31 @@ void vpp_set_3d_scale(bool enable)
void vpp_super_scaler_support(void)
{
if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu() ||
is_meson_txlx_cpu())
super_scaler = 1;
if (is_meson_gxlx_cpu()) {
sr_support &= ~SUPER_CORE0_SUPPORT;
sr_support |= SUPER_CORE1_SUPPORT;
} else if (is_meson_txhd_cpu() || is_meson_g12a_cpu()) {
sr_support |= SUPER_CORE0_SUPPORT;
sr_support &= ~SUPER_CORE1_SUPPORT;
} else if (is_meson_gxtvbb_cpu() || is_meson_txl_cpu() ||
is_meson_txlx_cpu()) {
sr_support |= SUPER_CORE0_SUPPORT;
sr_support |= SUPER_CORE1_SUPPORT;
} else {
sr_support &= ~SUPER_CORE0_SUPPORT;
sr_support &= ~SUPER_CORE1_SUPPORT;
}
if (super_scaler == 0) {
sr_support &= ~SUPER_CORE0_SUPPORT;
sr_support &= ~SUPER_CORE1_SUPPORT;
}
scaler_path_sel = SCALER_PATH_MAX;
if (is_meson_g12a_cpu())
sr_reg_offt = 0xc00;
else
super_scaler = 0;
sr_reg_offt = 0;
}
/*for gxlx only have core1 which will affact pip line*/
void vpp_bypass_ratio_config(void)
{
if (is_meson_gxbb_cpu() || is_meson_gxl_cpu() ||

5
include/linux/amlogic/media/registers/regs/viu_regs.h
View File

@@ -207,5 +207,10 @@
#define VD2_IF0_GEN_REG3 0x1aa8
#define VD1_AFBCD0_MISC_CTRL 0x1a0a
#define VD2_AFBCD1_MISC_CTRL 0x1a0b
#define G12_VD1_IF0_GEN_REG3 0x3216
#define G12_VD2_IF0_GEN_REG3 0x3236
#endif

35
include/linux/amlogic/media/registers/regs/vpp_regs.h
View File

@@ -317,5 +317,40 @@
#define SRSHARP1_SHARP_PK_NR_ENABLE 0x32a7
#define SRSHARP1_SHARP_DNLP_EN 0x32c5
#define SRSHARP1_SHARP_SR2_CTRL 0x32d7
/* g12a vd2 pps */
#define VD2_SCALE_COEF_IDX 0x3943
#define VD2_SCALE_COEF 0x3944
#define VD2_VSC_REGION12_STARTP 0x3945
#define VD2_VSC_REGION34_STARTP 0x3946
#define VD2_VSC_REGION4_ENDP 0x3947
#define VD2_VSC_START_PHASE_STEP 0x3948
#define VD2_VSC_REGION0_PHASE_SLOPE 0x3949
#define VD2_VSC_REGION1_PHASE_SLOPE 0x394a
#define VD2_VSC_REGION3_PHASE_SLOPE 0x394b
#define VD2_VSC_REGION4_PHASE_SLOPE 0x394c
#define VD2_VSC_PHASE_CTRL 0x394d
#define VD2_VSC_INI_PHASE 0x394e
#define VD2_HSC_REGION12_STARTP 0x394f
#define VD2_HSC_REGION34_STARTP 0x3950
#define VD2_HSC_REGION4_ENDP 0x3951
#define VD2_HSC_START_PHASE_STEP 0x3952
#define VD2_HSC_REGION0_PHASE_SLOPE 0x3953
#define VD2_HSC_REGION1_PHASE_SLOPE 0x3954
#define VD2_HSC_REGION3_PHASE_SLOPE 0x3955
#define VD2_HSC_REGION4_PHASE_SLOPE 0x3956
#define VD2_HSC_PHASE_CTRL 0x3957
#define VD2_SC_MISC 0x3958
#define VD2_SCO_FIFO_CTRL 0x3959
#define VD2_HSC_PHASE_CTRL1 0x395a
#define VD2_HSC_INI_PAT_CTRL 0x395b
#define VD2_SC_GCLK_CTRL 0x395c
#define VPP_VD2_HDR_IN_SIZE 0x1df0
#define VD1_BLEND_SRC_CTRL 0x1dfb
#define VD2_BLEND_SRC_CTRL 0x1dfc
#define OSD1_BLEND_SRC_CTRL 0x1dfd
#define OSD2_BLEND_SRC_CTRL 0x1dfe
#endif

3
include/linux/amlogic/media/video_sink/video.h
View File

@@ -38,6 +38,7 @@ enum {
};
extern bool pre_scaler_en;
extern bool super_scaler;
#define VIDEO_NOTIFY_TRICK_WAIT 0x01
#define VIDEO_NOTIFY_PROVIDER_GET 0x02
#define VIDEO_NOTIFY_PROVIDER_PUT 0x04
@@ -267,4 +268,6 @@ int query_video_status(int type, int *value);
int get_video0_frame_info(struct vframe_s *vf);
int amvideo_notifier_call_chain(unsigned long val, void *v);
struct device *get_video_device(void);
extern unsigned int DI_POST_REG_RD(unsigned int addr);
extern int DI_POST_WR_REG_BITS(u32 adr, u32 val, u32 start, u32 len);
#endif /* VIDEO_H */

40
include/linux/amlogic/media/video_sink/vpp.h
View File

@@ -123,17 +123,17 @@ struct vpp_frame_par_s {
bool supsc0_enable;
bool supsc1_enable;
bool supsc0_hori_ratio;
bool supsc1_hori_ratio;
bool supsc0_vert_ratio;
bool supsc1_vert_ratio;
u32 supscl_path;
u32 supsc0_hori_ratio;
u32 supsc1_hori_ratio;
u32 supsc0_vert_ratio;
u32 supsc1_vert_ratio;
u32 spsc0_w_in;
u32 spsc0_h_in;
u32 spsc1_w_in;
u32 spsc1_h_in;
u32 vpp_postblend_out_width;
u32 vpp_postblend_out_height;
u32 video_input_w;
u32 video_input_h;
bool nocomp;
@@ -154,21 +154,31 @@ struct vpp_frame_par_s {
extern bool reverse;
#endif
extern bool platform_type;
extern unsigned int super_scaler;
enum select_scaler_path_e {
sup0_pp_sp1_scpath,
sup0_pp_post_blender,
CORE0_PPS_CORE1 = 0,
CORE0_CORE1_PPS,
/*gxlx only have core1,support below two mode*/
CORE1_BEFORE_PPS,
CORE1_AFTER_PPS,
/*txhd only have core0,support below two mode*/
CORE0_BEFORE_PPS,
CORE0_AFTER_PPS,
SCALER_PATH_MAX,
};
/*
* note from vlsi!!!
* if core0 v enable,core0 input width max=1024;
* if core0 v disable,core0 input width max=2048;
* if core1 v enable,core1 input width max=2048;
* if core1 v disable,core1 input width max=4096;
*/
* note from vlsi!!!
* if core0 v enable,core0 input width max=1024;
* if core0 v disable,core0 input width max=2048;
* if core1 v enable,core1 input width max=2048;
* if core1 v disable,core1 input width max=4096;
* gxlx only have core1,txhd/g12a only have core0
*/
#define SUPER_CORE0_WIDTH_MAX 2048
#define SUPER_CORE1_WIDTH_MAX 4096
#define SUPER_CORE0_SUPPORT (1 << 0)
#define SUPER_CORE1_SUPPORT (1 << 1)
#ifdef TV_3D_FUNCTION_OPEN