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clk: fix 32bit system compatibility issue

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PD#169833: clk: fix 32bit system compatibility issue

Change-Id: I4033611ab0863448deb66d7ec1d06e645919fdc6
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
This commit is contained in:
Shunzhou Jiang
2018-07-06 13:02:34 +08:00
committed by Yixun Lan
parent 02bf0c02c0
commit e39e646127
35 changed files with 631 additions and 452 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
drivers/amlogic/clk/axg/axg.c
View File

@@ -644,6 +644,7 @@ static struct clk_gate axg_spicc_1 = {
.flags = 0,
},
};
/* Everything Else (EE) domain gates */
static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
@@ -864,29 +865,43 @@ static void __init axg_clkc_init(struct device_node *np)
axg_clk_mplls[i]->base = clk_base;
/* Populate the base address for CPU clk */
axg_cpu_clk.mux.reg = clk_base + (u64)axg_cpu_clk.mux.reg;
axg_cpu_fixedpll_p00.reg = clk_base + (u64)axg_cpu_fixedpll_p00.reg;
axg_cpu_fixedpll_p01.reg = clk_base + (u64)axg_cpu_fixedpll_p01.reg;
axg_cpu_fixedpll_p10.reg = clk_base + (u64)axg_cpu_fixedpll_p10.reg;
axg_cpu_fixedpll_p11.reg = clk_base + (u64)axg_cpu_fixedpll_p11.reg;
axg_cpu_fixedpll_p0.reg = clk_base + (u64)axg_cpu_fixedpll_p0.reg;
axg_cpu_fixedpll_p1.reg = clk_base + (u64)axg_cpu_fixedpll_p1.reg;
axg_cpu_fixedpll_p.reg = clk_base + (u64)axg_cpu_fixedpll_p.reg;
axg_cpu_clk.mux.reg = clk_base
+ (unsigned long)axg_cpu_clk.mux.reg;
axg_cpu_fixedpll_p00.reg = clk_base
+ (unsigned long)axg_cpu_fixedpll_p00.reg;
axg_cpu_fixedpll_p01.reg = clk_base
+ (unsigned long)axg_cpu_fixedpll_p01.reg;
axg_cpu_fixedpll_p10.reg = clk_base
+ (unsigned long)axg_cpu_fixedpll_p10.reg;
axg_cpu_fixedpll_p11.reg = clk_base
+ (unsigned long)axg_cpu_fixedpll_p11.reg;
axg_cpu_fixedpll_p0.reg = clk_base
+ (unsigned long)axg_cpu_fixedpll_p0.reg;
axg_cpu_fixedpll_p1.reg = clk_base
+ (unsigned long)axg_cpu_fixedpll_p1.reg;
axg_cpu_fixedpll_p.reg = clk_base
+ (unsigned long)axg_cpu_fixedpll_p.reg;
/* Populate the base address for the MPEG clks */
axg_mpeg_clk_sel.reg = clk_base + (u64)axg_mpeg_clk_sel.reg;
axg_mpeg_clk_div.reg = clk_base + (u64)axg_mpeg_clk_div.reg;
axg_mpeg_clk_sel.reg = clk_base
+ (unsigned long)axg_mpeg_clk_sel.reg;
axg_mpeg_clk_div.reg = clk_base
+ (unsigned long)axg_mpeg_clk_div.reg;
axg_pcie_mux.reg = clk_base + (u64)axg_pcie_mux.reg;
axg_pcie_ref.reg = clk_base + (u64)axg_pcie_ref.reg;
axg_pcie_mux.reg = clk_base
+ (unsigned long)axg_pcie_mux.reg;
axg_pcie_ref.reg = clk_base
+ (unsigned long)axg_pcie_ref.reg;
axg_pcie_cml_en0.reg = clk_base + (u64)axg_pcie_cml_en0.reg;
axg_pcie_cml_en1.reg = clk_base + (u64)axg_pcie_cml_en1.reg;
axg_pcie_cml_en0.reg = clk_base
+ (unsigned long)axg_pcie_cml_en0.reg;
axg_pcie_cml_en1.reg = clk_base
+ (unsigned long)axg_pcie_cml_en1.reg;
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(axg_clk_gates); i++)
axg_clk_gates[i]->reg = clk_base +
(u64)axg_clk_gates[i]->reg;
(unsigned long)axg_clk_gates[i]->reg;
if (!clks) {

8
drivers/amlogic/clk/axg/axg_ao.c
View File

@@ -113,10 +113,10 @@ static void __init axg_aoclkc_init(struct device_node *np)
}
/* pr_debug("%s: iomap clk_base ok!", __func__); */
/* Populate the base address for ao clk */
aoclk81.reg = ao_clk_base + (u64)aoclk81.reg;
axg_saradc_mux.reg = ao_clk_base + (u64)axg_saradc_mux.reg;
axg_saradc_div.reg = ao_clk_base + (u64)axg_saradc_div.reg;
axg_saradc_gate.reg = ao_clk_base + (u64)axg_saradc_gate.reg;
aoclk81.reg = ao_clk_base + (unsigned long)aoclk81.reg;
axg_saradc_mux.reg = ao_clk_base + (unsigned long)axg_saradc_mux.reg;
axg_saradc_div.reg = ao_clk_base + (unsigned long)axg_saradc_div.reg;
axg_saradc_gate.reg = ao_clk_base + (unsigned long)axg_saradc_gate.reg;
if (!clks) {
clks = kzalloc(NR_CLKS*sizeof(struct clk *), GFP_KERNEL);

64
drivers/amlogic/clk/axg/axg_clk-pll.c
View File

@@ -42,7 +42,7 @@
#include <linux/amlogic/cpu_version.h>
#include <dt-bindings/clock/amlogic,axg-clkc.h>
#ifdef CONFIG_ARM64
#if (defined CONFIG_ARM64) || (defined CONFIG_ARM64_A32)
#include "../clkc.h"
#else
#include "m8b/clkc.h"
@@ -82,7 +82,7 @@ static unsigned long meson_axg_pll_recalc_rate(struct clk_hw *hw,
{
struct meson_clk_pll *pll = to_meson_clk_pll(hw);
struct parm *p;
unsigned long parent_rate_mhz = parent_rate;
u64 parent_rate_mhz = parent_rate;
unsigned long rate_mhz;
u16 n, m, frac = 0, od, od2 = 0;
u32 reg;
@@ -207,25 +207,42 @@ static int meson_axg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
void *cntlbase = pll->base + p->reg_off;
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
writel(AXG_PCIE_PLL_CNTL, cntlbase + (u64)(0*4));
writel(AXG_PCIE_PLL_CNTL1, cntlbase + (u64)(1*4));
writel(AXG_PCIE_PLL_CNTL2, cntlbase + (u64)(2*4));
writel(AXG_PCIE_PLL_CNTL3, cntlbase + (u64)(3*4));
writel(AXG_PCIE_PLL_CNTL4, cntlbase + (u64)(4*4));
writel(AXG_PCIE_PLL_CNTL5, cntlbase + (u64)(5*4));
writel(AXG_PCIE_PLL_CNTL6, cntlbase + (u64)(6*4));
writel(AXG_PCIE_PLL_CNTL,
cntlbase + (unsigned long)(0*4));
writel(AXG_PCIE_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(AXG_PCIE_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(AXG_PCIE_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(AXG_PCIE_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(AXG_PCIE_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(AXG_PCIE_PLL_CNTL6,
cntlbase + (unsigned long)(6*4));
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
writel(AXG_HIFI_PLL_CNTL1, cntlbase + (u64)6*4);
writel(AXG_HIFI_PLL_CNTL2, cntlbase + (u64)1*4);
writel(AXG_HIFI_PLL_CNTL3, cntlbase + (u64)2*4);
writel(AXG_HIFI_PLL_CNTL4, cntlbase + (u64)3*4);
writel(AXG_HIFI_PLL_CNTL5, cntlbase + (u64)4*4);
writel(AXG_HIFI_PLL_CNTL1,
cntlbase + (unsigned long)(6*4));
writel(AXG_HIFI_PLL_CNTL2,
cntlbase + (unsigned long)(1*4));
writel(AXG_HIFI_PLL_CNTL3,
cntlbase + (unsigned long)(2*4));
writel(AXG_HIFI_PLL_CNTL4,
cntlbase + (unsigned long)(3*4));
writel(AXG_HIFI_PLL_CNTL5,
cntlbase + (unsigned long)(4*4));
} else {
writel(GXL_GP0_CNTL1, cntlbase + (u64)6*4);
writel(GXL_GP0_CNTL2, cntlbase + (u64)1*4);
writel(GXL_GP0_CNTL3, cntlbase + (u64)2*4);
writel(GXL_GP0_CNTL4, cntlbase + (u64)3*4);
writel(GXL_GP0_CNTL5, cntlbase + (u64)4*4);
writel(GXL_GP0_CNTL1,
cntlbase + (unsigned long)(6*4));
writel(GXL_GP0_CNTL2,
cntlbase + (unsigned long)(1*4));
writel(GXL_GP0_CNTL3,
cntlbase + (unsigned long)(2*4));
writel(GXL_GP0_CNTL4,
cntlbase + (unsigned long)(3*4));
writel(GXL_GP0_CNTL5,
cntlbase + (unsigned long)(4*4));
}
reg = readl(pll->base + p->reg_off);
@@ -311,13 +328,16 @@ static int meson_axg_pll_enable(struct clk_hw *hw)
void *cntlbase = pll->base + p->reg_off;
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
if (readl(cntlbase + (u64)(6*4)) == AXG_PCIE_PLL_CNTL6)
if (readl(cntlbase + (unsigned long)(6*4))
== AXG_PCIE_PLL_CNTL6)
first_set = 0;
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
if (readl(cntlbase + (u64)(4*4)) == AXG_HIFI_PLL_CNTL5)
if (readl(cntlbase + (unsigned long)(4*4))
== AXG_HIFI_PLL_CNTL5)
first_set = 0;
} else {
if (readl(cntlbase + (u64)(4*4)) == GXL_GP0_CNTL5)
if (readl(cntlbase + (unsigned long)(4*4))
== GXL_GP0_CNTL5)
first_set = 0;
}
}

36
drivers/amlogic/clk/axg/axg_clk_media.c
View File

@@ -318,28 +318,28 @@ static struct clk_gate ge2d_gate = {
void axg_amlogic_init_media(void)
{
/* cts_dsi_meas_clk */
dsi_meas_mux.reg = clk_base + (u64)(dsi_meas_mux.reg);
dsi_meas_div.reg = clk_base + (u64)(dsi_meas_div.reg);
dsi_meas_gate.reg = clk_base + (u64)(dsi_meas_gate.reg);
dsi_meas_mux.reg = clk_base + (unsigned long)(dsi_meas_mux.reg);
dsi_meas_div.reg = clk_base + (unsigned long)(dsi_meas_div.reg);
dsi_meas_gate.reg = clk_base + (unsigned long)(dsi_meas_gate.reg);
/* cts_vpu_clk */
vpu_p0_mux.reg = clk_base + (u64)(vpu_p0_mux.reg);
vpu_p0_div.reg = clk_base + (u64)(vpu_p0_div.reg);
vpu_p0_gate.reg = clk_base + (u64)(vpu_p0_gate.reg);
vpu_p1_mux.reg = clk_base + (u64)(vpu_p1_mux.reg);
vpu_p1_div.reg = clk_base + (u64)(vpu_p1_div.reg);
vpu_p1_gate.reg = clk_base + (u64)(vpu_p1_gate.reg);
vpu_mux.reg = clk_base + (u64)(vpu_mux.reg);
vpu_p0_mux.reg = clk_base + (unsigned long)(vpu_p0_mux.reg);
vpu_p0_div.reg = clk_base + (unsigned long)(vpu_p0_div.reg);
vpu_p0_gate.reg = clk_base + (unsigned long)(vpu_p0_gate.reg);
vpu_p1_mux.reg = clk_base + (unsigned long)(vpu_p1_mux.reg);
vpu_p1_div.reg = clk_base + (unsigned long)(vpu_p1_div.reg);
vpu_p1_gate.reg = clk_base + (unsigned long)(vpu_p1_gate.reg);
vpu_mux.reg = clk_base + (unsigned long)(vpu_mux.reg);
/* cts_vapbclk */
vapb_p0_mux.reg = clk_base + (u64)(vapb_p0_mux.reg);
vapb_p0_div.reg = clk_base + (u64)(vapb_p0_div.reg);
vapb_p0_gate.reg = clk_base + (u64)(vapb_p0_gate.reg);
vapb_p1_mux.reg = clk_base + (u64)(vapb_p1_mux.reg);
vapb_p1_div.reg = clk_base + (u64)(vapb_p1_div.reg);
vapb_p1_gate.reg = clk_base + (u64)(vapb_p1_gate.reg);
vapb_mux.reg = clk_base + (u64)(vapb_mux.reg);
vapb_p0_mux.reg = clk_base + (unsigned long)(vapb_p0_mux.reg);
vapb_p0_div.reg = clk_base + (unsigned long)(vapb_p0_div.reg);
vapb_p0_gate.reg = clk_base + (unsigned long)(vapb_p0_gate.reg);
vapb_p1_mux.reg = clk_base + (unsigned long)(vapb_p1_mux.reg);
vapb_p1_div.reg = clk_base + (unsigned long)(vapb_p1_div.reg);
vapb_p1_gate.reg = clk_base + (unsigned long)(vapb_p1_gate.reg);
vapb_mux.reg = clk_base + (unsigned long)(vapb_mux.reg);
/* cts_ge2d_clk */
ge2d_gate.reg = clk_base + (u64)(ge2d_gate.reg);
ge2d_gate.reg = clk_base + (unsigned long)(ge2d_gate.reg);
clks[CLKID_DSI_MEAS_COMP] = clk_register_composite(NULL,
"dsi_meas_composite",

6
drivers/amlogic/clk/axg/axg_clk_misc.c
View File

@@ -84,9 +84,9 @@ void axg_amlogic_init_misc(void)
/* Populate base address for reg */
pr_info("%s: register amlogic axg misc clks\n", __func__);
spicc_mux.reg = clk_base + (u64)(spicc_mux.reg);
spicc_div.reg = clk_base + (u64)(spicc_div.reg);
spicc_gate.reg = clk_base + (u64)(spicc_gate.reg);
spicc_mux.reg = clk_base + (unsigned long)(spicc_mux.reg);
spicc_div.reg = clk_base + (unsigned long)(spicc_div.reg);
spicc_gate.reg = clk_base + (unsigned long)(spicc_gate.reg);
clks[CLKID_SPICC_COMP] = clk_register_composite(NULL,
"spicc_comp",

18
drivers/amlogic/clk/axg/axg_clk_sdemmc.c
View File

@@ -132,12 +132,18 @@ void axg_amlogic_init_sdemmc(void)
/* Populate base address for reg */
pr_info("%s: register amlogic sdemmc clk\n", __func__);
sd_emmc_p0_mux_B.reg = clk_base + (u64)(sd_emmc_p0_mux_B.reg);
sd_emmc_p0_div_B.reg = clk_base + (u64)(sd_emmc_p0_div_B.reg);
sd_emmc_p0_gate_B.reg = clk_base + (u64)(sd_emmc_p0_gate_B.reg);
sd_emmc_p0_mux_C.reg = clk_base + (u64)(sd_emmc_p0_mux_C.reg);
sd_emmc_p0_div_C.reg = clk_base + (u64)(sd_emmc_p0_div_C.reg);
sd_emmc_p0_gate_C.reg = clk_base + (u64)(sd_emmc_p0_gate_C.reg);
sd_emmc_p0_mux_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_mux_B.reg);
sd_emmc_p0_div_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_div_B.reg);
sd_emmc_p0_gate_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_gate_B.reg);
sd_emmc_p0_mux_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_mux_C.reg);
sd_emmc_p0_div_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_div_C.reg);
sd_emmc_p0_gate_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_gate_C.reg);
clks[CLKID_SD_EMMC_B_P0_COMP] = clk_register_composite(NULL,
"sd_emmc_p0_B_comp",

31
drivers/amlogic/clk/clk-mpll.c
View File

@@ -41,6 +41,7 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw,
struct parm *p;
unsigned long rate = 0;
unsigned long reg, sdm, n2;
uint64_t rate64 = parent_rate;
p = &mpll->sdm;
reg = readl(mpll->base + p->reg_off);
@@ -50,7 +51,13 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw,
reg = readl(mpll->base + p->reg_off);
n2 = PARM_GET(p->width, p->shift, reg);
rate = (parent_rate * SDM_MAX) / ((SDM_MAX * n2) + sdm);
if (n2 == 0 && sdm == 0) {
rate = rate64;
} else {
rate64 = rate64 * SDM_MAX;
do_div(rate64, ((SDM_MAX * n2) + sdm));
rate = rate64;
}
return rate;
}
@@ -77,6 +84,7 @@ static int mpll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long old_rate = 0;
unsigned long reg, old_sdm, old_n2, sdm, n2;
unsigned long flags = 0;
uint64_t rate64 = parent_rate;
if ((rate > MAX_RATE) || (rate < MIN_RATE)) {
pr_err("Err: can not set rate to %lu!\n", rate);
@@ -95,7 +103,9 @@ static int mpll_set_rate(struct clk_hw *hw, unsigned long rate,
reg = readl(mpll->base + p->reg_off);
old_n2 = PARM_GET(p->width, p->shift, reg);
old_rate = (parent_rate * SDM_MAX) / ((SDM_MAX * old_n2) + old_sdm);
rate64 = rate64 * SDM_MAX;
do_div(rate64, ((SDM_MAX * old_n2) + old_sdm));
old_rate = rate64;
pr_debug("%s: old_sdm: %lu old_n2: %lu old_rate: %lu\n", __func__,
old_sdm, old_n2, old_rate);
/*
@@ -103,8 +113,13 @@ static int mpll_set_rate(struct clk_hw *hw, unsigned long rate,
* return 0;
*/
/* calculate new n2 and sdm */
n2 = parent_rate / rate;
sdm = DIV_ROUND_UP((parent_rate - n2 * rate) * SDM_MAX, rate);
rate64 = parent_rate;
do_div(rate64, rate);
n2 = rate64;
rate64 = (parent_rate - n2 * rate) * SDM_MAX;
do_div(rate64, rate);
sdm = rate64;
pr_debug("%s: sdm: %lu n2: %lu rate: %lu\n", __func__, sdm, n2, rate);
/*if (old_n2 != n2 || old_sdm != sdm)*/ {
@@ -126,12 +141,14 @@ static int mpll_set_rate(struct clk_hw *hw, unsigned long rate,
writel(reg, mpll->base + p->reg_off);
/* mpll top misc for cpu after txlx */
if (mpll->top_misc_reg)
writel(readl(mpll->base + (u64)(mpll->top_misc_reg)) |
writel(readl(mpll->base
+ (unsigned long)(mpll->top_misc_reg)) |
(1<<mpll->top_misc_bit),
(mpll->base + (u64)(mpll->top_misc_reg)));
(mpll->base + (unsigned long)(mpll->top_misc_reg)));
udelay(100);
pr_debug("%s: mpll->base+mpll->top_misc_reg: 0x%x\n",
__func__, readl(mpll->base+(u64)mpll->top_misc_reg));
__func__, readl(mpll->base
+(unsigned long)mpll->top_misc_reg));
}
if (mpll->lock)

2
drivers/amlogic/clk/clk-mux.c
View File

@@ -25,7 +25,7 @@
#include <linux/slab.h>
#include <linux/string.h>
#ifdef CONFIG_ARM64
#if (defined CONFIG_ARM64) || (defined CONFIG_ARM64_A32)
#include "clkc.h"
#else
#include "m8b/clkc.h"

41
drivers/amlogic/clk/clk-pll.c
View File

@@ -40,7 +40,7 @@
#include <linux/string.h>
#include <linux/amlogic/cpu_version.h>
#ifdef CONFIG_ARM64
#if (defined CONFIG_ARM64) || (defined CONFIG_ARM64_A32)
#include "clkc.h"
#else
#include "m8b/clkc.h"
@@ -182,25 +182,38 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
if ((get_cpu_type() == MESON_CPU_MAJOR_ID_GXBB) ||
(get_cpu_type() == MESON_CPU_MAJOR_ID_GXTVBB)) {
writel(GXBB_GP0_CNTL2, cntlbase + (u64)1*4);
writel(GXBB_GP0_CNTL3, cntlbase + (u64)2*4);
writel(GXBB_GP0_CNTL4, cntlbase + (u64)3*4);
writel(GXBB_GP0_CNTL2,
cntlbase + (unsigned long)(1*4));
writel(GXBB_GP0_CNTL3,
cntlbase + (unsigned long)(2*4));
writel(GXBB_GP0_CNTL4,
cntlbase + (unsigned long)(3*4));
} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXL) {
writel(GXL_GP0_CNTL1, cntlbase + (u64)6*4);
writel(GXL_GP0_CNTL2, cntlbase + (u64)1*4);
writel(GXL_GP0_CNTL3, cntlbase + (u64)2*4);
writel(GXL_GP0_CNTL4, cntlbase + (u64)3*4);
writel(GXL_GP0_CNTL5, cntlbase + (u64)4*4);
writel(GXL_GP0_CNTL1,
cntlbase + (unsigned long)(6*4));
writel(GXL_GP0_CNTL2,
cntlbase + (unsigned long)(1*4));
writel(GXL_GP0_CNTL3,
cntlbase + (unsigned long)(2*4));
writel(GXL_GP0_CNTL4,
cntlbase + (unsigned long)(3*4));
writel(GXL_GP0_CNTL5,
cntlbase + (unsigned long)(4*4));
reg = readl(pll->base + p->reg_off);
writel(((reg | (MESON_PLL_ENABLE)) &
(~MESON_PLL_RESET)), pll->base + p->reg_off);
} else if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TXLX) {
writel(GXL_GP0_CNTL1, cntlbase + (u64)6*4);
writel(GXL_GP0_CNTL2, cntlbase + (u64)1*4);
writel(GXL_GP0_CNTL3, cntlbase + (u64)2*4);
writel(GXL_GP0_CNTL4, cntlbase + (u64)3*4);
writel(TXLL_GP0_CNTL5, cntlbase + (u64)4*4);
writel(GXL_GP0_CNTL1,
cntlbase + (unsigned long)(6*4));
writel(GXL_GP0_CNTL2,
cntlbase + (unsigned long)(1*4));
writel(GXL_GP0_CNTL3,
cntlbase + (unsigned long)(2*4));
writel(GXL_GP0_CNTL4,
cntlbase + (unsigned long)(3*4));
writel(TXLL_GP0_CNTL5,
cntlbase + (unsigned long)(4*4));
reg = readl(pll->base + p->reg_off);
writel(((reg | (MESON_PLL_ENABLE)) &

4
drivers/amlogic/clk/clkc.h
View File

@@ -48,7 +48,7 @@ struct parm_fclk {
};
struct pll_rate_table {
unsigned long rate;
u64 rate;
u16 m;
u16 n;
u16 od;
@@ -57,7 +57,7 @@ struct pll_rate_table {
};
struct fclk_rate_table {
unsigned long rate;
u64 rate;
u16 premux;
u16 postmux;
u16 mux_div;

20
drivers/amlogic/clk/g12a/g12a.c
View File

@@ -873,24 +873,30 @@ static void __init g12a_clkc_init(struct device_node *np)
if (is_meson_g12b_cpu()) {
g12a_clk_hws[CLKID_CPU_CLK] = &g12b_cpu_clk1.mux.hw;
g12b_cpu_clk1.base = clk_base;
g12b_cpu_clk1.mux.reg = clk_base + (u64)g12b_cpu_clk1.mux.reg;
g12b_cpu_clk1.mux.reg = clk_base
+ (unsigned long)g12b_cpu_clk1.mux.reg;
} else {
g12a_cpu_clk.base = clk_base;
g12a_cpu_clk.mux.reg = clk_base + (u64)g12a_cpu_clk.mux.reg;
g12a_cpu_clk.mux.reg = clk_base
+ (unsigned long)g12a_cpu_clk.mux.reg;
}
g12a_cpu_fclk_p.reg = clk_base + (u64)g12a_cpu_fclk_p.reg;
g12a_cpu_fclk_p.reg = clk_base
+ (unsigned long)g12a_cpu_fclk_p.reg;
/* Populate the base address for the MPEG clks */
g12a_mpeg_clk_sel.reg = clk_base + (u64)g12a_mpeg_clk_sel.reg;
g12a_mpeg_clk_div.reg = clk_base + (u64)g12a_mpeg_clk_div.reg;
g12a_mpeg_clk_sel.reg = clk_base
+ (unsigned long)g12a_mpeg_clk_sel.reg;
g12a_mpeg_clk_div.reg = clk_base
+ (unsigned long)g12a_mpeg_clk_div.reg;
g12a_12m_div.reg = clk_base + (u64)g12a_12m_div.reg;
g12a_12m_div.reg = clk_base
+ (unsigned long)g12a_12m_div.reg;
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(g12a_clk_gates); i++)
g12a_clk_gates[i]->reg = clk_base +
(u64)g12a_clk_gates[i]->reg;
(unsigned long)g12a_clk_gates[i]->reg;
if (!clks) {
clks = kzalloc(NR_CLKS*sizeof(struct clk *), GFP_KERNEL);

132
drivers/amlogic/clk/g12a/g12a.h
View File

@@ -44,7 +44,7 @@
#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
#define HHI_GCLK_SP_MPEG 0x154 /* 0x55 offset in data sheet */
#define HHI_GCLK_SP_MPEG 0x154 /* 0x55 offset in data sheet */
#define HHI_APICALGDC_CNTL 0x168 /* 0x5a offset in data sheet */
@@ -128,71 +128,71 @@
*clk_out = FDCO >> OD
*/
static const struct pll_rate_table g12a_pll_rate_table[] = {
PLL_RATE(24000000, 128, 1, 7), /*DCO=3072M*/
PLL_RATE(48000000, 128, 1, 6), /*DCO=3072M*/
PLL_RATE(96000000, 128, 1, 5), /*DCO=3072M*/
PLL_RATE(192000000, 128, 1, 4), /*DCO=3072M*/
PLL_RATE(312000000, 208, 1, 4), /*DCO=4992M*/
PLL_RATE(408000000, 136, 1, 3), /*DCO=3264M*/
PLL_RATE(600000000, 200, 1, 3), /*DCO=4800M*/
PLL_RATE(696000000, 232, 1, 3), /*DCO=5568M*/
PLL_RATE(792000000, 132, 1, 2), /*DCO=3168M*/
PLL_RATE(846000000, 141, 1, 2), /*DCO=3384M*/
PLL_RATE(912000000, 152, 1, 2), /*DCO=3648M*/
PLL_RATE(1008000000, 168, 1, 2), /*DCO=4032M*/
PLL_RATE(1104000000, 184, 1, 2), /*DCO=4416M*/
PLL_RATE(1200000000, 200, 1, 2), /*DCO=4800M*/
PLL_RATE(1296000000, 216, 1, 2), /*DCO=5184M*/
PLL_RATE(1398000000, 233, 1, 2), /*DCO=5592M*/
PLL_RATE(1494000000, 249, 1, 2), /*DCO=5976M*/
PLL_RATE(1512000000, 126, 1, 1), /*DCO=3024M*/
PLL_RATE(1608000000, 134, 1, 1), /*DCO=3216M*/
PLL_RATE(1704000000, 142, 1, 1), /*DCO=3408M*/
PLL_RATE(1800000000, 150, 1, 1), /*DCO=3600M*/
PLL_RATE(1896000000, 158, 1, 1), /*DCO=3792M*/
PLL_RATE(1908000000, 159, 1, 1), /*DCO=3816M*/
PLL_RATE(1920000000, 160, 1, 1), /*DCO=3840M*/
PLL_RATE(2016000000, 168, 1, 1), /*DCO=4032M*/
PLL_RATE(2100000000, 175, 1, 1), /*DCO=4200M*/
PLL_RATE(2196000000, 183, 1, 1), /*DCO=4392M*/
PLL_RATE(2292000000, 191, 1, 1), /*DCO=4584M*/
PLL_RATE(2400000000, 200, 1, 1), /*DCO=4800M*/
PLL_RATE(2496000000, 208, 1, 1), /*DCO=4992M*/
PLL_RATE(2592000000, 216, 1, 1), /*DCO=5184M*/
PLL_RATE(2700000000, 225, 1, 1), /*DCO=5400M*/
PLL_RATE(2796000000, 233, 1, 1), /*DCO=5592M*/
PLL_RATE(2892000000, 241, 1, 1), /*DCO=5784M*/
PLL_RATE(3000000000, 125, 1, 0), /*DCO=3000M*/
PLL_RATE(3096000000, 129, 1, 0), /*DCO=3096M*/
PLL_RATE(3192000000, 133, 1, 0), /*DCO=3192M*/
PLL_RATE(3288000000, 137, 1, 0), /*DCO=3288M*/
PLL_RATE(3408000000, 142, 1, 0), /*DCO=3408M*/
PLL_RATE(3504000000, 146, 1, 0), /*DCO=3504M*/
PLL_RATE(3600000000, 150, 1, 0), /*DCO=3600M*/
PLL_RATE(3696000000, 154, 1, 0), /*DCO=3696M*/
PLL_RATE(3792000000, 158, 1, 0), /*DCO=3792M*/
PLL_RATE(3888000000, 162, 1, 0), /*DCO=3888M*/
PLL_RATE(4008000000, 167, 1, 0), /*DCO=4008M*/
PLL_RATE(4104000000, 171, 1, 0), /*DCO=4104M*/
PLL_RATE(4200000000, 175, 1, 0), /*DCO=4200M*/
PLL_RATE(4296000000, 179, 1, 0), /*DCO=4296M*/
PLL_RATE(4392000000, 183, 1, 0), /*DCO=4392M*/
PLL_RATE(4488000000, 187, 1, 0), /*DCO=4488M*/
PLL_RATE(4608000000, 192, 1, 0), /*DCO=4608M*/
PLL_RATE(4704000000, 196, 1, 0), /*DCO=4704M*/
PLL_RATE(4800000000, 200, 1, 0), /*DCO=4800M*/
PLL_RATE(4896000000, 204, 1, 0), /*DCO=4896M*/
PLL_RATE(4992000000, 208, 1, 0), /*DCO=4992M*/
PLL_RATE(5088000000, 212, 1, 0), /*DCO=5088M*/
PLL_RATE(5208000000, 217, 1, 0), /*DCO=5208M*/
PLL_RATE(5304000000, 221, 1, 0), /*DCO=5304M*/
PLL_RATE(5400000000, 225, 1, 0), /*DCO=5400M*/
PLL_RATE(5496000000, 229, 1, 0), /*DCO=5496M*/
PLL_RATE(5592000000, 233, 1, 0), /*DCO=5592M*/
PLL_RATE(5688000000, 237, 1, 0), /*DCO=5688M*/
PLL_RATE(5808000000, 242, 1, 0), /*DCO=5808M*/
PLL_RATE(5904000000, 246, 1, 0), /*DCO=5904M*/
PLL_RATE(6000000000, 250, 1, 0), /*DCO=6000M*/
PLL_RATE(24000000ULL, 128, 1, 7), /*DCO=3072M*/
PLL_RATE(48000000ULL, 128, 1, 6), /*DCO=3072M*/
PLL_RATE(96000000ULL, 128, 1, 5), /*DCO=3072M*/
PLL_RATE(192000000ULL, 128, 1, 4), /*DCO=3072M*/
PLL_RATE(312000000ULL, 208, 1, 4), /*DCO=4992M*/
PLL_RATE(408000000ULL, 136, 1, 3), /*DCO=3264M*/
PLL_RATE(600000000ULL, 200, 1, 3), /*DCO=4800M*/
PLL_RATE(696000000ULL, 232, 1, 3), /*DCO=5568M*/
PLL_RATE(792000000ULL, 132, 1, 2), /*DCO=3168M*/
PLL_RATE(846000000ULL, 141, 1, 2), /*DCO=3384M*/
PLL_RATE(912000000ULL, 152, 1, 2), /*DCO=3648M*/
PLL_RATE(1008000000ULL, 168, 1, 2), /*DCO=4032M*/
PLL_RATE(1104000000ULL, 184, 1, 2), /*DCO=4416M*/
PLL_RATE(1200000000ULL, 200, 1, 2), /*DCO=4800M*/
PLL_RATE(1296000000ULL, 216, 1, 2), /*DCO=5184M*/
PLL_RATE(1398000000ULL, 233, 1, 2), /*DCO=5592M*/
PLL_RATE(1494000000ULL, 249, 1, 2), /*DCO=5976M*/
PLL_RATE(1512000000ULL, 126, 1, 1), /*DCO=3024M*/
PLL_RATE(1608000000ULL, 134, 1, 1), /*DCO=3216M*/
PLL_RATE(1704000000ULL, 142, 1, 1), /*DCO=3408M*/
PLL_RATE(1800000000ULL, 150, 1, 1), /*DCO=3600M*/
PLL_RATE(1896000000ULL, 158, 1, 1), /*DCO=3792M*/
PLL_RATE(1908000000ULL, 159, 1, 1), /*DCO=3816M*/
PLL_RATE(1920000000ULL, 160, 1, 1), /*DCO=3840M*/
PLL_RATE(2016000000ULL, 168, 1, 1), /*DCO=4032M*/
PLL_RATE(2100000000ULL, 175, 1, 1), /*DCO=4200M*/
PLL_RATE(2196000000ULL, 183, 1, 1), /*DCO=4392M*/
PLL_RATE(2292000000ULL, 191, 1, 1), /*DCO=4584M*/
PLL_RATE(2400000000ULL, 200, 1, 1), /*DCO=4800M*/
PLL_RATE(2496000000ULL, 208, 1, 1), /*DCO=4992M*/
PLL_RATE(2592000000ULL, 216, 1, 1), /*DCO=5184M*/
PLL_RATE(2700000000ULL, 225, 1, 1), /*DCO=5400M*/
PLL_RATE(2796000000ULL, 233, 1, 1), /*DCO=5592M*/
PLL_RATE(2892000000ULL, 241, 1, 1), /*DCO=5784M*/
PLL_RATE(3000000000ULL, 125, 1, 0), /*DCO=3000M*/
PLL_RATE(3096000000ULL, 129, 1, 0), /*DCO=3096M*/
PLL_RATE(3192000000ULL, 133, 1, 0), /*DCO=3192M*/
PLL_RATE(3288000000ULL, 137, 1, 0), /*DCO=3288M*/
PLL_RATE(3408000000ULL, 142, 1, 0), /*DCO=3408M*/
PLL_RATE(3504000000ULL, 146, 1, 0), /*DCO=3504M*/
PLL_RATE(3600000000ULL, 150, 1, 0), /*DCO=3600M*/
PLL_RATE(3696000000ULL, 154, 1, 0), /*DCO=3696M*/
PLL_RATE(3792000000ULL, 158, 1, 0), /*DCO=3792M*/
PLL_RATE(3888000000ULL, 162, 1, 0), /*DCO=3888M*/
PLL_RATE(4008000000ULL, 167, 1, 0), /*DCO=4008M*/
PLL_RATE(4104000000ULL, 171, 1, 0), /*DCO=4104M*/
PLL_RATE(4200000000ULL, 175, 1, 0), /*DCO=4200M*/
PLL_RATE(4296000000ULL, 179, 1, 0), /*DCO=4296M*/
PLL_RATE(4392000000ULL, 183, 1, 0), /*DCO=4392M*/
PLL_RATE(4488000000ULL, 187, 1, 0), /*DCO=4488M*/
PLL_RATE(4608000000ULL, 192, 1, 0), /*DCO=4608M*/
PLL_RATE(4704000000ULL, 196, 1, 0), /*DCO=4704M*/
PLL_RATE(4800000000ULL, 200, 1, 0), /*DCO=4800M*/
PLL_RATE(4896000000ULL, 204, 1, 0), /*DCO=4896M*/
PLL_RATE(4992000000ULL, 208, 1, 0), /*DCO=4992M*/
PLL_RATE(5088000000ULL, 212, 1, 0), /*DCO=5088M*/
PLL_RATE(5208000000ULL, 217, 1, 0), /*DCO=5208M*/
PLL_RATE(5304000000ULL, 221, 1, 0), /*DCO=5304M*/
PLL_RATE(5400000000ULL, 225, 1, 0), /*DCO=5400M*/
PLL_RATE(5496000000ULL, 229, 1, 0), /*DCO=5496M*/
PLL_RATE(5592000000ULL, 233, 1, 0), /*DCO=5592M*/
PLL_RATE(5688000000ULL, 237, 1, 0), /*DCO=5688M*/
PLL_RATE(5808000000ULL, 242, 1, 0), /*DCO=5808M*/
PLL_RATE(5904000000ULL, 246, 1, 0), /*DCO=5904M*/
PLL_RATE(6000000000ULL, 250, 1, 0), /*DCO=6000M*/
{ /* sentinel */ },
};

11
drivers/amlogic/clk/g12a/g12a_ao.c
View File

@@ -113,10 +113,13 @@ static void __init g12a_aoclkc_init(struct device_node *np)
}
/* pr_debug("%s: iomap clk_base ok!", __func__); */
/* Populate the base address for ao clk */
aoclk81.reg = ao_clk_base + (u64)aoclk81.reg;
g12a_saradc_mux.reg = ao_clk_base + (u64)g12a_saradc_mux.reg;
g12a_saradc_div.reg = ao_clk_base + (u64)g12a_saradc_div.reg;
g12a_saradc_gate.reg = ao_clk_base + (u64)g12a_saradc_gate.reg;
aoclk81.reg = ao_clk_base + (unsigned long)aoclk81.reg;
g12a_saradc_mux.reg = ao_clk_base
+ (unsigned long)g12a_saradc_mux.reg;
g12a_saradc_div.reg = ao_clk_base
+ (unsigned long)g12a_saradc_div.reg;
g12a_saradc_gate.reg = ao_clk_base
+ (unsigned long)g12a_saradc_gate.reg;
if (!clks) {
clks = kzalloc(NR_CLKS*sizeof(struct clk *), GFP_KERNEL);

11
drivers/amlogic/clk/g12a/g12a_clk-mpll.c
View File

@@ -45,6 +45,7 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw,
struct parm *p;
unsigned long rate = 0;
unsigned long reg, sdm, n2;
u64 rate64 = parent_rate;
p = &mpll->sdm;
reg = readl(mpll->base + p->reg_off);
@@ -54,7 +55,13 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw,
reg = readl(mpll->base + p->reg_off);
n2 = PARM_GET(p->width, p->shift, reg);
rate = (parent_rate * SDM_MAX) / ((SDM_MAX * n2) + sdm);
if (n2 == 0 && sdm == 0) {
rate = rate64;
} else {
rate64 = rate64 * SDM_MAX;
do_div(rate64, ((SDM_MAX * n2) + sdm));
rate = rate64;
}
return rate;
}
@@ -102,7 +109,7 @@ static int mpll_set_rate(struct clk_hw *hw, unsigned long rate,
writel(G12A_MPLL_CNTL0, mpll->base + mpll->mpll_cntl0_reg);
p = &mpll->sdm;
writel(G12A_MPLL_CNTL2, mpll->base + p->reg_off + (u64)(1*4));
writel(G12A_MPLL_CNTL2, mpll->base + p->reg_off + (unsigned long)(1*4));
reg = readl(mpll->base + p->reg_off);
reg = PARM_SET(p->width, p->shift, reg, sdm);
p = &mpll->n2;

120
drivers/amlogic/clk/g12a/g12a_clk-pll.c
View File

@@ -61,8 +61,8 @@
#define G12A_PCIE_PLL_CNTL3 0x10058e00
#define G12A_PCIE_PLL_CNTL4 0x000100c0
#define G12A_PCIE_PLL_CNTL4_ 0x008100c0
#define G12A_PCIE_PLL_CNTL5 0x68000048
#define G12A_PCIE_PLL_CNTL5_ 0x68000068
#define G12A_PCIE_PLL_CNTL5 0x28000048
#define G12A_PCIE_PLL_CNTL5_ 0x28000068
#define G12A_SYS_PLL_CNTL1 0x00000000
#define G12A_SYS_PLL_CNTL2 0x00000000
@@ -97,7 +97,7 @@ static unsigned long meson_g12a_pll_recalc_rate(struct clk_hw *hw,
{
struct meson_clk_pll *pll = to_meson_clk_pll(hw);
struct parm *p;
unsigned long parent_rate_mhz = parent_rate;
u64 parent_rate_mhz = parent_rate;
unsigned long rate_mhz;
u16 n, m, od, od2 = 0;
u32 reg, frac = 0;
@@ -234,62 +234,98 @@ static int meson_g12a_pll_set_rate(struct clk_hw *hw, unsigned long rate,
cntlbase = pll->base + p->reg_off;
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
writel(G12A_PCIE_PLL_CNTL0_0, cntlbase + (u64)(0*4));
writel(G12A_PCIE_PLL_CNTL0_1, cntlbase + (u64)(0*4));
writel(G12A_PCIE_PLL_CNTL1, cntlbase + (u64)(1*4));
writel(G12A_PCIE_PLL_CNTL2, cntlbase + (u64)(2*4));
writel(G12A_PCIE_PLL_CNTL3, cntlbase + (u64)(3*4));
writel(G12A_PCIE_PLL_CNTL4, cntlbase + (u64)(4*4));
writel(G12A_PCIE_PLL_CNTL5, cntlbase + (u64)(5*4));
writel(G12A_PCIE_PLL_CNTL5_, cntlbase + (u64)(5*4));
writel(G12A_PCIE_PLL_CNTL0_0,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL0_1,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_PCIE_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_PCIE_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_PCIE_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_PCIE_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PCIE_PLL_CNTL5_,
cntlbase + (unsigned long)(5*4));
udelay(20);
writel(G12A_PCIE_PLL_CNTL4_, cntlbase + (u64)(4*4));
writel(G12A_PCIE_PLL_CNTL4_,
cntlbase + (unsigned long)(4*4));
udelay(10);
/*set pcie_apll_afc_start bit*/
writel(G12A_PCIE_PLL_CNTL0_2, cntlbase + (u64)(0*4));
writel(G12A_PCIE_PLL_CNTL0_3, cntlbase + (u64)(0*4));
writel(G12A_PCIE_PLL_CNTL0_2,
cntlbase + (unsigned long)(0*4));
writel(G12A_PCIE_PLL_CNTL0_3,
cntlbase + (unsigned long)(0*4));
udelay(10);
writel(G12A_PCIE_PLL_CNTL2_, cntlbase + (u64)(2*4));
writel(G12A_PCIE_PLL_CNTL2_,
cntlbase + (unsigned long)(2*4));
goto OUT;
} else if (!strcmp(clk_hw_get_name(hw), "sys_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_SYS_PLL_CNTL1, cntlbase + (u64)1*4);
writel(G12A_SYS_PLL_CNTL2, cntlbase + (u64)2*4);
writel(G12A_SYS_PLL_CNTL3, cntlbase + (u64)3*4);
writel(G12A_SYS_PLL_CNTL4, cntlbase + (u64)4*4);
writel(G12A_SYS_PLL_CNTL5, cntlbase + (u64)5*4);
writel(G12A_PLL_CNTL6, cntlbase + (u64)6*4);
writel(G12A_SYS_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_SYS_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_SYS_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_SYS_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_SYS_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6*4));
udelay(10);
} else if (!strcmp(clk_hw_get_name(hw), "sys1_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_SYS1_PLL_CNTL1, cntlbase + (u64)1*4);
writel(G12A_SYS1_PLL_CNTL2, cntlbase + (u64)2*4);
writel(G12A_SYS1_PLL_CNTL3, cntlbase + (u64)3*4);
writel(G12A_SYS1_PLL_CNTL4, cntlbase + (u64)4*4);
writel(G12A_SYS1_PLL_CNTL5, cntlbase + (u64)5*4);
writel(G12A_PLL_CNTL6, cntlbase + (u64)6*4);
writel(G12A_SYS1_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_SYS1_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_SYS1_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_SYS1_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_SYS1_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6*4));
udelay(10);
} else if (!strcmp(clk_hw_get_name(hw), "gp0_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_GP0_PLL_CNTL1, cntlbase + (u64)1*4);
writel(G12A_GP0_PLL_CNTL2, cntlbase + (u64)2*4);
writel(G12A_GP0_PLL_CNTL3, cntlbase + (u64)3*4);
writel(G12A_GP0_PLL_CNTL4, cntlbase + (u64)4*4);
writel(G12A_GP0_PLL_CNTL5, cntlbase + (u64)5*4);
writel(G12A_PLL_CNTL6, cntlbase + (u64)6*4);
writel(G12A_GP0_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_GP0_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_GP0_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_GP0_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_GP0_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6*4));
udelay(10);
} else if (!strcmp(clk_hw_get_name(hw), "hifi_pll")) {
writel((readl(cntlbase) | MESON_PLL_RESET)
& (~MESON_PLL_ENABLE), cntlbase);
writel(G12A_GP0_PLL_CNTL1, cntlbase + (u64)1*4);
writel(G12A_GP0_PLL_CNTL2, cntlbase + (u64)2*4);
writel(G12A_GP0_PLL_CNTL3, cntlbase + (u64)3*4);
writel(G12A_GP0_PLL_CNTL4, cntlbase + (u64)4*4);
writel(G12A_GP0_PLL_CNTL5, cntlbase + (u64)5*4);
writel(G12A_PLL_CNTL6, cntlbase + (u64)6*4);
writel(G12A_GP0_PLL_CNTL1,
cntlbase + (unsigned long)(1*4));
writel(G12A_GP0_PLL_CNTL2,
cntlbase + (unsigned long)(2*4));
writel(G12A_GP0_PLL_CNTL3,
cntlbase + (unsigned long)(3*4));
writel(G12A_GP0_PLL_CNTL4,
cntlbase + (unsigned long)(4*4));
writel(G12A_GP0_PLL_CNTL5,
cntlbase + (unsigned long)(5*4));
writel(G12A_PLL_CNTL6,
cntlbase + (unsigned long)(6*4));
udelay(10);
} else {
pr_err("%s: %s pll not found!!!\n",
@@ -385,10 +421,12 @@ static int meson_g12a_pll_enable(struct clk_hw *hw)
void *cntlbase = pll->base + p->reg_off;
if (!strcmp(clk_hw_get_name(hw), "pcie_pll")) {
if (readl(cntlbase + (u64)(3*4)) == G12A_PCIE_PLL_CNTL3)
if (readl(cntlbase + (unsigned long)(3*4))
== G12A_PCIE_PLL_CNTL3)
first_set = 0;
} else {
if (readl(cntlbase + (u64)(6*4)) == G12A_PLL_CNTL6)
if (readl(cntlbase + (unsigned long)(6*4))
== G12A_PLL_CNTL6)
first_set = 0;
}
}

14
drivers/amlogic/clk/g12a/g12a_clk_gpu.c
View File

@@ -139,13 +139,13 @@ static struct clk_hw *gpu_clk_hws[] = {
void meson_g12a_gpu_init(void)
{
gpu_p0_mux.reg = clk_base + (u64)(gpu_p0_mux.reg);
gpu_p0_div.reg = clk_base + (u64)(gpu_p0_div.reg);
gpu_p0_gate.reg = clk_base + (u64)(gpu_p0_gate.reg);
gpu_p1_mux.reg = clk_base + (u64)(gpu_p1_mux.reg);
gpu_p1_div.reg = clk_base + (u64)(gpu_p1_div.reg);
gpu_p1_gate.reg = clk_base + (u64)(gpu_p1_gate.reg);
gpu_mux.reg = clk_base + (u64)(gpu_mux.reg);
gpu_p0_mux.reg = clk_base + (unsigned long)(gpu_p0_mux.reg);
gpu_p0_div.reg = clk_base + (unsigned long)(gpu_p0_div.reg);
gpu_p0_gate.reg = clk_base + (unsigned long)(gpu_p0_gate.reg);
gpu_p1_mux.reg = clk_base + (unsigned long)(gpu_p1_mux.reg);
gpu_p1_div.reg = clk_base + (unsigned long)(gpu_p1_div.reg);
gpu_p1_gate.reg = clk_base + (unsigned long)(gpu_p1_gate.reg);
gpu_mux.reg = clk_base + (unsigned long)(gpu_mux.reg);
clks[CLKID_GPU_P0_COMP] = clk_register_composite(NULL,
"gpu_p0_composite",

117
drivers/amlogic/clk/g12a/g12a_clk_media.c
View File

@@ -947,81 +947,82 @@ static struct clk_hw *vpu_clkc_hws[] = {
void meson_g12a_media_init(void)
{
/* cts_dsi_meas_clk */
dsi_meas_mux.reg = clk_base + (u64)(dsi_meas_mux.reg);
dsi_meas_div.reg = clk_base + (u64)(dsi_meas_div.reg);
dsi_meas_gate.reg = clk_base + (u64)(dsi_meas_gate.reg);
dsi_meas_mux.reg = clk_base + (unsigned long)(dsi_meas_mux.reg);
dsi_meas_div.reg = clk_base + (unsigned long)(dsi_meas_div.reg);
dsi_meas_gate.reg = clk_base + (unsigned long)(dsi_meas_gate.reg);
/* cts_vdec_clk */
vdec_p0_mux.reg = clk_base + (u64)(vdec_p0_mux.reg);
vdec_p0_div.reg = clk_base + (u64)(vdec_p0_div.reg);
vdec_p0_gate.reg = clk_base + (u64)(vdec_p0_gate.reg);
vdec_p1_mux.reg = clk_base + (u64)(vdec_p1_mux.reg);
vdec_p1_div.reg = clk_base + (u64)(vdec_p1_div.reg);
vdec_p1_gate.reg = clk_base + (u64)(vdec_p1_gate.reg);
vdec_mux.reg = clk_base + (u64)(vdec_mux.reg);
vdec_p0_mux.reg = clk_base + (unsigned long)(vdec_p0_mux.reg);
vdec_p0_div.reg = clk_base + (unsigned long)(vdec_p0_div.reg);
vdec_p0_gate.reg = clk_base + (unsigned long)(vdec_p0_gate.reg);
vdec_p1_mux.reg = clk_base + (unsigned long)(vdec_p1_mux.reg);
vdec_p1_div.reg = clk_base + (unsigned long)(vdec_p1_div.reg);
vdec_p1_gate.reg = clk_base + (unsigned long)(vdec_p1_gate.reg);
vdec_mux.reg = clk_base + (unsigned long)(vdec_mux.reg);
/* cts_hcodec_clk */
hcodec_p0_mux.reg = clk_base + (u64)(hcodec_p0_mux.reg);
hcodec_p0_div.reg = clk_base + (u64)(hcodec_p0_div.reg);
hcodec_p0_gate.reg = clk_base + (u64)(hcodec_p0_gate.reg);
hcodec_p1_mux.reg = clk_base + (u64)(hcodec_p1_mux.reg);
hcodec_p1_div.reg = clk_base + (u64)(hcodec_p1_div.reg);
hcodec_p1_gate.reg = clk_base + (u64)(hcodec_p1_gate.reg);
hcodec_mux.reg = clk_base + (u64)(hcodec_mux.reg);
hcodec_p0_mux.reg = clk_base + (unsigned long)(hcodec_p0_mux.reg);
hcodec_p0_div.reg = clk_base + (unsigned long)(hcodec_p0_div.reg);
hcodec_p0_gate.reg = clk_base + (unsigned long)(hcodec_p0_gate.reg);
hcodec_p1_mux.reg = clk_base + (unsigned long)(hcodec_p1_mux.reg);
hcodec_p1_div.reg = clk_base + (unsigned long)(hcodec_p1_div.reg);
hcodec_p1_gate.reg = clk_base + (unsigned long)(hcodec_p1_gate.reg);
hcodec_mux.reg = clk_base + (unsigned long)(hcodec_mux.reg);
/* cts_hevc_clk */
hevc_p0_mux.reg = clk_base + (u64)(hevc_p0_mux.reg);
hevc_p0_div.reg = clk_base + (u64)(hevc_p0_div.reg);
hevc_p0_gate.reg = clk_base + (u64)(hevc_p0_gate.reg);
hevc_p1_mux.reg = clk_base + (u64)(hevc_p1_mux.reg);
hevc_p1_div.reg = clk_base + (u64)(hevc_p1_div.reg);
hevc_p1_gate.reg = clk_base + (u64)(hevc_p1_gate.reg);
hevc_mux.reg = clk_base + (u64)(hevc_mux.reg);
hevc_p0_mux.reg = clk_base + (unsigned long)(hevc_p0_mux.reg);
hevc_p0_div.reg = clk_base + (unsigned long)(hevc_p0_div.reg);
hevc_p0_gate.reg = clk_base + (unsigned long)(hevc_p0_gate.reg);
hevc_p1_mux.reg = clk_base + (unsigned long)(hevc_p1_mux.reg);
hevc_p1_div.reg = clk_base + (unsigned long)(hevc_p1_div.reg);
hevc_p1_gate.reg = clk_base + (unsigned long)(hevc_p1_gate.reg);
hevc_mux.reg = clk_base + (unsigned long)(hevc_mux.reg);
/* cts_hevcf_clk */
hevcf_p0_mux.reg = clk_base + (u64)(hevcf_p0_mux.reg);
hevcf_p0_div.reg = clk_base + (u64)(hevcf_p0_div.reg);
hevcf_p0_gate.reg = clk_base + (u64)(hevcf_p0_gate.reg);
hevcf_p1_mux.reg = clk_base + (u64)(hevcf_p1_mux.reg);
hevcf_p1_div.reg = clk_base + (u64)(hevcf_p1_div.reg);
hevcf_p1_gate.reg = clk_base + (u64)(hevcf_p1_gate.reg);
hevcf_mux.reg = clk_base + (u64)(hevcf_mux.reg);
hevcf_p0_mux.reg = clk_base + (unsigned long)(hevcf_p0_mux.reg);
hevcf_p0_div.reg = clk_base + (unsigned long)(hevcf_p0_div.reg);
hevcf_p0_gate.reg = clk_base + (unsigned long)(hevcf_p0_gate.reg);
hevcf_p1_mux.reg = clk_base + (unsigned long)(hevcf_p1_mux.reg);
hevcf_p1_div.reg = clk_base + (unsigned long)(hevcf_p1_div.reg);
hevcf_p1_gate.reg = clk_base + (unsigned long)(hevcf_p1_gate.reg);
hevcf_mux.reg = clk_base + (unsigned long)(hevcf_mux.reg);
/* cts_vpu_clk */
vpu_p0_mux.reg = clk_base + (u64)(vpu_p0_mux.reg);
vpu_p0_div.reg = clk_base + (u64)(vpu_p0_div.reg);
vpu_p0_gate.reg = clk_base + (u64)(vpu_p0_gate.reg);
vpu_p1_mux.reg = clk_base + (u64)(vpu_p1_mux.reg);
vpu_p1_div.reg = clk_base + (u64)(vpu_p1_div.reg);
vpu_p1_gate.reg = clk_base + (u64)(vpu_p1_gate.reg);
vpu_mux.reg = clk_base + (u64)(vpu_mux.reg);
vpu_p0_mux.reg = clk_base + (unsigned long)(vpu_p0_mux.reg);
vpu_p0_div.reg = clk_base + (unsigned long)(vpu_p0_div.reg);
vpu_p0_gate.reg = clk_base + (unsigned long)(vpu_p0_gate.reg);
vpu_p1_mux.reg = clk_base + (unsigned long)(vpu_p1_mux.reg);
vpu_p1_div.reg = clk_base + (unsigned long)(vpu_p1_div.reg);
vpu_p1_gate.reg = clk_base + (unsigned long)(vpu_p1_gate.reg);
vpu_mux.reg = clk_base + (unsigned long)(vpu_mux.reg);
/* cts_vapbclk */
vapb_p0_mux.reg = clk_base + (u64)(vapb_p0_mux.reg);
vapb_p0_div.reg = clk_base + (u64)(vapb_p0_div.reg);
vapb_p0_gate.reg = clk_base + (u64)(vapb_p0_gate.reg);
vapb_p1_mux.reg = clk_base + (u64)(vapb_p1_mux.reg);
vapb_p1_div.reg = clk_base + (u64)(vapb_p1_div.reg);
vapb_p1_gate.reg = clk_base + (u64)(vapb_p1_gate.reg);
vapb_mux.reg = clk_base + (u64)(vapb_mux.reg);
vapb_p0_mux.reg = clk_base + (unsigned long)(vapb_p0_mux.reg);
vapb_p0_div.reg = clk_base + (unsigned long)(vapb_p0_div.reg);
vapb_p0_gate.reg = clk_base + (unsigned long)(vapb_p0_gate.reg);
vapb_p1_mux.reg = clk_base + (unsigned long)(vapb_p1_mux.reg);
vapb_p1_div.reg = clk_base + (unsigned long)(vapb_p1_div.reg);
vapb_p1_gate.reg = clk_base + (unsigned long)(vapb_p1_gate.reg);
vapb_mux.reg = clk_base + (unsigned long)(vapb_mux.reg);
/* cts_ge2d_clk */
ge2d_gate.reg = clk_base + (u64)(ge2d_gate.reg);
ge2d_gate.reg = clk_base + (unsigned long)(ge2d_gate.reg);
/* vpu_clkb_tmp */
vpu_clkb_tmp_mux.reg = clk_base + (u64)(vpu_clkb_tmp_mux.reg);
vpu_clkb_tmp_div.reg = clk_base + (u64)(vpu_clkb_tmp_div.reg);
vpu_clkb_tmp_gate.reg = clk_base + (u64)(vpu_clkb_tmp_gate.reg);
vpu_clkb_tmp_mux.reg = clk_base + (unsigned long)(vpu_clkb_tmp_mux.reg);
vpu_clkb_tmp_div.reg = clk_base + (unsigned long)(vpu_clkb_tmp_div.reg);
vpu_clkb_tmp_gate.reg = clk_base
+ (unsigned long)(vpu_clkb_tmp_gate.reg);
vpu_clkb_div.reg = clk_base + (u64)(vpu_clkb_div.reg);
vpu_clkb_gate.reg = clk_base + (u64)(vpu_clkb_gate.reg);
vpu_clkb_div.reg = clk_base + (unsigned long)(vpu_clkb_div.reg);
vpu_clkb_gate.reg = clk_base + (unsigned long)(vpu_clkb_gate.reg);
/* cts_vpu_clkc */
vpu_clkc_p0_mux.reg = clk_base + (u64)(vpu_clkc_p0_mux.reg);
vpu_clkc_p0_div.reg = clk_base + (u64)(vpu_clkc_p0_div.reg);
vpu_clkc_p0_gate.reg = clk_base + (u64)(vpu_clkc_p0_gate.reg);
vpu_clkc_p1_mux.reg = clk_base + (u64)(vpu_clkc_p1_mux.reg);
vpu_clkc_p1_div.reg = clk_base + (u64)(vpu_clkc_p1_div.reg);
vpu_clkc_p1_gate.reg = clk_base + (u64)(vpu_clkc_p1_gate.reg);
vpu_clkc_mux.reg = clk_base + (u64)(vpu_clkc_mux.reg);
vpu_clkc_p0_mux.reg = clk_base + (unsigned long)(vpu_clkc_p0_mux.reg);
vpu_clkc_p0_div.reg = clk_base + (unsigned long)(vpu_clkc_p0_div.reg);
vpu_clkc_p0_gate.reg = clk_base + (unsigned long)(vpu_clkc_p0_gate.reg);
vpu_clkc_p1_mux.reg = clk_base + (unsigned long)(vpu_clkc_p1_mux.reg);
vpu_clkc_p1_div.reg = clk_base + (unsigned long)(vpu_clkc_p1_div.reg);
vpu_clkc_p1_gate.reg = clk_base + (unsigned long)(vpu_clkc_p1_gate.reg);
vpu_clkc_mux.reg = clk_base + (unsigned long)(vpu_clkc_mux.reg);
clks[CLKID_DSI_MEAS_COMP] = clk_register_composite(NULL,
"dsi_meas_composite",

16
drivers/amlogic/clk/g12a/g12a_clk_misc.c
View File

@@ -150,15 +150,15 @@ void meson_g12a_misc_init(void)
/* Populate base address for reg */
pr_info("%s: register amlogic g12a misc clks\n", __func__);
g12a_ts_clk_div.reg = clk_base + (u64)(g12a_ts_clk_div.reg);
g12a_ts_clk_gate.reg = clk_base + (u64)(g12a_ts_clk_gate.reg);
g12a_ts_clk_div.reg = clk_base + (unsigned long)(g12a_ts_clk_div.reg);
g12a_ts_clk_gate.reg = clk_base + (unsigned long)(g12a_ts_clk_gate.reg);
g12a_spicc0_mux.reg = clk_base + (u64)(g12a_spicc0_mux.reg);
g12a_spicc0_div.reg = clk_base + (u64)(g12a_spicc0_div.reg);
g12a_spicc0_gate.reg = clk_base + (u64)(g12a_spicc0_gate.reg);
g12a_spicc1_mux.reg = clk_base + (u64)(g12a_spicc1_mux.reg);
g12a_spicc1_div.reg = clk_base + (u64)(g12a_spicc1_div.reg);
g12a_spicc1_gate.reg = clk_base + (u64)(g12a_spicc1_gate.reg);
g12a_spicc0_mux.reg = clk_base + (unsigned long)(g12a_spicc0_mux.reg);
g12a_spicc0_div.reg = clk_base + (unsigned long)(g12a_spicc0_div.reg);
g12a_spicc0_gate.reg = clk_base + (unsigned long)(g12a_spicc0_gate.reg);
g12a_spicc1_mux.reg = clk_base + (unsigned long)(g12a_spicc1_mux.reg);
g12a_spicc1_div.reg = clk_base + (unsigned long)(g12a_spicc1_div.reg);
g12a_spicc1_gate.reg = clk_base + (unsigned long)(g12a_spicc1_gate.reg);
clks[CLKID_TS_COMP] = clk_register_composite(NULL,
"ts_comp",

27
drivers/amlogic/clk/g12a/g12a_clk_sdemmc.c
View File

@@ -179,15 +179,24 @@ void meson_g12a_sdemmc_init(void)
/* Populate base address for reg */
pr_info("%s: register amlogic sdemmc clk\n", __func__);
sd_emmc_p0_mux_A.reg = clk_base + (u64)(sd_emmc_p0_mux_A.reg);
sd_emmc_p0_div_A.reg = clk_base + (u64)(sd_emmc_p0_div_A.reg);
sd_emmc_p0_gate_A.reg = clk_base + (u64)(sd_emmc_p0_gate_A.reg);
sd_emmc_p0_mux_B.reg = clk_base + (u64)(sd_emmc_p0_mux_B.reg);
sd_emmc_p0_div_B.reg = clk_base + (u64)(sd_emmc_p0_div_B.reg);
sd_emmc_p0_gate_B.reg = clk_base + (u64)(sd_emmc_p0_gate_B.reg);
sd_emmc_p0_mux_C.reg = clk_base + (u64)(sd_emmc_p0_mux_C.reg);
sd_emmc_p0_div_C.reg = clk_base + (u64)(sd_emmc_p0_div_C.reg);
sd_emmc_p0_gate_C.reg = clk_base + (u64)(sd_emmc_p0_gate_C.reg);
sd_emmc_p0_mux_A.reg = clk_base
+ (unsigned long)(sd_emmc_p0_mux_A.reg);
sd_emmc_p0_div_A.reg = clk_base
+ (unsigned long)(sd_emmc_p0_div_A.reg);
sd_emmc_p0_gate_A.reg = clk_base
+ (unsigned long)(sd_emmc_p0_gate_A.reg);
sd_emmc_p0_mux_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_mux_B.reg);
sd_emmc_p0_div_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_div_B.reg);
sd_emmc_p0_gate_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_gate_B.reg);
sd_emmc_p0_mux_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_mux_C.reg);
sd_emmc_p0_div_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_div_C.reg);
sd_emmc_p0_gate_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_gate_C.reg);
clks[CLKID_SD_EMMC_A_P0_COMP] = clk_register_composite(NULL,
"sd_emmc_p0_A_comp",

58
drivers/amlogic/clk/g12b/g12b.c
View File

@@ -489,58 +489,66 @@ static void __init g12b_clkc_init(struct device_node *np)
}
g12b_cpu_clk.base = clk_base;
g12b_cpu_fclk_p.reg = clk_base + (u64)g12b_cpu_fclk_p.reg;
g12b_cpu_clk.mux.reg = clk_base + (u64)g12b_cpu_clk.mux.reg;
g12b_cpu_fclk_p.reg = clk_base
+ (unsigned long)g12b_cpu_fclk_p.reg;
g12b_cpu_clk.mux.reg = clk_base
+ (unsigned long)g12b_cpu_clk.mux.reg;
cts_gdc_core_clk_mux.reg = clk_base + (u64)(cts_gdc_core_clk_mux.reg);
cts_gdc_core_clk_gate.reg = clk_base + (u64)(cts_gdc_core_clk_gate.reg);
cts_gdc_core_clk_div.reg = clk_base + (u64)(cts_gdc_core_clk_div.reg);
cts_gdc_core_clk_mux.reg = clk_base
+ (unsigned long)(cts_gdc_core_clk_mux.reg);
cts_gdc_core_clk_gate.reg = clk_base
+ (unsigned long)(cts_gdc_core_clk_gate.reg);
cts_gdc_core_clk_div.reg = clk_base
+ (unsigned long)(cts_gdc_core_clk_div.reg);
cts_gdc_axi_clk_mux.reg = clk_base + (u64)(cts_gdc_axi_clk_mux.reg);
cts_gdc_axi_clk_gate.reg = clk_base + (u64)(cts_gdc_axi_clk_gate.reg);
cts_gdc_axi_clk_div.reg = clk_base + (u64)(cts_gdc_axi_clk_div.reg);
cts_gdc_axi_clk_mux.reg = clk_base
+ (unsigned long)(cts_gdc_axi_clk_mux.reg);
cts_gdc_axi_clk_gate.reg = clk_base
+ (unsigned long)(cts_gdc_axi_clk_gate.reg);
cts_gdc_axi_clk_div.reg = clk_base
+ (unsigned long)(cts_gdc_axi_clk_div.reg);
cts_vipnanoq_core_clk_mux.reg = clk_base
+ (u64)(cts_vipnanoq_core_clk_mux.reg);
+ (unsigned long)(cts_vipnanoq_core_clk_mux.reg);
cts_vipnanoq_core_clk_gate.reg = clk_base
+ (u64)(cts_vipnanoq_core_clk_gate.reg);
+ (unsigned long)(cts_vipnanoq_core_clk_gate.reg);
cts_vipnanoq_core_clk_div.reg = clk_base
+ (u64)(cts_vipnanoq_core_clk_div.reg);
+ (unsigned long)(cts_vipnanoq_core_clk_div.reg);
cts_vipnanoq_axi_clk_mux.reg = clk_base
+ (u64)(cts_vipnanoq_axi_clk_mux.reg);
+ (unsigned long)(cts_vipnanoq_axi_clk_mux.reg);
cts_vipnanoq_axi_clk_gate.reg = clk_base
+ (u64)(cts_vipnanoq_axi_clk_gate.reg);
+ (unsigned long)(cts_vipnanoq_axi_clk_gate.reg);
cts_vipnanoq_axi_clk_div.reg = clk_base
+ (u64)(cts_vipnanoq_axi_clk_div.reg);
+ (unsigned long)(cts_vipnanoq_axi_clk_div.reg);
cts_mipi_isp_clk_mux.reg = clk_base
+ (u64)(cts_mipi_isp_clk_mux.reg);
+ (unsigned long)(cts_mipi_isp_clk_mux.reg);
cts_mipi_isp_clk_gate.reg = clk_base
+ (u64)(cts_mipi_isp_clk_gate.reg);
+ (unsigned long)(cts_mipi_isp_clk_gate.reg);
cts_mipi_isp_clk_div.reg = clk_base
+ (u64)(cts_mipi_isp_clk_div.reg);
+ (unsigned long)(cts_mipi_isp_clk_div.reg);
cts_mipi_csi_phy_clk0_mux.reg = clk_base
+ (u64)(cts_mipi_csi_phy_clk0_mux.reg);
+ (unsigned long)(cts_mipi_csi_phy_clk0_mux.reg);
cts_mipi_csi_phy_clk0_div.reg = clk_base
+ (u64)(cts_mipi_csi_phy_clk0_div.reg);
+ (unsigned long)(cts_mipi_csi_phy_clk0_div.reg);
cts_mipi_csi_phy_clk0_gate.reg = clk_base
+ (u64)(cts_mipi_csi_phy_clk0_gate.reg);
+ (unsigned long)(cts_mipi_csi_phy_clk0_gate.reg);
cts_mipi_csi_phy_clk1_mux.reg = clk_base
+ (u64)(cts_mipi_csi_phy_clk1_mux.reg);
+ (unsigned long)(cts_mipi_csi_phy_clk1_mux.reg);
cts_mipi_csi_phy_clk1_div.reg = clk_base
+ (u64)(cts_mipi_csi_phy_clk1_div.reg);
+ (unsigned long)(cts_mipi_csi_phy_clk1_div.reg);
cts_mipi_csi_phy_clk1_gate.reg = clk_base
+ (u64)(cts_mipi_csi_phy_clk1_gate.reg);
+ (unsigned long)(cts_mipi_csi_phy_clk1_gate.reg);
cts_mipi_sci_phy_mux.reg = clk_base
+ (u64)(cts_mipi_sci_phy_mux.reg);
+ (unsigned long)(cts_mipi_sci_phy_mux.reg);
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(g12b_clk_gates); i++)
g12b_clk_gates[i]->reg = clk_base +
(u64)g12b_clk_gates[i]->reg;
(unsigned long)g12b_clk_gates[i]->reg;
/* Populate base address for PLLs */
for (i = 0; i < ARRAY_SIZE(g12b_clk_plls); i++)

14
drivers/amlogic/clk/gxl/clk_gpu.c
View File

@@ -140,13 +140,13 @@ static struct clk_hw *gpu_clk_hws[] = {
void amlogic_init_gpu(void)
{
gpu_p0_mux.reg = clk_base + (u64)(gpu_p0_mux.reg);
gpu_p0_div.reg = clk_base + (u64)(gpu_p0_div.reg);
gpu_p0_gate.reg = clk_base + (u64)(gpu_p0_gate.reg);
gpu_p1_mux.reg = clk_base + (u64)(gpu_p1_mux.reg);
gpu_p1_div.reg = clk_base + (u64)(gpu_p1_div.reg);
gpu_p1_gate.reg = clk_base + (u64)(gpu_p1_gate.reg);
gpu_mux.reg = clk_base + (u64)(gpu_mux.reg);
gpu_p0_mux.reg = clk_base + (unsigned long)(gpu_p0_mux.reg);
gpu_p0_div.reg = clk_base + (unsigned long)(gpu_p0_div.reg);
gpu_p0_gate.reg = clk_base + (unsigned long)(gpu_p0_gate.reg);
gpu_p1_mux.reg = clk_base + (unsigned long)(gpu_p1_mux.reg);
gpu_p1_div.reg = clk_base + (unsigned long)(gpu_p1_div.reg);
gpu_p1_gate.reg = clk_base + (unsigned long)(gpu_p1_gate.reg);
gpu_mux.reg = clk_base + (unsigned long)(gpu_mux.reg);
clks[CLKID_GPU_P0_COMP] = clk_register_composite(NULL,
"gpu_p0_composite",

78
drivers/amlogic/clk/gxl/clk_media.c
View File

@@ -649,51 +649,51 @@ static struct clk_hw *bt656_clk1_hws[] = {
void amlogic_init_media(void)
{
/* cts_vdec_clk */
vdec_p0_mux.reg = clk_base + (u64)(vdec_p0_mux.reg);
vdec_p0_div.reg = clk_base + (u64)(vdec_p0_div.reg);
vdec_p0_gate.reg = clk_base + (u64)(vdec_p0_gate.reg);
vdec_p1_mux.reg = clk_base + (u64)(vdec_p1_mux.reg);
vdec_p1_div.reg = clk_base + (u64)(vdec_p1_div.reg);
vdec_p1_gate.reg = clk_base + (u64)(vdec_p1_gate.reg);
vdec_mux.reg = clk_base + (u64)(vdec_mux.reg);
vdec_p0_mux.reg = clk_base + (unsigned long)(vdec_p0_mux.reg);
vdec_p0_div.reg = clk_base + (unsigned long)(vdec_p0_div.reg);
vdec_p0_gate.reg = clk_base + (unsigned long)(vdec_p0_gate.reg);
vdec_p1_mux.reg = clk_base + (unsigned long)(vdec_p1_mux.reg);
vdec_p1_div.reg = clk_base + (unsigned long)(vdec_p1_div.reg);
vdec_p1_gate.reg = clk_base + (unsigned long)(vdec_p1_gate.reg);
vdec_mux.reg = clk_base + (unsigned long)(vdec_mux.reg);
/* cts_hcodec_clk */
hcodec_p0_mux.reg = clk_base + (u64)(hcodec_p0_mux.reg);
hcodec_p0_div.reg = clk_base + (u64)(hcodec_p0_div.reg);
hcodec_p0_gate.reg = clk_base + (u64)(hcodec_p0_gate.reg);
hcodec_p1_mux.reg = clk_base + (u64)(hcodec_p1_mux.reg);
hcodec_p1_div.reg = clk_base + (u64)(hcodec_p1_div.reg);
hcodec_p1_gate.reg = clk_base + (u64)(hcodec_p1_gate.reg);
hcodec_mux.reg = clk_base + (u64)(hcodec_mux.reg);
hcodec_p0_mux.reg = clk_base + (unsigned long)(hcodec_p0_mux.reg);
hcodec_p0_div.reg = clk_base + (unsigned long)(hcodec_p0_div.reg);
hcodec_p0_gate.reg = clk_base + (unsigned long)(hcodec_p0_gate.reg);
hcodec_p1_mux.reg = clk_base + (unsigned long)(hcodec_p1_mux.reg);
hcodec_p1_div.reg = clk_base + (unsigned long)(hcodec_p1_div.reg);
hcodec_p1_gate.reg = clk_base + (unsigned long)(hcodec_p1_gate.reg);
hcodec_mux.reg = clk_base + (unsigned long)(hcodec_mux.reg);
/* cts_hevc_clk */
hevc_p0_mux.reg = clk_base + (u64)(hevc_p0_mux.reg);
hevc_p0_div.reg = clk_base + (u64)(hevc_p0_div.reg);
hevc_p0_gate.reg = clk_base + (u64)(hevc_p0_gate.reg);
hevc_p1_mux.reg = clk_base + (u64)(hevc_p1_mux.reg);
hevc_p1_div.reg = clk_base + (u64)(hevc_p1_div.reg);
hevc_p1_gate.reg = clk_base + (u64)(hevc_p1_gate.reg);
hevc_mux.reg = clk_base + (u64)(hevc_mux.reg);
hevc_p0_mux.reg = clk_base + (unsigned long)(hevc_p0_mux.reg);
hevc_p0_div.reg = clk_base + (unsigned long)(hevc_p0_div.reg);
hevc_p0_gate.reg = clk_base + (unsigned long)(hevc_p0_gate.reg);
hevc_p1_mux.reg = clk_base + (unsigned long)(hevc_p1_mux.reg);
hevc_p1_div.reg = clk_base + (unsigned long)(hevc_p1_div.reg);
hevc_p1_gate.reg = clk_base + (unsigned long)(hevc_p1_gate.reg);
hevc_mux.reg = clk_base + (unsigned long)(hevc_mux.reg);
/* cts_vpu_clk */
vpu_p0_mux.reg = clk_base + (u64)(vpu_p0_mux.reg);
vpu_p0_div.reg = clk_base + (u64)(vpu_p0_div.reg);
vpu_p0_gate.reg = clk_base + (u64)(vpu_p0_gate.reg);
vpu_p1_mux.reg = clk_base + (u64)(vpu_p1_mux.reg);
vpu_p1_div.reg = clk_base + (u64)(vpu_p1_div.reg);
vpu_p1_gate.reg = clk_base + (u64)(vpu_p1_gate.reg);
vpu_mux.reg = clk_base + (u64)(vpu_mux.reg);
vpu_p0_mux.reg = clk_base + (unsigned long)(vpu_p0_mux.reg);
vpu_p0_div.reg = clk_base + (unsigned long)(vpu_p0_div.reg);
vpu_p0_gate.reg = clk_base + (unsigned long)(vpu_p0_gate.reg);
vpu_p1_mux.reg = clk_base + (unsigned long)(vpu_p1_mux.reg);
vpu_p1_div.reg = clk_base + (unsigned long)(vpu_p1_div.reg);
vpu_p1_gate.reg = clk_base + (unsigned long)(vpu_p1_gate.reg);
vpu_mux.reg = clk_base + (unsigned long)(vpu_mux.reg);
/* cts_vapbclk */
vapb_p0_mux.reg = clk_base + (u64)(vapb_p0_mux.reg);
vapb_p0_div.reg = clk_base + (u64)(vapb_p0_div.reg);
vapb_p0_gate.reg = clk_base + (u64)(vapb_p0_gate.reg);
vapb_p1_mux.reg = clk_base + (u64)(vapb_p1_mux.reg);
vapb_p1_div.reg = clk_base + (u64)(vapb_p1_div.reg);
vapb_p1_gate.reg = clk_base + (u64)(vapb_p1_gate.reg);
vapb_mux.reg = clk_base + (u64)(vapb_mux.reg);
vapb_p0_mux.reg = clk_base + (unsigned long)(vapb_p0_mux.reg);
vapb_p0_div.reg = clk_base + (unsigned long)(vapb_p0_div.reg);
vapb_p0_gate.reg = clk_base + (unsigned long)(vapb_p0_gate.reg);
vapb_p1_mux.reg = clk_base + (unsigned long)(vapb_p1_mux.reg);
vapb_p1_div.reg = clk_base + (unsigned long)(vapb_p1_div.reg);
vapb_p1_gate.reg = clk_base + (unsigned long)(vapb_p1_gate.reg);
vapb_mux.reg = clk_base + (unsigned long)(vapb_mux.reg);
/* cts_ge2d_clk */
ge2d_gate.reg = clk_base + (u64)(ge2d_gate.reg);
ge2d_gate.reg = clk_base + (unsigned long)(ge2d_gate.reg);
/* cts_bt656_clk1 */
bt656_clk1_mux.reg = clk_base + (u64)(bt656_clk1_mux.reg);
bt656_clk1_div.reg = clk_base + (u64)(bt656_clk1_div.reg);
bt656_clk1_gate.reg = clk_base + (u64)(bt656_clk1_gate.reg);
bt656_clk1_mux.reg = clk_base + (unsigned long)(bt656_clk1_mux.reg);
bt656_clk1_div.reg = clk_base + (unsigned long)(bt656_clk1_div.reg);
bt656_clk1_gate.reg = clk_base + (unsigned long)(bt656_clk1_gate.reg);
/* cts_vdec_clk */
clks[CLKID_VDEC_P0_COMP] = clk_register_composite(NULL,

42
drivers/amlogic/clk/gxl/clk_misc.c
View File

@@ -375,41 +375,41 @@ static struct clk_hw *saradc_hws[] = {
void amlogic_init_misc(void)
{
/* cts_vdin_meas_clk */
vdin_meas_mux.reg = clk_base + (u64)(vdin_meas_mux.reg);
vdin_meas_div.reg = clk_base + (u64)(vdin_meas_div.reg);
vdin_meas_gate.reg = clk_base + (u64)(vdin_meas_gate.reg);
vdin_meas_mux.reg = clk_base + (unsigned long)(vdin_meas_mux.reg);
vdin_meas_div.reg = clk_base + (unsigned long)(vdin_meas_div.reg);
vdin_meas_gate.reg = clk_base + (unsigned long)(vdin_meas_gate.reg);
/* cts_amclk */
amclk_mux.reg = clk_base + (u64)(amclk_mux.reg);
amclk_div.reg = clk_base + (u64)(amclk_div.reg);
amclk_gate.reg = clk_base + (u64)(amclk_gate.reg);
amclk_mux.reg = clk_base + (unsigned long)(amclk_mux.reg);
amclk_div.reg = clk_base + (unsigned long)(amclk_div.reg);
amclk_gate.reg = clk_base + (unsigned long)(amclk_gate.reg);
/* cts_pdm */
pdm_mux.reg = clk_base + (u64)(pdm_mux.reg);
pdm_div.reg = clk_base + (u64)(pdm_div.reg);
pdm_gate.reg = clk_base + (u64)(pdm_gate.reg);
pdm_mux.reg = clk_base + (unsigned long)(pdm_mux.reg);
pdm_div.reg = clk_base + (unsigned long)(pdm_div.reg);
pdm_gate.reg = clk_base + (unsigned long)(pdm_gate.reg);
/* cts_clk_i958 */
i958_mux.reg = clk_base + (u64)(i958_mux.reg);
i958_div.reg = clk_base + (u64)(i958_div.reg);
i958_gate.reg = clk_base + (u64)(i958_gate.reg);
i958_mux.reg = clk_base + (unsigned long)(i958_mux.reg);
i958_div.reg = clk_base + (unsigned long)(i958_div.reg);
i958_gate.reg = clk_base + (unsigned long)(i958_gate.reg);
/*clk_i958 spdif*/
i958_comp_spdif.reg = clk_base + (u64)(i958_comp_spdif.reg);
i958_comp_spdif.reg = clk_base + (unsigned long)(i958_comp_spdif.reg);
/* cts_pclk_mclk */
pcm_mclk_mux.reg = clk_base + (u64)(pcm_mclk_mux.reg);
pcm_mclk_div.reg = clk_base + (u64)(pcm_mclk_div.reg);
pcm_mclk_gate.reg = clk_base + (u64)(pcm_mclk_gate.reg);
pcm_mclk_mux.reg = clk_base + (unsigned long)(pcm_mclk_mux.reg);
pcm_mclk_div.reg = clk_base + (unsigned long)(pcm_mclk_div.reg);
pcm_mclk_gate.reg = clk_base + (unsigned long)(pcm_mclk_gate.reg);
/* cts_pclk_sclk */
pcm_sclk_div.reg = clk_base + (u64)(pcm_sclk_div.reg);
pcm_sclk_gate.reg = clk_base + (u64)(pcm_sclk_gate.reg);
pcm_sclk_div.reg = clk_base + (unsigned long)(pcm_sclk_div.reg);
pcm_sclk_gate.reg = clk_base + (unsigned long)(pcm_sclk_gate.reg);
/* cts_sar_adc_clk */
gxl_saradc_mux.reg = clk_base + (u64)(gxl_saradc_mux.reg);
gxl_saradc_div.reg = clk_base + (u64)(gxl_saradc_div.reg);
gxl_saradc_gate.reg = clk_base + (u64)(gxl_saradc_gate.reg);
gxl_saradc_mux.reg = clk_base + (unsigned long)(gxl_saradc_mux.reg);
gxl_saradc_div.reg = clk_base + (unsigned long)(gxl_saradc_div.reg);
gxl_saradc_gate.reg = clk_base + (unsigned long)(gxl_saradc_gate.reg);
clks[CLKID_VDIN_MEAS_COMP] = clk_register_composite(NULL,
"vdin_meas_composite",

27
drivers/amlogic/clk/gxl/clk_sdemmc.c
View File

@@ -183,15 +183,24 @@ void amlogic_init_sdemmc(void)
{
/* Populate base address for reg */
pr_info("%s: register amlogic sdemmc clk\n", __func__);
sd_emmc_p0_mux_A.reg = clk_base + (u64)(sd_emmc_p0_mux_A.reg);
sd_emmc_p0_div_A.reg = clk_base + (u64)(sd_emmc_p0_div_A.reg);
sd_emmc_p0_gate_A.reg = clk_base + (u64)(sd_emmc_p0_gate_A.reg);
sd_emmc_p0_mux_B.reg = clk_base + (u64)(sd_emmc_p0_mux_B.reg);
sd_emmc_p0_div_B.reg = clk_base + (u64)(sd_emmc_p0_div_B.reg);
sd_emmc_p0_gate_B.reg = clk_base + (u64)(sd_emmc_p0_gate_B.reg);
sd_emmc_p0_mux_C.reg = clk_base + (u64)(sd_emmc_p0_mux_C.reg);
sd_emmc_p0_div_C.reg = clk_base + (u64)(sd_emmc_p0_div_C.reg);
sd_emmc_p0_gate_C.reg = clk_base + (u64)(sd_emmc_p0_gate_C.reg);
sd_emmc_p0_mux_A.reg = clk_base
+ (unsigned long)(sd_emmc_p0_mux_A.reg);
sd_emmc_p0_div_A.reg = clk_base
+ (unsigned long)(sd_emmc_p0_div_A.reg);
sd_emmc_p0_gate_A.reg = clk_base
+ (unsigned long)(sd_emmc_p0_gate_A.reg);
sd_emmc_p0_mux_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_mux_B.reg);
sd_emmc_p0_div_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_div_B.reg);
sd_emmc_p0_gate_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_gate_B.reg);
sd_emmc_p0_mux_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_mux_C.reg);
sd_emmc_p0_div_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_div_C.reg);
sd_emmc_p0_gate_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_gate_C.reg);
clks[CLKID_SD_EMMC_A_P0_COMP] = clk_register_composite(NULL,
"sd_emmc_p0_A_comp",

32
drivers/amlogic/clk/gxl/gxl.c
View File

@@ -1061,23 +1061,33 @@ static void __init gxl_clkc_init(struct device_node *np)
gxl_clk_mplls[i]->base = clk_base;
/* Populate the base address for CPU clk */
gxl_cpu_clk.mux.reg = clk_base + (u64)gxl_cpu_clk.mux.reg;
gxl_cpu_fixedpll_p00.reg = clk_base + (u64)gxl_cpu_fixedpll_p00.reg;
gxl_cpu_fixedpll_p01.reg = clk_base + (u64)gxl_cpu_fixedpll_p01.reg;
gxl_cpu_fixedpll_p10.reg = clk_base + (u64)gxl_cpu_fixedpll_p10.reg;
gxl_cpu_fixedpll_p11.reg = clk_base + (u64)gxl_cpu_fixedpll_p11.reg;
gxl_cpu_fixedpll_p0.reg = clk_base + (u64)gxl_cpu_fixedpll_p0.reg;
gxl_cpu_fixedpll_p1.reg = clk_base + (u64)gxl_cpu_fixedpll_p1.reg;
gxl_cpu_fixedpll_p.reg = clk_base + (u64)gxl_cpu_fixedpll_p.reg;
gxl_cpu_clk.mux.reg = clk_base
+ (unsigned long)gxl_cpu_clk.mux.reg;
gxl_cpu_fixedpll_p00.reg = clk_base
+ (unsigned long)gxl_cpu_fixedpll_p00.reg;
gxl_cpu_fixedpll_p01.reg = clk_base
+ (unsigned long)gxl_cpu_fixedpll_p01.reg;
gxl_cpu_fixedpll_p10.reg = clk_base
+ (unsigned long)gxl_cpu_fixedpll_p10.reg;
gxl_cpu_fixedpll_p11.reg = clk_base
+ (unsigned long)gxl_cpu_fixedpll_p11.reg;
gxl_cpu_fixedpll_p0.reg = clk_base
+ (unsigned long)gxl_cpu_fixedpll_p0.reg;
gxl_cpu_fixedpll_p1.reg = clk_base
+ (unsigned long)gxl_cpu_fixedpll_p1.reg;
gxl_cpu_fixedpll_p.reg = clk_base
+ (unsigned long)gxl_cpu_fixedpll_p.reg;
/* Populate the base address for the MPEG clks */
gxl_mpeg_clk_sel.reg = clk_base + (u64)gxl_mpeg_clk_sel.reg;
gxl_mpeg_clk_div.reg = clk_base + (u64)gxl_mpeg_clk_div.reg;
gxl_mpeg_clk_sel.reg = clk_base
+ (unsigned long)gxl_mpeg_clk_sel.reg;
gxl_mpeg_clk_div.reg = clk_base
+ (unsigned long)gxl_mpeg_clk_div.reg;
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(gxl_clk_gates); i++)
gxl_clk_gates[i]->reg = clk_base +
(u64)gxl_clk_gates[i]->reg;
(unsigned long)gxl_clk_gates[i]->reg;
clks = kzalloc(NR_CLKS*sizeof(struct clk *), GFP_KERNEL);
if (!clks) {

2
drivers/amlogic/clk/m8b/clk-mpll.c
View File

@@ -33,7 +33,7 @@
#define to_meson_clk_mpll(_hw) container_of(_hw, struct meson_clk_mpll, hw)
static unsigned long rate_from_params(unsigned long parent_rate,
static unsigned long rate_from_params(u64 parent_rate,
unsigned long sdm,
unsigned long n2)
{

30
drivers/amlogic/clk/m8b/clk_misc.c
View File

@@ -275,30 +275,30 @@ static struct clk_gate pcm_sclk_gate = {
void amlogic_init_misc(void)
{
/* cts_vdin_meas_clk */
vdin_meas_mux.reg = clk_base + (u32)(vdin_meas_mux.reg);
vdin_meas_div.reg = clk_base + (u32)(vdin_meas_div.reg);
vdin_meas_gate.reg = clk_base + (u32)(vdin_meas_gate.reg);
vdin_meas_mux.reg = clk_base + (unsigned long)(vdin_meas_mux.reg);
vdin_meas_div.reg = clk_base + (unsigned long)(vdin_meas_div.reg);
vdin_meas_gate.reg = clk_base + (unsigned long)(vdin_meas_gate.reg);
/* cts_amclk */
amclk_mux.reg = clk_base + (u32)(amclk_mux.reg);
amclk_div.reg = clk_base + (u32)(amclk_div.reg);
amclk_gate.reg = clk_base + (u32)(amclk_gate.reg);
amclk_mux.reg = clk_base + (unsigned long)(amclk_mux.reg);
amclk_div.reg = clk_base + (unsigned long)(amclk_div.reg);
amclk_gate.reg = clk_base + (unsigned long)(amclk_gate.reg);
/* cts_clk_i958 */
i958_mux.reg = clk_base + (u32)(i958_mux.reg);
i958_div.reg = clk_base + (u32)(i958_div.reg);
i958_gate.reg = clk_base + (u32)(i958_gate.reg);
i958_mux.reg = clk_base + (unsigned long)(i958_mux.reg);
i958_div.reg = clk_base + (unsigned long)(i958_div.reg);
i958_gate.reg = clk_base + (unsigned long)(i958_gate.reg);
/*clk_i958 spdif*/
i958_comp_spdif.reg = clk_base + (u32)(i958_comp_spdif.reg);
i958_comp_spdif.reg = clk_base + (unsigned long)(i958_comp_spdif.reg);
/* cts_pclk_mclk */
pcm_mclk_mux.reg = clk_base + (u32)(pcm_mclk_mux.reg);
pcm_mclk_div.reg = clk_base + (u32)(pcm_mclk_div.reg);
pcm_mclk_gate.reg = clk_base + (u32)(pcm_mclk_gate.reg);
pcm_mclk_mux.reg = clk_base + (unsigned long)(pcm_mclk_mux.reg);
pcm_mclk_div.reg = clk_base + (unsigned long)(pcm_mclk_div.reg);
pcm_mclk_gate.reg = clk_base + (unsigned long)(pcm_mclk_gate.reg);
/* cts_pclk_sclk */
pcm_sclk_div.reg = clk_base + (u32)(pcm_sclk_div.reg);
pcm_sclk_gate.reg = clk_base + (u32)(pcm_sclk_gate.reg);
pcm_sclk_div.reg = clk_base + (unsigned long)(pcm_sclk_div.reg);
pcm_sclk_gate.reg = clk_base + (unsigned long)(pcm_sclk_gate.reg);
clks[CLKID_VDIN_MEAS_COMP] = clk_register_composite(NULL,
"vdin_meas_composite",

2
drivers/amlogic/clk/m8b/clkc.h
View File

@@ -39,7 +39,7 @@ struct parm {
};
struct pll_rate_table {
unsigned long rate;
u64 rate;
u16 m;
u16 n;
u16 od;

32
drivers/amlogic/clk/txlx/txlx.c
View File

@@ -973,23 +973,33 @@ static void __init txlx_clkc_init(struct device_node *np)
txlx_clk_mplls[i]->base = clk_base;
/* Populate the base address for CPU clk */
txlx_cpu_clk.mux.reg = clk_base + (u64)txlx_cpu_clk.mux.reg;
txlx_cpu_fixedpll_p00.reg = clk_base + (u64)txlx_cpu_fixedpll_p00.reg;
txlx_cpu_fixedpll_p01.reg = clk_base + (u64)txlx_cpu_fixedpll_p01.reg;
txlx_cpu_fixedpll_p10.reg = clk_base + (u64)txlx_cpu_fixedpll_p10.reg;
txlx_cpu_fixedpll_p11.reg = clk_base + (u64)txlx_cpu_fixedpll_p11.reg;
txlx_cpu_fixedpll_p0.reg = clk_base + (u64)txlx_cpu_fixedpll_p0.reg;
txlx_cpu_fixedpll_p1.reg = clk_base + (u64)txlx_cpu_fixedpll_p1.reg;
txlx_cpu_fixedpll_p.reg = clk_base + (u64)txlx_cpu_fixedpll_p.reg;
txlx_cpu_clk.mux.reg = clk_base
+ (unsigned long)txlx_cpu_clk.mux.reg;
txlx_cpu_fixedpll_p00.reg = clk_base
+ (unsigned long)txlx_cpu_fixedpll_p00.reg;
txlx_cpu_fixedpll_p01.reg = clk_base
+ (unsigned long)txlx_cpu_fixedpll_p01.reg;
txlx_cpu_fixedpll_p10.reg = clk_base
+ (unsigned long)txlx_cpu_fixedpll_p10.reg;
txlx_cpu_fixedpll_p11.reg = clk_base
+ (unsigned long)txlx_cpu_fixedpll_p11.reg;
txlx_cpu_fixedpll_p0.reg = clk_base
+ (unsigned long)txlx_cpu_fixedpll_p0.reg;
txlx_cpu_fixedpll_p1.reg = clk_base
+ (unsigned long)txlx_cpu_fixedpll_p1.reg;
txlx_cpu_fixedpll_p.reg = clk_base
+ (unsigned long)txlx_cpu_fixedpll_p.reg;
/* Populate the base address for the MPEG clks */
txlx_mpeg_clk_sel.reg = clk_base + (u64)txlx_mpeg_clk_sel.reg;
txlx_mpeg_clk_div.reg = clk_base + (u64)txlx_mpeg_clk_div.reg;
txlx_mpeg_clk_sel.reg = clk_base
+ (unsigned long)txlx_mpeg_clk_sel.reg;
txlx_mpeg_clk_div.reg = clk_base
+ (unsigned long)txlx_mpeg_clk_div.reg;
/* Populate base address for gates */
for (i = 0; i < ARRAY_SIZE(txlx_clk_gates); i++)
txlx_clk_gates[i]->reg = clk_base +
(u64)txlx_clk_gates[i]->reg;
(unsigned long)txlx_clk_gates[i]->reg;
if (!clks) {
clks = kzalloc(NR_CLKS*sizeof(struct clk *), GFP_KERNEL);

8
drivers/amlogic/clk/txlx/txlx_ao.c
View File

@@ -109,10 +109,10 @@ static int txlx_aoclkc_probe(struct platform_device *pdev)
return -ENXIO;
}
/* Populate the base address for ao clk */
aoclk81.reg = aoclk_base + (u64)aoclk81.reg;
txlx_saradc_mux.reg = aoclk_base + (u64)txlx_saradc_mux.reg;
txlx_saradc_div.reg = aoclk_base + (u64)txlx_saradc_div.reg;
txlx_saradc_gate.reg = aoclk_base + (u64)txlx_saradc_gate.reg;
aoclk81.reg = aoclk_base + (unsigned long)aoclk81.reg;
txlx_saradc_mux.reg = aoclk_base + (unsigned long)txlx_saradc_mux.reg;
txlx_saradc_div.reg = aoclk_base + (unsigned long)txlx_saradc_div.reg;
txlx_saradc_gate.reg = aoclk_base + (unsigned long)txlx_saradc_gate.reg;
for (clkid = CLKID_AO_BASE; clkid < NR_CLKS; clkid++) {
if (txlx_ao_clk_hws[clkid-CLKID_AO_BASE]) {

6
drivers/amlogic/clk/txlx/txlx_clk_gpu.c
View File

@@ -85,13 +85,13 @@ void meson_init_gpu(void)
/* Populate base address for gpu muxes, divs,gates */
for (i = 0; i < ARRAY_SIZE(txlx_gpu_clk_muxes); i++)
txlx_gpu_clk_muxes[i]->reg = clk_base +
(u64)txlx_gpu_clk_muxes[i]->reg;
(unsigned long)txlx_gpu_clk_muxes[i]->reg;
for (i = 0; i < ARRAY_SIZE(txlx_gpu_clk_divs); i++)
txlx_gpu_clk_divs[i]->reg = clk_base +
(u64)txlx_gpu_clk_divs[i]->reg;
(unsigned long)txlx_gpu_clk_divs[i]->reg;
for (i = 0; i < ARRAY_SIZE(txlx_gpu_clk_gates); i++)
txlx_gpu_clk_gates[i]->reg = clk_base +
(u64)txlx_gpu_clk_gates[i]->reg;
(unsigned long)txlx_gpu_clk_gates[i]->reg;
meson_clk_register_composite(clks, gpu_composite, length);

6
drivers/amlogic/clk/txlx/txlx_clk_media.c
View File

@@ -614,17 +614,17 @@ void meson_txlx_media_init(void)
/* Populate base address for media muxes */
for (i = 0; i < ARRAY_SIZE(txlx_media_clk_muxes); i++)
txlx_media_clk_muxes[i]->reg = clk_base +
(u64)txlx_media_clk_muxes[i]->reg;
(unsigned long)txlx_media_clk_muxes[i]->reg;
/* Populate base address for media divs */
for (i = 0; i < ARRAY_SIZE(txlx_media_clk_divs); i++)
txlx_media_clk_divs[i]->reg = clk_base +
(u64)txlx_media_clk_divs[i]->reg;
(unsigned long)txlx_media_clk_divs[i]->reg;
/* Populate base address for media gates */
for (i = 0; i < ARRAY_SIZE(txlx_media_clk_gates); i++)
txlx_media_clk_gates[i]->reg = clk_base +
(u64)txlx_media_clk_gates[i]->reg;
(unsigned long)txlx_media_clk_gates[i]->reg;
meson_clk_register_composite(clks, m_composite, length);

18
drivers/amlogic/clk/txlx/txlx_clk_sdemmc.c
View File

@@ -62,12 +62,18 @@ void meson_txlx_sdemmc_init(void)
int length = ARRAY_SIZE(sdemmc_comp);
/* Populate base address for reg */
sd_emmc_p0_mux_B.reg = clk_base + (u64)(sd_emmc_p0_mux_B.reg);
sd_emmc_p0_div_B.reg = clk_base + (u64)(sd_emmc_p0_div_B.reg);
sd_emmc_p0_gate_B.reg = clk_base + (u64)(sd_emmc_p0_gate_B.reg);
sd_emmc_p0_mux_C.reg = clk_base + (u64)(sd_emmc_p0_mux_C.reg);
sd_emmc_p0_div_C.reg = clk_base + (u64)(sd_emmc_p0_div_C.reg);
sd_emmc_p0_gate_C.reg = clk_base + (u64)(sd_emmc_p0_gate_C.reg);
sd_emmc_p0_mux_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_mux_B.reg);
sd_emmc_p0_div_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_div_B.reg);
sd_emmc_p0_gate_B.reg = clk_base
+ (unsigned long)(sd_emmc_p0_gate_B.reg);
sd_emmc_p0_mux_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_mux_C.reg);
sd_emmc_p0_div_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_div_C.reg);
sd_emmc_p0_gate_C.reg = clk_base
+ (unsigned long)(sd_emmc_p0_gate_C.reg);
meson_clk_register_composite(clks, sdemmc_comp, length);
}

3
drivers/clk/meson/clk-mpll.c
View File

@@ -75,6 +75,7 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw,
struct parm *p;
unsigned long rate = 0;
unsigned long reg, sdm, n2;
u64 pRate = parent_rate;
p = &mpll->sdm;
reg = readl(mpll->base + p->reg_off);
@@ -84,7 +85,7 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw,
reg = readl(mpll->base + p->reg_off);
n2 = PARM_GET(p->width, p->shift, reg);
rate = (parent_rate * SDM_MAX) / ((SDM_MAX * n2) + sdm);
rate = (pRate * SDM_MAX) / ((SDM_MAX * n2) + sdm);
return rate;
}

2
drivers/clk/meson/clkc.h
View File

@@ -36,7 +36,7 @@ struct parm {
};
struct pll_rate_table {
unsigned long rate;
u64 rate;
u16 m;
u16 n;
u16 od;