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rk29: add clock

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This commit is contained in:
黄涛
2010-10-23 15:45:50 +08:00
parent 2d6ca34280
commit e3ab2a068f
9 changed files with 1878 additions and 20 deletions
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2
arch/arm/Kconfig
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@@ -720,6 +720,8 @@ config ARCH_RK29
bool "Rockchip Soc Rk29"
select HAVE_CLK
select CPU_V7
select HAVE_CLK
select COMMON_CLKDEV
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select ARM_GIC

2
arch/arm/mach-rk29/Makefile
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@@ -1,2 +1,2 @@
obj-y += timer.o io.o devices.o iomux.o
obj-y += timer.o io.o devices.o iomux.o clock.o
obj-$(CONFIG_MACH_RK29SDK) += board-rk29sdk.o

2
arch/arm/mach-rk29/board-rk29sdk.c
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@@ -69,7 +69,7 @@ static void __init machine_rk29_board_init(void)
static void __init machine_rk29_mapio(void)
{
rk29_map_common_io();
//rk29_clock_init();
rk29_clock_init();
//rk29_iomux_init();
}

1681
arch/arm/mach-rk29/clock.c Normal file
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File diff suppressed because it is too large Load Diff

3
arch/arm/mach-rk29/include/mach/board.h
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@@ -18,5 +18,6 @@
#include <linux/types.h>
void __init rk29_map_common_io(void);
void __init rk29_clock_init(void);
#endif
#endif

173
arch/arm/mach-rk29/include/mach/cru.h Normal file
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@@ -0,0 +1,173 @@
/* arch/arm/mach-rk29/include/mach/cru.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_RK29_CRU_H
enum cru_clk_gate
{
/* SCU CLK GATE 0 CON */
CLK_GATE_CORE = 0,
CLK_GATE_CORE_APB,
CLK_GATE_CORE_ATB,
CLK_GATE_CPU_AXI,
CLK_GATE_CPU_AXI2,
CLK_GATE_CPU_AHB,
CLK_GATE_CPU_MATRIX1_AHB,
CLK_GATE_CPU_APB,
CLK_GATE_CPU_ATB,
CLK_GATE_DMA0,
CLK_GATE_DMA1,
CLK_GATE_GIC,
CLK_GATE_IMEM,
CLK_GATE_EBROM = 14,
CLK_GATE_I2S0,
CLK_GATE_I2S1,
CLK_GATE_SPDIF,
CLK_GATE_DDR_PHY,
CLK_GATE_DDR_REG,
CLK_GATE_DDR_CPU,
CLK_GATE_EFUSE,
CLK_GATE_TZPC,
CLK_GATE_TIMER0,
CLK_GATE_GPIO0,
CLK_GATE_UART0,
CLK_GATE_I2C0,
CLK_GATE_DEBUG,
CLK_GATE_TPIU,
CLK_GATE_RTC,
CLK_GATE_PMU,
CLK_GATE_GRF,
/* SCU CLK GATE 1 CON */
CLK_GATE_PEIRPH_AXI = 32,
CLK_GATE_PEIRPH_AHB,
CLK_GATE_PEIRPH_APB,
CLK_GATE_EMEM,
CLK_GATE_USB,
CLK_GATE_DMA2,
CLK_GATE_DDR_PERIPH,
CLK_GATE_PERIPH, /* FIXME */
CLK_GATE_SMC_AXI,
CLK_GATE_SMC,
CLK_GATE_MAC_AHB = 43,
CLK_GATE_MAC_PHY,
CLK_GATE_MAC_TX,
CLK_GATE_MAC_RX,
CLK_GATE_HIF,
CLK_GATE_NANDC,
CLK_GATE_HSADC_AHB,
CLK_GATE_HSADC,
CLK_GATE_SDMMC0_AHB,
CLK_GATE_SDMMC0,
CLK_GATE_SDMMC1_AHB,
CLK_GATE_SDMMC1,
CLK_GATE_EMMC_AHB,
CLK_GATE_EMMC,
CLK_GATE_USBOTG0,
CLK_GATE_USBPHY0,
CLK_GATE_USBOTG1,
CLK_GATE_USBPHY1,
CLK_GATE_UHOST_AHB,
CLK_GATE_UHOST,
CLK_GATE_PID_FILTER,
/* SCU CLK GATE 2 CON */
CLK_GATE_UART1 = 64,
CLK_GATE_UART2,
CLK_GATE_UART3,
CLK_GATE_TIMER1,
CLK_GATE_TIMER2,
CLK_GATE_TIMER3,
CLK_GATE_GPIO1,
CLK_GATE_GPIO2,
CLK_GATE_GPIO3,
CLK_GATE_GPIO4,
CLK_GATE_GPIO5,
CLK_GATE_GPIO6,
CLK_GATE_I2C1,
CLK_GATE_I2C2,
CLK_GATE_I2C3,
CLK_GATE_SPI0,
CLK_GATE_SPI1,
CLK_GATE_VIP_SLAVE = 82,
CLK_GATE_WDT,
CLK_GATE_SARADC,
CLK_GATE_PWM,
CLK_GATE_VIP_BUS,
CLK_GATE_VIP_MATRIX,
CLK_GATE_VIP,
CLK_GATE_VIP_INPUT,
CLK_GATE_JTAG,
/* CRU CLK GATE 3 CON */
CLK_GATE_LCDC_AXI = 96,
CLK_GATE_DDR_LCDC_AXI,
CLK_GATE_LCDC_AHB,
CLK_GATE_LCDC,
CLK_GATE_IPP_AXI,
CLK_GATE_IPP_AHB,
CLK_GATE_EBOOK_AHB,
CLK_GATE_EBOOK,
CLK_GATE_DISPLAY_MATRIX_AXI,
CLK_GATE_DISPLAY_MATRIX_AHB,
CLK_GAET_VEPU_AXI,
CLK_GATE_DDR_VEDU_AXI,
CLK_GATE_VDPU_AXI,
CLK_GATE_DDR_VDPU_AXI,
CLK_GATE_GPU,
CLK_GATE_GPU_AXI,
CLK_GATE_DDR_GPU_AXI,
CLK_GATE_GPU_AHB,
CLK_GATE_VEPU_AHB,
CLK_GATE_VDPU_AHB,
CLK_GATE_CPU_VCODEC_AHB,
CLK_GATE_CPU_DISPLAY_AHB,
CLK_GATE_MAX,
};
/* Register definitions */
#define CRU_APLL_CON 0x00
#define CRU_DPLL_CON 0x04
#define CRU_CPLL_CON 0x08
#define CRU_PPLL_CON 0x0c
#define CRU_MODE_CON 0x10
#define CRU_CLKSEL0_CON 0x14
#define CRU_CLKSEL1_CON 0x18
#define CRU_CLKSEL2_CON 0x1c
#define CRU_CLKSEL3_CON 0x20
#define CRU_CLKSEL4_CON 0x24
#define CRU_CLKSEL5_CON 0x28
#define CRU_CLKSEL6_CON 0x2c
#define CRU_CLKSEL7_CON 0x30
#define CRU_CLKSEL8_CON 0x34
#define CRU_CLKSEL9_CON 0x38
#define CRU_CLKSEL10_CON 0x3c
#define CRU_CLKSEL11_CON 0x40
#define CRU_CLKSEL12_CON 0x44
#define CRU_CLKSEL13_CON 0x48
#define CRU_CLKSEL14_CON 0x4c
#define CRU_CLKSEL15_CON 0x50
#define CRU_CLKSEL16_CON 0x54
#define CRU_CLKSEL17_CON 0x58
#define CRU_CLKGATE0_CON 0x5c
#define CRU_CLKGATE1_CON 0x60
#define CRU_CLKGATE2_CON 0x64
#define CRU_CLKGATE3_CON 0x68
#define CRU_SOFTRST0_CON 0x6c
#define CRU_SOFTRST1_CON 0x70
#define CRU_SOFTRST2_CON 0x74
#endif

3
arch/arm/mach-rk29/include/mach/rk29_iomap.h
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@@ -100,7 +100,8 @@
//CPU AXI 1 APB
#define RK29_CRU_PHYS 0x20000000
#define RK29_CRU_SIZE SZ_16K
#define RK29_CRU_BASE RK29_ADDR_BASE1
#define RK29_CRU_SIZE SZ_4K
#define RK29_PMU_PHYS 0x20004000
#define RK29_PMU_SIZE SZ_16K
#define RK29_GRF_BASE (RK29_ADDR_BASE1+0x8000)

3
arch/arm/mach-rk29/io.c
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@@ -37,9 +37,10 @@ static struct map_desc rk29_io_desc[] __initdata = {
RK29_DEVICE(DDRC),
RK29_DEVICE(UART1),
RK29_DEVICE(GRF),
RK29_DEVICE(CRU),
};
void __init rk29_map_common_io(void)
{
iotable_init(rk29_io_desc, ARRAY_SIZE(rk29_io_desc));
}
}

29
arch/arm/mach-rk29/timer.c
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@@ -20,7 +20,6 @@
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/cpufreq.h>
#include <asm/mach/time.h>
#include <mach/rk29_iomap.h>
@@ -35,8 +34,6 @@
#define TIMER_ENABLE 3
#define TIMER_ENABLE_FREE_RUNNING 1
#define CHECK_VBUS_MS 1000 /* ms */
#define RK_TIMER_ENABLE(n) writel(TIMER_ENABLE, RK29_TIMER0_BASE + 0x2000 * n + TIMER_CONTROL_REG)
#define RK_TIMER_ENABLE_FREE_RUNNING(n) writel(TIMER_ENABLE_FREE_RUNNING, RK29_TIMER0_BASE + 0x2000 * n + TIMER_CONTROL_REG)
#define RK_TIMER_DISABLE(n) writel(TIMER_DISABLE, RK29_TIMER0_BASE + 0x2000 * n + TIMER_CONTROL_REG)
@@ -47,6 +44,8 @@
#define RK_TIMER_READVALUE(n) readl(RK29_TIMER0_BASE + 0x2000 * n + TIMER_CUR_VALUE)
#define RK_TIMER_INT_CLEAR(n) readl(RK29_TIMER0_BASE + 0x2000 * n + TIMER_EOI)
#define RK_TIMER_INT_STATUS(n) readl(RK29_TIMER0_BASE + 0x2000 * n + TIMER_INT_STATUS)
#define TIMER_CLKEVT 0 /* timer0 */
#define IRQ_NR_TIMER_CLKEVT IRQ_TIMER0
#define TIMER_CLKEVT_NAME "timer0"
@@ -55,13 +54,10 @@
#define IRQ_NR_TIMER_CLKSRC IRQ_TIMER1
#define TIMER_CLKSRC_NAME "timer1"
//static struct clk *timer_clk;
static int rk29_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt)
{
RK_TIMER_DISABLE(TIMER_CLKEVT);
RK_TIMER_SETCOUNT(TIMER_CLKEVT, cycles );
RK_TIMER_SETCOUNT(TIMER_CLKEVT, cycles);
RK_TIMER_ENABLE(TIMER_CLKEVT);
return 0;
@@ -113,14 +109,18 @@ static struct irqaction rk29_timer_clockevent_irq = {
static __init int rk29_timer_init_clockevent(void)
{
struct clock_event_device *ce = &rk29_timer_clockevent;
struct clk *clk = clk_get(NULL, TIMER_CLKEVT_NAME);
struct clk *xin24m = clk_get(NULL, "xin24m");
clk_set_parent(clk, xin24m);
clk_enable(clk);
//timer_clk = clk_get(NULL, "timer");
RK_TIMER_DISABLE(TIMER_CLKEVT);
setup_irq(rk29_timer_clockevent_irq.irq, &rk29_timer_clockevent_irq);
ce->mult = div_sc(24000000, NSEC_PER_SEC, ce->shift);
ce->max_delta_ns = clockevent_delta2ns(0xFFFFFFFFUL, ce); // max pclk < 256MHz
ce->max_delta_ns = clockevent_delta2ns(0xFFFFFFFFUL, ce);
ce->min_delta_ns = clockevent_delta2ns(1, ce) + 1;
ce->cpumask = cpumask_of(0);
@@ -148,6 +148,11 @@ static void __init rk29_timer_init_clocksource(void)
{
static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n";
struct clocksource *cs = &rk29_timer_clocksource;
struct clk *clk = clk_get(NULL, TIMER_CLKSRC_NAME);
struct clk *xin24m = clk_get(NULL, "xin24m");
clk_set_parent(clk, xin24m);
clk_enable(clk);
RK_TIMER_DISABLE(TIMER_CLKSRC);
RK_TIMER_SETCOUNT(TIMER_CLKSRC, 0xFFFFFFFF);
@@ -156,7 +161,6 @@ static void __init rk29_timer_init_clocksource(void)
cs->mult = clocksource_hz2mult(24000000, cs->shift);
if (clocksource_register(cs))
printk(err, cs->name);
}
static void __init rk29_timer_init(void)
@@ -169,8 +173,3 @@ struct sys_timer rk29_timer = {
.init = rk29_timer_init
};