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https://github.com/hardkernel/linux.git
synced 2026-04-15 01:50:40 +09:00
ARM: rockchip: rk3288.dtsi indent only
This commit is contained in:
黄涛
@@ -96,8 +96,6 @@
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status = "disabled";
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};
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i2c0: i2c@ff650000 {
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compatible = "rockchip,rk30-i2c";
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reg = <0xff650000 0x1000>;
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@@ -173,30 +171,29 @@
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status = "disabled";
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};
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i2c5: i2c@ff170000 {
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compatible = "rockchip,rk30-i2c";
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reg = <0xff170000 0x1000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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//pinctrl-names = "default", "gpio";
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//pinctrl-0 = <&i2c5_sda &i2c5_scl>;
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//pinctrl-1 = <&i2c5_gpio>;
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//gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
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//clocks = <&clk_gates8 8>;
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rockchip,check-idle = <1>;
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status = "disabled";
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};
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i2c5: i2c@ff170000 {
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compatible = "rockchip,rk30-i2c";
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reg = <0xff170000 0x1000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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//pinctrl-names = "default", "gpio";
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//pinctrl-0 = <&i2c5_sda &i2c5_scl>;
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//pinctrl-1 = <&i2c5_gpio>;
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//gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
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//clocks = <&clk_gates8 8>;
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rockchip,check-idle = <1>;
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status = "disabled";
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};
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edp: edp@ff970000 {
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compatible = "rockchip,rk32-edp";
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reg = <0xff970000 0x4000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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compatible = "rockchip,rk32-edp";
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reg = <0xff970000 0x4000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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hdmi:hdmi@ff980000 {
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hdmi: hdmi@ff980000 {
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compatible = "rockchip,rk3288-hdmi";
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reg = <0xff980000 0x20000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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@@ -205,13 +202,13 @@
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pinctrl-0 = <&i2c5_sda &i2c5_scl>;
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pinctrl-1 = <&i2c5_gpio>;
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status = "disabled";
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};
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};
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fb: fb{
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compatible = "rockchip,rk-fb";
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rockchip,disp-mode = <DUAL>;
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};
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lcdc0:lcdc@ff940000 {
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lcdc0: lcdc@ff940000 {
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compatible = "rockchip,rk3288-lcdc";
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rockchip,prop = <PRMRY>;
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rochchip,pwr18 = <0>;
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@@ -223,7 +220,7 @@
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status = "disabled";
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};
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lcdc1:lcdc@ff930000 {
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lcdc1: lcdc@ff930000 {
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compatible = "rockchip,rk3288-lcdc";
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rockchip,prop = <EXTEND>;
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rockchip,pwr18 = <0>;
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@@ -233,26 +230,26 @@
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pinctrl-0 = <&lcdc0_lcdc>;
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pinctrl-1 = <&lcdc0_gpio>;
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status = "disabled";
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};
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};
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adc: adc@ff100000 {
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compatible = "rockchip,saradc";
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reg = <0xff100000 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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io-channel-ranges;
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rockchip,adc-vref = <1800>;
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clock-frequency = <1000000>;
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clock-names = "saradc", "pclk_saradc";
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status = "disabled";
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};
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adc: adc@ff100000 {
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compatible = "rockchip,saradc";
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reg = <0xff100000 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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#io-channel-cells = <1>;
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io-channel-ranges;
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rockchip,adc-vref = <1800>;
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clock-frequency = <1000000>;
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clock-names = "saradc", "pclk_saradc";
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status = "disabled";
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};
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rga@ff920000 {
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compatible = "rockchip,rga";
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reg = <0xff920000 0x1000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "hclk_rga", "aclk_rga";
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};
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};
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i2s: rockchip-i2s@0xff890000 {
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compatible = "rockchip-i2s";
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@@ -283,7 +280,8 @@
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// pinctrl-names = "default";
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// pinctrl-0 = <&spdif_tx>;
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};
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ion: ion{
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ion: ion {
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compatible = "rockchip,ion";
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -294,115 +292,115 @@
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reg = <3>;
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};
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};
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mmc: mshc@ff0c0000 {
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compatible = "rockchip,rk_mmc";
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reg = <0xff0c0000 0x4000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
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#address-cells = <1>;
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#size-cells = <0>;
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//pinctrl-names = "default","suspend";
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//pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_cd &sdmmc0_wp &sdmmc0_pwr &sdmmc0_bus1 &sdmmc0_bus4>;
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//pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
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//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
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//clock-names = "hclk_mmc","mmc";
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clock-frequency = <50000000>;
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clock-freq-min-max = <400000 50000000>;
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num-slots = <1>;
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supports-highspeed;
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broken-cd;
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card-detect-delay = <200>;
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pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/
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fifo-depth = <0x100>;
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emmc-compatible = <0>;
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status = "okay";
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compatible = "rockchip,rk_mmc";
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reg = <0xff0c0000 0x4000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
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#address-cells = <1>;
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#size-cells = <0>;
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//pinctrl-names = "default","suspend";
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//pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_cd &sdmmc0_wp &sdmmc0_pwr &sdmmc0_bus1 &sdmmc0_bus4>;
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//pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
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//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
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//clock-names = "hclk_mmc","mmc";
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clock-frequency = <50000000>;
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clock-freq-min-max = <400000 50000000>;
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num-slots = <1>;
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supports-highspeed;
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broken-cd;
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card-detect-delay = <200>;
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pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/
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fifo-depth = <0x100>;
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emmc-compatible = <0>;
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status = "okay";
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};
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sdio0: mshc@ff0d0000 {
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compatible = "rockchip,rk_mmc";
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reg = <0xff0d0000 0x4000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; /*irq=65*/
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#address-cells = <1>;
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#size-cells = <0>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
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//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
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//clock-names = "hclk_sdio0","sdio0";
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clock-frequency = <50000000>;
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clock-freq-min-max = <400000 50000000>;
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num-slots = <1>;
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supports-highspeed;
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fifo-depth = <0x100>;
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emmc-compatible = <0>;
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status = "disabled";
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reg = <0xff0d0000 0x4000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; /*irq=65*/
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#address-cells = <1>;
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#size-cells = <0>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
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//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
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//clock-names = "hclk_sdio0","sdio0";
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clock-frequency = <50000000>;
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clock-freq-min-max = <400000 50000000>;
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num-slots = <1>;
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supports-highspeed;
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fifo-depth = <0x100>;
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emmc-compatible = <0>;
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status = "disabled";
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};
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sdio1: mshc@ff0e0000 {
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compatible = "rockchip,rk_mmc";
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reg = <0xff0e0000 0x4000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; /*irq=66*/
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#address-cells = <1>;
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#size-cells = <0>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
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//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
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//clock-names = "hclk_sdio1","sdio1";
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clock-frequency = <50000000>;
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clock-freq-min-max = <400000 50000000>;
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num-slots = <1>;
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supports-highspeed;
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fifo-depth = <0x100>;
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emmc-compatible = <0>;
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status = "disabled";
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reg = <0xff0e0000 0x4000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; /*irq=66*/
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#address-cells = <1>;
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#size-cells = <0>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
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//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
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//clock-names = "hclk_sdio1","sdio1";
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clock-frequency = <50000000>;
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clock-freq-min-max = <400000 50000000>;
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num-slots = <1>;
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supports-highspeed;
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fifo-depth = <0x100>;
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emmc-compatible = <0>;
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status = "disabled";
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};
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emmc: mshc@ff0f0000 {
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compatible = "rockchip,rk_mmc";
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reg = <0xff0f0000 0x4000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; /*irq=67*/
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#address-cells = <1>;
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#size-cells = <0>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
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//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
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//clock-names = "hclk_sdio1","sdio1";
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clock-frequency = <50000000>;
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clock-freq-min-max = <400000 50000000>;
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num-slots = <1>;
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supports-highspeed;
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fifo-depth = <0x100>;
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emmc-compatible = <1>;
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status = "disabled";
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reg = <0xff0f0000 0x4000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; /*irq=67*/
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#address-cells = <1>;
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#size-cells = <0>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
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//clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
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//clock-names = "hclk_sdio1","sdio1";
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clock-frequency = <50000000>;
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clock-freq-min-max = <400000 50000000>;
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num-slots = <1>;
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supports-highspeed;
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fifo-depth = <0x100>;
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emmc-compatible = <1>;
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status = "disabled";
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};
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vpu:vpu_service@ff9a0000 {
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vpu: vpu_service@ff9a0000 {
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compatible = "vpu_service";
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reg = <0xff9a0000 0x800>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irq_enc", "irq_dec";
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/*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
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clock-names = "aclk_vcodec", "hclk_vcodec"; */
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name = "vpu_service";
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status = "disabled";
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irq_enc", "irq_dec";
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/*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
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clock-names = "aclk_vcodec", "hclk_vcodec"; */
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name = "vpu_service";
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status = "disabled";
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};
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hevc:hevc_service@ff9c0000 {
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compatible = "rockchip,hevc_service";
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reg = <0xff9c0000 0x800>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irq_dec";
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/*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
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clock-names = "aclk_vcodec", "hclk_vcodec";*/
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name = "hevc_service";
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status = "disabled";
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};
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hevc: hevc_service@ff9c0000 {
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compatible = "rockchip,hevc_service";
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reg = <0xff9c0000 0x800>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "irq_dec";
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/*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
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clock-names = "aclk_vcodec", "hclk_vcodec";*/
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name = "hevc_service";
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status = "disabled";
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};
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iep:iep@ff900000 {
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compatible = "rockchip,iep";
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reg = <0xff900000 0x800>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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/*clocks = <&clk_gate3 9>, <&clk_gate3 10>;
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clock_names = "aclk_iep", "hclk_iep";*/
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iep: iep@ff900000 {
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compatible = "rockchip,iep";
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reg = <0xff900000 0x800>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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/*clocks = <&clk_gate3 9>, <&clk_gate3 10>;
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clock_names = "aclk_iep", "hclk_iep";*/
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status = "disabled";
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};
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};
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Block a user