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clk_measure: tm2: add clock measurement [1/1]

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PD#SWPL-5636

Problem:
the clock measurement in SoC is changed

Solution:
add clock measurement

Verify:
test passed on ptm

Change-Id: I2325e9c76e27498c258449624b01f0deff9f7684
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
This commit is contained in:
Jian Hu
2019-03-26 11:27:32 +08:00
committed by Jianxiong Pan
parent 7625b3d031
commit e3f35d98bc
4 changed files with 185 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/clock/amlogic,meson-clkc.txt
View File

@@ -26,6 +26,8 @@ Required Properties:
"amlogic,sm1-clkc-2" - for sm1 ee part2 clock
"amlogic,sm1-aoclkc" - for sm1 ao clock
"amlogic,tm2-clkc" - for tm2 additional ee clock
"amlogic,tm2-clkc" - for tm2 additional ee clock
"amlogic,tm2-measure" - for tm2 clock measurement
- reg: physical base address of the clock controller and length of memory
mapped region.

2
arch/arm/boot/dts/amlogic/mesontm2.dtsi
View File

@@ -709,7 +709,7 @@
ranges = <0x0 0xffd00000 0x27000>;
clk-measure@18004 {
compatible = "amlogic,tl1-measure";
compatible = "amlogic,tm2-measure";
reg = <0x18004 0x4 0x1800c 0x4>;
};

2
arch/arm64/boot/dts/amlogic/mesontm2.dtsi
View File

@@ -689,7 +689,7 @@
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x27000>;
clk-measure@18004 {
compatible = "amlogic,tl1-measure";
compatible = "amlogic,tm2-measure";
reg = <0x0 0x18004 0x0 0x4 0x0 0x1800c 0x0 0x4>;
ringctrl = <0xff6345fc>;
};

182
drivers/amlogic/clk/clk_measure.c
View File

@@ -1623,18 +1623,198 @@ static const char * const sm1_table[] = {
[0] = "am_ring_osc_clk_out_ee[0]",
};
static const char * const tm2_table[] = {
[171] = "pcie1_clk_inn",
[170] = "pcie1_clk_inp",
[169] = "pcie0_phy_bs_clk",
[168] = "pcie1_phy_bs_clk",
[167] = "au_dac1l_en_dac_clk",
[166] = "au_dac1r_en_dac_clk",
[165] = "au_dac2l_en_dac_clk",
[164] = "au_dac2r_en_dac_clk",
[163] = "hdmirx_aud_sck",
[162] = "audio_t0_hdmitx_bclk",
[161] = "audio_t0_hdmitx_spdif_clk",
[160] = "dspb_clk",
[159] = "dspa_clk",
[157] = "vpu_dmc_clk",
[156] = "p22_usb2_clkout",
[155] = "p21_usb2_clkout",
[154] = "p20_usb2_clkout",
[153] = "c_alocker_out_clk",
[152] = "c_alocker_in_clk",
[151] = "dpll_intclk",
[150] = "dpll_clk_a2",
[149] = "dpll_clk_b2",
[148] = "dpll_clk_b3",
[147] = "pcie0_clk_inp",
[146] = "pcie0_clk_inn",
[145] = "hdmitx_sys_clk",
[144] = "ts_pll_clk",
[143] = "mainclk",
[142] = "demode_ts_clk",
[141] = "ts_ddr_clk",
[140] = "audio_toacodec_bclk",
[139] = "aud_adc_clk_g128x",
[138] = "vipnanoq_core_clk",
[137] = "atv_dmd_i2c_sclk",
[136] = "vipnanoq_axi_clk",
[135] = "tvfe_sample_clk",
[134] = "adc_extclk_in",
[133] = "atv_dmd_mono_clk_32",
[132] = "audio_toacode_mclk",
[131] = "ts_sar_clk",
[130] = "au_dac2_clk_gf128x",
[129] = "lvds_fifo_clk",
[128] = "cts_tcon_pll_clk",
[127] = "hdmirx_vid_clk",
[126] = "sar_ring_osc_clk",
[125] = "cts_hdmi_axi_clk",
[124] = "cts_demod_core_clk",
[123] = "mod_audio_pdm_dclk_o",
[122] = "audio_spdifin_mst_clk",
[121] = "audio_spdifout_mst_clk",
[120] = "audio_spdifout_b_mst_clk",
[119] = "audio_pdm_sysclk",
[118] = "audio_resamplea_clk",
[117] = "audio_resampleb_clk",
[116] = "audio_tdmin_a_sclk",
[115] = "audio_tdmin_b_sclk",
[114] = "audio_tdmin_c_sclk",
[113] = "audio_tdmin_lb_sclk",
[112] = "audio_tdmout_a_sclk",
[111] = "audio_tdmout_b_sclk",
[110] = "audio_tdmout_c_sclk",
[109] = "o_vad_clk",
[108] = "acodec_i2sout_bclk",
[107] = "au_dac_clk_g128x",
[106] = "ephy_test_clk",
[105] = "am_ring_osc_clk_out_ee[9]",
[104] = "am_ring_osc_clk_out_ee[8]",
[103] = "am_ring_osc_clk_out_ee[7]",
[102] = "am_ring_osc_clk_out_ee[6]",
[101] = "am_ring_osc_clk_out_ee[5]",
[100] = "am_ring_osc_clk_out_ee[4]",
[99] = "am_ring_osc_clk_out_ee[3]",
[98] = "cts_ts_clk",
[97] = "cts_vpu_clkb_tmp",
[96] = "cts_vpu_clkb",
[95] = "eth_phy_plltxclk",
[94] = "eth_phy_exclk",
[93] = "sys_cpu_ring_osc_clk[3]",
[92] = "sys_cpu_ring_osc_clk[2]",
[91] = "hdmirx_audmeas_clk",
[90] = "am_ring_osc_clk_out_ee[11]",
[89] = "am_ring_osc_clk_out_ee[10]",
[88] = "cts_hdmirx_meter_clk",
[87] = "hdmitx_tmds_clk",
[86] = "cts_hdmirx_modet_clk",
[85] = "cts_hdmirx_acr_ref_clk",
[84] = "co_tx_cl",
[83] = "co_rx_clk",
[82] = "cts_ge2d_clk",
[81] = "cts_vapbclk",
[80] = "rng_ring_osc_clk[3]",
[79] = "rng_ring_osc_clk[2]",
[78] = "rng_ring_osc_clk[1]",
[77] = "rng_ring_osc_clk[0]",
[76] = "hdmix_aud_clk",
[75] = "cts_hevcf_clk",
[74] = "hdmirx_aud_pll_clk",
[73] = "cts_pwm_C_clk",
[72] = "cts_pwm_D_clk",
[71] = "cts_pwm_E_clk",
[70] = "cts_pwm_F_clk",
[69] = "cts_hdcp22_skpclk",
[68] = "cts_hdcp22_esmclk",
[67] = "hdmirx_apll_clk_audio",
[66] = "cts_vid_lock_clk",
[65] = "cts_spicc_0_clk",
[64] = "cts_spicc_1_clk",
[63] = "hdmirx_tmds_clk",
[62] = "cts_hevcb_clk",
[61] = "gpio_clk_msr",
[60] = "cts_hdmirx_aud_pll_clk",
[59] = "cts_hcodec_clk",
[58] = "cts_vafe_datack",
[57] = "cts_atv_dmd_vdac_clk",
[56] = "cts_atv_dmd_sys_clk",
[55] = "vid_pll_div_clk_out",
[54] = "cts_vpu_clkc",
[53] = "ddr_2xclk",
[52] = "cts_sd_emmc_clk_B",
[51] = "cts_sd_emmc_clk_C",
[50] = "mp3_clk_out",
[49] = "mp2_clk_out",
[48] = "mp1_clk_out",
[47] = "ddr_dpll_pt_clk",
[46] = "cts_vpu_clk",
[45] = "cts_pwm_A_clk",
[44] = "cts_pwm_B_clk",
[43] = "fclk_div5",
[42] = "mp0_clk_out",
[41] = "mac_eth_rx_clk_rmii",
[40] = "cts_hdmirx_cfg_clk",
[39] = "cts_bt656_clk0",
[38] = "cts_vdin_meas_clk",
[37] = "cts_cdac_clk_c",
[36] = "cts_hdmi_tx_pixel_clk",
[35] = "cts_mali_clk",
[34] = "eth_mppll_50m_ckout",
[33] = "sys_cpu_ring_osc_clk[1]",
[32] = "cts_vdec_clk",
[31] = "mpll_clk_test_out",
[30] = "hdmirx_cable_clk",
[29] = "hdmirx_apll_clk_out_div",
[28] = "cts_sar_adc_clk",
[27] = "co_clkin_to_mac",
[26] = "sc_clk_int",
[25] = "cts_eth_clk_rmii",
[24] = "cts_eth_clk125Mhz",
[23] = "mpll_clk_50m",
[22] = "mac_eth_phy_ref_clk",
[21] = "lcd_an_clk_ph3",
[20] = "rtc_osc_clk_out",
[19] = "lcd_an_clk_ph2",
[18] = "sys_cpu_clk_div16",
[17] = "sys_pll_div16",
[16] = "cts_FEC_CLK_2",
[15] = "cts_FEC_CLK_1",
[14] = "cts_FEC_CLK_0",
[13] = "mod_tcon_clko",
[12] = "hifi_pll_clk",
[11] = "mac_eth_tx_clk",
[10] = "cts_vdac_clk",
[9] = "cts_encl_clk",
[8] = "cts_encp_clk",
[7] = "clk81",
[6] = "cts_enci_clk",
[5] = "gp1_pll_clk",
[4] = "gp0_pll_clk",
[3] = "sys_cpu_ring_osc_clk[0]",
[2] = "am_ring_osc_clk_out_ee[2]",
[1] = "am_ring_osc_clk_out_ee[1]",
[0] = "am_ring_osc_clk_out_ee[0]",
};
static const struct meson_clkmsr_data sm1_data = {
.clk_table = sm1_table,
.table_size = ARRAY_SIZE(sm1_table),
.clk_msr_function = gxbb_clk_util_clk_msr,
};
static const struct meson_clkmsr_data tm2_data = {
.clk_table = tm2_table,
.table_size = ARRAY_SIZE(tm2_table),
.clk_msr_function = gxbb_clk_util_clk_msr,
};
static const struct of_device_id meson_clkmsr_dt_match[] = {
{ .compatible = "amlogic, gxl_measure",},
{ .compatible = "amlogic, m8b_measure",},
{ .compatible = "amlogic,tl1-measure", .data = &tl1_data },
{ .compatible = "amlogic, sm1-measure", .data = &sm1_data },
{ .compatible = "amlogic,tm2-measure", .data = &tm2_data },
{},
};