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Merge tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes

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RISC-V Devicetrees for v6.6-final

A single fix for the Starfive VisionFive 2 platform so that chip select
for SPI matches the vendor documentation.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: visionfive 2: correct spi's ss pin

Link: https://lore.kernel.org/r/20231015-outmatch-tragedy-228f91d396b5@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2023-10-16 23:14:09 +02:00
parent 5e24617f66 cf98fe6b57
commit e4078ebbdd
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
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@@ -431,7 +431,7 @@
};
ss-pins {
pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS,
pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
GPOEN_ENABLE,
GPI_SYS_SPI0_FSS)>;
bias-disable;