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phy: rockchip: csi2-dphy: add clk invert control for rv1106

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Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I67d5ae91177380e7447f87360b0feed37986f0d6
This commit is contained in:
Zefa Chen
2022-03-23 11:27:32 +08:00
committed by Tao Huang
parent fbb4903f5d
commit e5421eb70d
1 changed files with 10 additions and 0 deletions
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10
drivers/phy/rockchip/phy-rockchip-csi2-dphy-hw.c
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@@ -51,6 +51,8 @@
#define CSI2_DPHY_CTRL_LANE_ENABLE (0x00)
#define CSI2_DPHY_CLK1_LANE_EN (0x2C)
#define CSI2_DPHY_DUAL_CAL_EN (0x80)
#define CSI2_DPHY_CLK_INV (0X84)
#define CSI2_DPHY_CLK_WR_THS_SETTLE (0x160)
#define CSI2_DPHY_CLK_CALIB_EN (0x168)
#define CSI2_DPHY_LANE0_WR_THS_SETTLE (0x1e0)
@@ -221,6 +223,7 @@ enum csi2dphy_reg_id {
CSI2PHY_PATH0_LVDS_MODEL,
CSI2PHY_PATH1_MODEL,
CSI2PHY_PATH1_LVDS_MODEL,
CSI2PHY_CLK_INV,
};
#define HIWORD_UPDATE(val, mask, shift) \
@@ -466,6 +469,7 @@ static const struct csi2dphy_reg rv1106_csi2dphy_regs[] = {
[CSI2PHY_PATH0_LVDS_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH0_LVDS_MODE_SEL),
[CSI2PHY_PATH1_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH1_MODE_SEL),
[CSI2PHY_PATH1_LVDS_MODEL] = CSI2PHY_REG(CSI2_DPHY_PATH1_LVDS_MODE_SEL),
[CSI2PHY_CLK_INV] = CSI2PHY_REG(CSI2_DPHY_CLK_INV),
};
/* These tables must be sorted by .range_h ascending. */
@@ -826,6 +830,12 @@ static int csi2_dphy_hw_stream_on(struct csi2_dphy *dphy,
write_csi2_dphy_reg(hw, CSI2PHY_PATH1_LVDS_MODEL, (lvds_width << 4) | 0X01);
}
}
if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
if (hw->lane_mode == LANE_MODE_FULL)
write_csi2_dphy_reg(hw, CSI2PHY_CLK_INV, 0x04);
else
write_csi2_dphy_reg(hw, CSI2PHY_CLK_INV, 0x14);
}
}
atomic_inc(&hw->stream_cnt);