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camsys_drv: v0.d.0

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ddl
2014-06-10 09:43:23 +08:00
parent 649662820c
commit e62ea88ccb
3 changed files with 14 additions and 3 deletions
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6
drivers/media/video/rk_camsys/camsys_internal.h
View File

@@ -78,9 +78,11 @@
*v0.b.0:
1) control ddr freq by marvin self other than by clk unit.
*v0.c.0:
1) add flash_trigger_out control
* 1) add flash_trigger_out control
*v0.d.0:
* 1) add Isp_SoftRst for rk3288;
*/
#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0,0xc,0)
#define CAMSYS_DRIVER_VERSION KERNEL_VERSION(0,0xd,0)
#define CAMSYS_PLATFORM_DRV_NAME "RockChip-CamSys"

8
drivers/media/video/rk_camsys/camsys_soc_priv.c
View File

@@ -37,9 +37,15 @@ static int camsys_rk3288_cfg (camsys_soc_cfg_t cfg_cmd, void* cfg_para)
break;
}
case Isp_SoftRst:
case Isp_SoftRst: /* ddl@rock-chips.com: v0.d.0 */
{
para_int = (unsigned int*)cfg_para;
if (para_int)
cru_writel(0x40004000,0x1d0);
else
cru_writel(0x40000000,0x1d0);
camsys_trace(1, "Isp_SoftRst: %d",para_int);
break;
}

3
drivers/media/video/rk_camsys/camsys_soc_rk3288.h
View File

@@ -97,6 +97,9 @@
#define read_grf_reg(addr) __raw_readl(addr+RK_GRF_VIRT)
#define mask_grf_reg(addr, msk, val) write_grf_reg(addr,(val)|((~(msk))&read_grf_reg(addr)))
#define cru_writel(v, o) do {writel(v, RK_CRU_VIRT + (o)); dsb();} \
while (0)
#define write_csihost_reg(addr, val) __raw_writel(val, addr+IOMEM(phy_virt))
#define read_csihost_reg(addr) __raw_readl(addr+IOMEM(phy_virt))