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tl1: bringup: demux && async fifo [1/1]

Browse Source 
PD#SWPL-2187

Problem:
add 1 ts input && 1 async_fifo && 1 s2p2

Solution:
Comptible with other platform

Verify:
Verified on TL1 ref board

Change-Id: I4100dd7ac07f95cf0d671f251d1ce67ba1111a99
Signed-off-by: Chuangcheng Peng <chuangcheng.peng@amlogic.com>
This commit is contained in:
Chuangcheng Peng
2018-11-16 18:16:24 +08:00
committed by Dongjin Kim
parent 0967e5f5a6
commit e70ee8c04d
6 changed files with 250 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

131
drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dmx.c
View File

@@ -253,14 +253,17 @@ dmx_write_reg(int r, u32 v)
#define WRITE_PERI_REG WRITE_CBUS_REG
#define READ_ASYNC_FIFO_REG(i, r)\
((i) ? READ_PERI_REG(ASYNC_FIFO2_##r) : READ_PERI_REG(ASYNC_FIFO_##r))
((i) ? ((i-1)?READ_PERI_REG(ASYNC_FIFO1_##r):\
READ_PERI_REG(ASYNC_FIFO2_##r)) : READ_PERI_REG(ASYNC_FIFO_##r))
#define WRITE_ASYNC_FIFO_REG(i, r, d)\
do {\
if (i == 1) {\
WRITE_PERI_REG(ASYNC_FIFO2_##r, d);\
} else {\
if (i == 2) {\
WRITE_PERI_REG(ASYNC_FIFO1_##r, d);\
} else if (i == 0) {\
WRITE_PERI_REG(ASYNC_FIFO_##r, d);\
} else {\
WRITE_PERI_REG(ASYNC_FIFO2_##r, d);\
} \
} while (0)
@@ -1481,6 +1484,7 @@ static void dvr_irq_bh_handler(unsigned long arg)
if (dvb && afifo->source >= AM_DMX_0 && afifo->source < AM_DMX_MAX) {
dmx = &dvb->dmx[afifo->source];
// pr_inf("async fifo %d irq, source:%d\n", afifo->id,afifo->source);
if (dmx->init && dmx->record) {
struct aml_swfilter *sf = &dvb->swfilter;
int issf = 0;
@@ -1525,8 +1529,8 @@ static void stb_enable(struct aml_dvb *dvb)
{
int out_src, des_in, en_des, fec_clk, hiu, dec_clk_en;
int src, tso_src, i;
u32 fec_s0, fec_s1;
u32 invert0, invert1;
u32 fec_s0, fec_s1,fec_s2;
u32 invert0, invert1, invert2;
u32 data;
switch (dvb->stb_source) {
@@ -1557,6 +1561,10 @@ static void stb_enable(struct aml_dvb *dvb)
fec_clk = tsfile_clkdiv;
hiu = 0;
break;
case AM_TS_SRC_TS3:
fec_clk = tsfile_clkdiv;
hiu = 0;
break;
case AM_TS_SRC_S_TS0:
fec_clk = tsfile_clkdiv;
hiu = 0;
@@ -1627,11 +1635,18 @@ static void stb_enable(struct aml_dvb *dvb)
case AM_TS_SRC_TS2:
out_src = 2;
break;
case AM_TS_SRC_TS3:
out_src = 3;
break;
case AM_TS_SRC_S_TS0:
case AM_TS_SRC_S_TS1:
case AM_TS_SRC_S_TS2:
out_src = 6;
break;
case AM_TS_SRC_S_TS1:
out_src = 5;
break;
case AM_TS_SRC_S_TS2:
out_src = 4;
break;
case AM_TS_SRC_HIU:
out_src = 7;
break;
@@ -1644,14 +1659,18 @@ static void stb_enable(struct aml_dvb *dvb)
fec_s0 = 0;
fec_s1 = 0;
fec_s2 = 0;
invert0 = 0;
invert1 = 0;
invert2 = 0;
for (i = 0; i < TS_IN_COUNT; i++) {
for (i = 0; i < dvb->ts_in_total_count; i++) {
if (dvb->ts[i].s2p_id == 0)
fec_s0 = i;
else if (dvb->ts[i].s2p_id == 1)
fec_s1 = i;
else if (dvb->ts[i].s2p_id == 2)
fec_s2 = i;
}
invert0 = dvb->s2p[0].invert;
@@ -1667,6 +1686,15 @@ static void stb_enable(struct aml_dvb *dvb)
(invert0 << INVERT_S2P0_FEC_CLK) |
(fec_s0 << S2P0_FEC_SERIAL_SEL));
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TL1) {
invert2 = dvb->s2p[2].invert;
WRITE_MPEG_REG(STB_S2P2_CONFIG,
(invert2 << INVERT_S2P2_FEC_CLK) |
(fec_s2 << S2P2_FEC_SERIAL_SEL));
}
if (dvb->reset_flag)
hiu = 0;
/* invert ts out clk,add ci model need add this*/
@@ -2628,7 +2656,7 @@ static int dmx_get_record_flag(struct aml_dmx *dmx)
struct aml_dvb *dvb = (struct aml_dvb *)dmx->demux.priv;
/*Check whether a async fifo connected to this dmx */
for (i = 0; i < ASYNCFIFO_COUNT; i++) {
for (i = 0; i < dvb->async_fifo_total_count; i++) {
if (!dvb->asyncfifo[i].init)
continue;
if ((dvb->asyncfifo[i].source == dmx->id)
@@ -2681,7 +2709,7 @@ static int dmx_enable(struct aml_dmx *dmx)
int fec_core_sel = 0;
int set_stb = 0, fec_s = 0;
int s2p_id;
u32 invert0 = 0, invert1 = 0, fec_s0 = 0, fec_s1 = 0;
u32 invert0 = 0, invert1 = 0, invert2 = 0, fec_s0 = 0, fec_s1 = 0, fec_s2 = 0;
u32 use_sop = 0;
record = dmx_get_record_flag(dmx);
@@ -2720,7 +2748,8 @@ static int dmx_enable(struct aml_dmx *dmx)
s2p_id = dvb->ts[2].s2p_id;
fec_ctrl = dvb->ts[2].control;
}
fec_sel = (s2p_id == 1) ? 5 : 6;
//fec_sel = (s2p_id == 1) ? 5 : 6;
fec_sel = 6 - s2p_id;
record = record ? 1 : 0;
set_stb = 1;
fec_s = dmx->source - AM_TS_SRC_S_TS0;
@@ -2809,11 +2838,13 @@ static int dmx_enable(struct aml_dmx *dmx)
u32 v = READ_MPEG_REG(STB_TOP_CONFIG);
int i;
for (i = 0; i < TS_IN_COUNT; i++) {
for (i = 0; i < dvb->ts_in_total_count; i++) {
if (dvb->ts[i].s2p_id == 0)
fec_s0 = i;
else if (dvb->ts[i].s2p_id == 1)
fec_s1 = i;
else if (dvb->ts[i].s2p_id == 2)
fec_s2 = i;
}
invert0 = dvb->s2p[0].invert;
@@ -2829,6 +2860,18 @@ static int dmx_enable(struct aml_dmx *dmx)
(fec_s1 << S2P1_FEC_SERIAL_SEL) |
(invert1 << INVERT_S2P1_FEC_CLK);
WRITE_MPEG_REG(STB_TOP_CONFIG, v);
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_TL1) {
invert2 = dvb->s2p[2].invert;
//add s2p2 config
v = READ_MPEG_REG(STB_S2P2_CONFIG);
v &= ~((0x3 << S2P2_FEC_SERIAL_SEL) |
(0x1f << INVERT_S2P2_FEC_CLK));
v |= (fec_s2 << S2P2_FEC_SERIAL_SEL) |
(invert2 << INVERT_S2P2_FEC_CLK);
WRITE_MPEG_REG(STB_S2P2_CONFIG, v);
}
}
/*Initialize the registers */
@@ -3284,11 +3327,12 @@ static void reset_async_fifos(struct aml_dvb *dvb)
{
struct aml_asyncfifo *low_dmx_fifo = NULL;
struct aml_asyncfifo *high_dmx_fifo = NULL;
struct aml_asyncfifo *highest_dmx_fifo = NULL;
int i, j;
int record_enable;
pr_dbg("reset ASYNC FIFOs\n");
for (i = 0; i < ASYNCFIFO_COUNT; i++) {
for (i = 0; i < dvb->async_fifo_total_count; i++) {
if (!dvb->asyncfifo[i].init)
continue;
pr_dbg("Disable ASYNC FIFO id=%d\n", dvb->asyncfifo[i].id);
@@ -3311,7 +3355,7 @@ static void reset_async_fifos(struct aml_dvb *dvb)
if (!dvb->dmx[j].init)
continue;
record_enable = 0;
for (i = 0; i < ASYNCFIFO_COUNT; i++) {
for (i = 0; i < dvb->async_fifo_total_count; i++) {
if (!dvb->asyncfifo[i].init)
continue;
@@ -3325,11 +3369,25 @@ static void reset_async_fifos(struct aml_dvb *dvb)
low_dmx_fifo = &dvb->asyncfifo[i];
} else if (low_dmx_fifo->source >
dvb->asyncfifo[i].source) {
high_dmx_fifo = low_dmx_fifo;
if (!high_dmx_fifo)
high_dmx_fifo = low_dmx_fifo;
else {
highest_dmx_fifo = high_dmx_fifo;
high_dmx_fifo = low_dmx_fifo;
}
low_dmx_fifo = &dvb->asyncfifo[i];
} else if (low_dmx_fifo->source <
dvb->asyncfifo[i].source) {
high_dmx_fifo = &dvb->asyncfifo[i];
if (!high_dmx_fifo)
high_dmx_fifo = &dvb->asyncfifo[i];
else {
if (high_dmx_fifo->source > dvb->asyncfifo[i].source) {
highest_dmx_fifo = high_dmx_fifo;
high_dmx_fifo = &dvb->asyncfifo[i];
} else {
highest_dmx_fifo = &dvb->asyncfifo[i];
}
}
}
break;
@@ -3358,8 +3416,12 @@ static void reset_async_fifos(struct aml_dvb *dvb)
if (low_dmx_fifo) {
async_fifo_set_regs(low_dmx_fifo, 0x3);
if (high_dmx_fifo)
if (high_dmx_fifo) {
async_fifo_set_regs(high_dmx_fifo, 0x2);
if (highest_dmx_fifo)
async_fifo_set_regs(highest_dmx_fifo, 0x0);
}
}
}
@@ -3402,6 +3464,7 @@ void dmx_reset_hw_ex(struct aml_dvb *dvb, int reset_irq)
}
WRITE_MPEG_REG(STB_TOP_CONFIG, 0);
WRITE_MPEG_REG(STB_S2P2_CONFIG, 0);
for (id = 0; id < DMX_DEV_COUNT; id++) {
u32 version, data;
@@ -4572,17 +4635,22 @@ int aml_dmx_hw_set_source(struct dmx_demux *demux, dmx_source_t src)
case DMX_SOURCE_FRONT0:
hw_src =
(dvb->ts[0].mode ==
AM_TS_SERIAL) ? AM_TS_SRC_S_TS0 : AM_TS_SRC_TS0;
AM_TS_SERIAL) ? (dvb->ts[0].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS0;
break;
case DMX_SOURCE_FRONT1:
hw_src =
(dvb->ts[1].mode ==
AM_TS_SERIAL) ? AM_TS_SRC_S_TS1 : AM_TS_SRC_TS1;
AM_TS_SERIAL) ? (dvb->ts[1].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS1;
break;
case DMX_SOURCE_FRONT2:
hw_src =
(dvb->ts[2].mode ==
AM_TS_SERIAL) ? AM_TS_SRC_S_TS2 : AM_TS_SRC_TS2;
AM_TS_SERIAL) ? (dvb->ts[2].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS2;
break;
case DMX_SOURCE_FRONT3:
hw_src =
(dvb->ts[3].mode ==
AM_TS_SERIAL) ? (dvb->ts[3].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS2;
break;
case DMX_SOURCE_DVR0:
hw_src = AM_TS_SRC_HIU;
@@ -4621,17 +4689,22 @@ int aml_stb_hw_set_source(struct aml_dvb *dvb, dmx_source_t src)
case DMX_SOURCE_FRONT0:
hw_src =
(dvb->ts[0].mode ==
AM_TS_SERIAL) ? AM_TS_SRC_S_TS0 : AM_TS_SRC_TS0;
AM_TS_SERIAL) ? (dvb->ts[0].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS0;
break;
case DMX_SOURCE_FRONT1:
hw_src =
(dvb->ts[1].mode ==
AM_TS_SERIAL) ? AM_TS_SRC_S_TS1 : AM_TS_SRC_TS1;
AM_TS_SERIAL) ? (dvb->ts[1].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS1;
break;
case DMX_SOURCE_FRONT2:
hw_src =
(dvb->ts[2].mode ==
AM_TS_SERIAL) ? AM_TS_SRC_S_TS2 : AM_TS_SRC_TS2;
AM_TS_SERIAL) ? (dvb->ts[2].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS2;
break;
case DMX_SOURCE_FRONT3:
hw_src =
(dvb->ts[3].mode ==
AM_TS_SERIAL) ? (dvb->ts[3].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS3;
break;
case DMX_SOURCE_DVR0:
hw_src = AM_TS_SRC_HIU;
@@ -4836,15 +4909,19 @@ int aml_tso_hw_set_source(struct aml_dvb *dvb, dmx_source_t src)
switch (src) {
case DMX_SOURCE_FRONT0:
hw_src = (dvb->ts[0].mode == AM_TS_SERIAL)
? AM_TS_SRC_S_TS0 : AM_TS_SRC_TS0;
? (dvb->ts[0].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS0;
break;
case DMX_SOURCE_FRONT1:
hw_src = (dvb->ts[1].mode == AM_TS_SERIAL)
? AM_TS_SRC_S_TS1 : AM_TS_SRC_TS1;
? (dvb->ts[1].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS1;
break;
case DMX_SOURCE_FRONT2:
hw_src = (dvb->ts[2].mode == AM_TS_SERIAL)
? AM_TS_SRC_S_TS2 : AM_TS_SRC_TS2;
? (dvb->ts[2].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS2;
break;
case DMX_SOURCE_FRONT3:
hw_src = (dvb->ts[3].mode == AM_TS_SERIAL)
? (dvb->ts[3].s2p_id + AM_TS_SRC_S_TS0) : AM_TS_SRC_TS3;
break;
case DMX_SOURCE_DVR0:
hw_src = AM_TS_SRC_HIU;

113
drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.c
View File

@@ -156,6 +156,8 @@ long aml_stb_get_base(int id)
return (newbase) ? 0x9400 : 0x2110;
case ID_ASYNC_FIFO_REG_BASE:
return (newbase) ? 0x2800 : 0x2310;
case ID_ASYNC_FIFO1_REG_BASE:
return 0x9800;
case ID_ASYNC_FIFO2_REG_BASE:
return (newbase) ? 0x2400 : 0x2314;
case ID_RESET_BASE:
@@ -677,6 +679,8 @@ static int aml_dvb_asyncfifo_init(struct aml_dvb *advb,
if (id == 0)
asyncfifo->asyncfifo_irq = INT_ASYNC_FIFO_FLUSH;
else if(id == 2)
asyncfifo->asyncfifo_irq = INT_ASYNC_FIFO3_FLUSH;
else
asyncfifo->asyncfifo_irq = INT_ASYNC_FIFO2_FLUSH;
@@ -752,6 +756,9 @@ static ssize_t stb_show_source(struct class *class,
case AM_TS_SRC_S_TS2:
src = "ts2";
break;
case AM_TS_SRC_TS3:
src = "ts3";
break;
case AM_TS_SRC_HIU:
src = "hiu";
break;
@@ -786,6 +793,8 @@ static ssize_t stb_store_source(struct class *class,
src = DMX_SOURCE_FRONT1;
else if (!strncmp("ts2", buf, 3))
src = DMX_SOURCE_FRONT2;
else if (!strncmp("ts3", buf, 3))
src = DMX_SOURCE_FRONT3;
else if (!strncmp("hiu", buf, 3))
src = DMX_SOURCE_DVR0;
else if (!strncmp("dmx0", buf, 4))
@@ -923,6 +932,9 @@ static ssize_t tso_show_source(struct class *class,
case AM_TS_SRC_S_TS2:
src = "ts2";
break;
case AM_TS_SRC_TS3:
src = "ts3";
break;
case AM_TS_SRC_HIU:
src = "hiu";
break;
@@ -957,6 +969,8 @@ static ssize_t tso_store_source(struct class *class,
src = DMX_SOURCE_FRONT1;
else if (!strncmp("ts2", buf, 3))
src = DMX_SOURCE_FRONT2;
else if (!strncmp("ts3", buf, 3))
src = DMX_SOURCE_FRONT3;
else if (!strncmp("hiu", buf, 3))
src = DMX_SOURCE_DVR0;
else if (!strncmp("dmx0", buf, 4))
@@ -1225,6 +1239,8 @@ static ssize_t asyncfifo##i##_show_source(struct class *class, \
struct aml_asyncfifo *afifo = &dvb->asyncfifo[i];\
ssize_t ret = 0;\
char *src;\
if (dvb->async_fifo_total_count <= i)\
return ret;\
switch (afifo->source) {\
CASE_PREFIX case AM_DMX_0:\
src = "dmx0";\
@@ -1247,6 +1263,8 @@ static ssize_t asyncfifo##i##_store_source(struct class *class, \
{\
enum aml_dmx_id_t src = -1;\
\
if (aml_dvb_device.async_fifo_total_count <= i)\
return 0;\
if (!strncmp("dmx0", buf, 4)) {\
src = AM_DMX_0;\
} else if (!strncmp("dmx1", buf, 4)) {\
@@ -1266,6 +1284,11 @@ ASYNCFIFO_SOURCE_FUNC_DECL(0)
#if ASYNCFIFO_COUNT > 1
ASYNCFIFO_SOURCE_FUNC_DECL(1)
#endif
#if ASYNCFIFO_COUNT > 2
ASYNCFIFO_SOURCE_FUNC_DECL(2)
#endif
/*Show the async fifo flush size*/
#define ASYNCFIFO_FLUSHSIZE_FUNC_DECL(i) \
static ssize_t asyncfifo##i##_show_flush_size(struct class *class, \
@@ -1274,6 +1297,8 @@ static ssize_t asyncfifo##i##_show_flush_size(struct class *class, \
struct aml_dvb *dvb = &aml_dvb_device;\
struct aml_asyncfifo *afifo = &dvb->asyncfifo[i];\
ssize_t ret = 0;\
if (dvb->async_fifo_total_count <= i)\
return ret;\
ret = sprintf(buf, "%d\n", afifo->flush_size);\
return ret;\
} \
@@ -1286,7 +1311,10 @@ static ssize_t asyncfifo##i##_store_flush_size(struct class *class, \
/*int fsize = simple_strtol(buf, NULL, 10);*/\
int fsize = 0;\
long value;\
int ret = kstrtol(buf, 0, &value);\
int ret =0;\
if (dvb->async_fifo_total_count <= i)\
return (size_t)0;\
ret = kstrtol(buf, 0, &value);\
if (ret == 0)\
fsize = value;\
if (fsize != afifo->flush_size) {\
@@ -1303,6 +1331,11 @@ ASYNCFIFO_FLUSHSIZE_FUNC_DECL(0)
#if ASYNCFIFO_COUNT > 1
ASYNCFIFO_FLUSHSIZE_FUNC_DECL(1)
#endif
#if ASYNCFIFO_COUNT > 2
ASYNCFIFO_FLUSHSIZE_FUNC_DECL(2)
#endif
/*Show the async fifo secure buffer addr*/
#define ASYNCFIFO_SECUREADDR_FUNC_DECL(i) \
static ssize_t asyncfifo##i##_show_secure_addr(struct class *class, \
@@ -1311,6 +1344,8 @@ static ssize_t asyncfifo##i##_show_secure_addr(struct class *class, \
struct aml_dvb *dvb = &aml_dvb_device;\
struct aml_asyncfifo *afifo = &dvb->asyncfifo[i];\
ssize_t ret = 0;\
if (dvb->async_fifo_total_count <= i)\
return ret;\
ret = sprintf(buf, "0x%x\n", afifo->blk.addr);\
return ret;\
} \
@@ -1321,7 +1356,10 @@ const char *buf, size_t size)\
struct aml_dvb *dvb = &aml_dvb_device;\
struct aml_asyncfifo *afifo = &dvb->asyncfifo[i];\
unsigned long value;\
int ret = kstrtol(buf, 0, &value);\
int ret=0;\
if (dvb->async_fifo_total_count <= i)\
return (size_t)0;\
ret = kstrtol(buf, 0, &value);\
if (ret == 0 && value != afifo->blk.addr) {\
afifo->blk.addr = value;\
aml_asyncfifo_hw_reset(&aml_dvb_device.asyncfifo[i]);\
@@ -1337,6 +1375,10 @@ const char *buf, size_t size)\
ASYNCFIFO_SECUREADDR_FUNC_DECL(1)
#endif
#if ASYNCFIFO_COUNT > 2
ASYNCFIFO_SECUREADDR_FUNC_DECL(2)
#endif
/*Show the async fifo secure enable*/
#define ASYNCFIFO_SECURENABLE_FUNC_DECL(i) \
@@ -1346,6 +1388,8 @@ static ssize_t asyncfifo##i##_show_secure_enable(struct class *class, \
struct aml_dvb *dvb = &aml_dvb_device;\
struct aml_asyncfifo *afifo = &dvb->asyncfifo[i];\
ssize_t ret = 0;\
if (dvb->async_fifo_total_count <= i)\
return ret;\
ret = sprintf(buf, "%d\n", afifo->secure_enable);\
return ret;\
} \
@@ -1357,7 +1401,10 @@ static ssize_t asyncfifo##i##_store_secure_enable(struct class *class, \
struct aml_asyncfifo *afifo = &dvb->asyncfifo[i];\
int enable = 0;\
long value;\
int ret = kstrtol(buf, 0, &value);\
int ret=0;\
if (dvb->async_fifo_total_count <= i)\
return (size_t)0;\
ret = kstrtol(buf, 0, &value);\
if (ret == 0)\
enable = value;\
if (enable != afifo->secure_enable) {\
@@ -1374,6 +1421,11 @@ ASYNCFIFO_SECURENABLE_FUNC_DECL(0)
#if ASYNCFIFO_COUNT > 1
ASYNCFIFO_SECURENABLE_FUNC_DECL(1)
#endif
#if ASYNCFIFO_COUNT > 2
ASYNCFIFO_SECURENABLE_FUNC_DECL(2)
#endif
/*Reset the Demux*/
static ssize_t demux_do_reset(struct class *class,
struct class_attribute *attr,
@@ -1450,7 +1502,7 @@ static ssize_t stb_show_hw_setting(struct class *class,
struct aml_dvb *dvb = &aml_dvb_device;
int invert, ctrl;
for (i = 0; i < TS_IN_COUNT; i++) {
for (i = 0; i < dvb->ts_in_total_count; i++) {
struct aml_ts_input *ts = &dvb->ts[i];
if (ts->s2p_id != -1)
@@ -1486,7 +1538,7 @@ static ssize_t stb_store_hw_setting(struct class *class,
if (r != 4)
return -EINVAL;
if (id < 0 || id >= TS_IN_COUNT)
if (id < 0 || id >= dvb->ts_in_total_count)
return -EINVAL;
if ((mname[0] == 's') || (mname[0] == 'S')) {
@@ -1506,12 +1558,12 @@ static ssize_t stb_store_hw_setting(struct class *class,
int i;
int scnt = 0;
for (i = 0; i < TS_IN_COUNT; i++) {
for (i = 0; i < dvb->ts_in_total_count; i++) {
if (dvb->ts[i].s2p_id != -1)
scnt++;
}
if (scnt >= S2P_COUNT)
if (scnt >= dvb->s2p_total_count)
pr_error("no free s2p\n");
else
ts->s2p_id = scnt;
@@ -1631,6 +1683,13 @@ static struct class_attribute aml_stb_class_attrs[] = {
ASYNCFIFO_SECURENABLE_ATTR_DECL(1),
#endif
#if ASYNCFIFO_COUNT > 2
ASYNCFIFO_SOURCE_ATTR_DECL(2),
ASYNCFIFO_FLUSHSIZE_ATTR_DECL(2),
ASYNCFIFO_SECUREADDR_ATTR_DECL(2),
ASYNCFIFO_SECURENABLE_ATTR_DECL(2),
#endif
__ATTR(demux_reset, 0644, NULL, demux_do_reset),
__ATTR(video_pts, 0664, demux_show_video_pts,
NULL),
@@ -1685,7 +1744,7 @@ static int aml_dvb_probe(struct platform_device *pdev)
int i, ret = 0;
struct devio_aml_platform_data *pd_dvb;
pr_inf("probe amlogic dvb driver\n");
pr_dbg("probe amlogic dvb driver\n");
/*switch_mod_gate_by_name("demux", 1); */
#if 0
@@ -1750,6 +1809,16 @@ static int aml_dvb_probe(struct platform_device *pdev)
amports_switch_gate("demux", 1);
amports_switch_gate("ahbarb0", 1);
amports_switch_gate("parser_top", 1);
if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1)
{
aml_dvb_afifo_clk =
devm_clk_get(&pdev->dev, "asyncfifo");
if (IS_ERR_OR_NULL(aml_dvb_afifo_clk)) {
dev_err(&pdev->dev, "get asyncfifo clk fail\n");
return -1;
}
clk_prepare_enable(aml_dvb_afifo_clk);
}
}
#endif
advb = &aml_dvb_device;
@@ -1762,6 +1831,16 @@ static int aml_dvb_probe(struct platform_device *pdev)
advb->stb_source = -1;
advb->tso_source = -1;
if (get_cpu_type() < MESON_CPU_MAJOR_ID_TL1) {
advb->ts_in_total_count = 3;
advb->s2p_total_count = 2;
advb->async_fifo_total_count = 2;
} else {
advb->ts_in_total_count = 4;
advb->s2p_total_count = 3;
advb->async_fifo_total_count = 3;
}
for (i = 0; i < DMX_DEV_COUNT; i++) {
advb->dmx[i].dmx_irq = -1;
advb->dmx[i].dvr_irq = -1;
@@ -1774,7 +1853,7 @@ static int aml_dvb_probe(struct platform_device *pdev)
const char *str;
u32 value;
for (i = 0; i < TS_IN_COUNT; i++) {
for (i = 0; i < advb->ts_in_total_count; i++) {
advb->ts[i].mode = AM_TS_DISABLE;
advb->ts[i].s2p_id = -1;
@@ -1788,7 +1867,7 @@ static int aml_dvb_probe(struct platform_device *pdev)
if (!strcmp(str, "serial")) {
pr_inf("%s: serial\n", buf);
if (s2p_id >= S2P_COUNT)
if (s2p_id >= advb->s2p_total_count)
pr_error("no free s2p\n");
else {
snprintf(buf, sizeof(buf),
@@ -1868,7 +1947,7 @@ static int aml_dvb_probe(struct platform_device *pdev)
for (i = 0; i<DSC_DEV_COUNT; i++)
advb->dsc[i].id = -1;
for (i = 0; i < ASYNCFIFO_COUNT; i++)
for (i = 0; i < advb->async_fifo_total_count; i++)
advb->asyncfifo[i].id = -1;
advb->dvb_adapter.priv = advb;
@@ -1887,7 +1966,7 @@ static int aml_dvb_probe(struct platform_device *pdev)
}
/*Init the async fifos */
for (i = 0; i < ASYNCFIFO_COUNT; i++) {
for (i = 0; i < advb->async_fifo_total_count; i++) {
ret = aml_dvb_asyncfifo_init(advb, &advb->asyncfifo[i], i);
if (ret < 0)
goto error;
@@ -2164,7 +2243,7 @@ error_fe:
}
return 0;
error:
for (i = 0; i < ASYNCFIFO_COUNT; i++) {
for (i = 0; i < advb->async_fifo_total_count; i++) {
if (advb->asyncfifo[i].id != -1)
aml_dvb_asyncfifo_release(advb, &advb->asyncfifo[i]);
}
@@ -2223,7 +2302,7 @@ static int aml_dvb_remove(struct platform_device *pdev)
aml_unregist_dmx_class();
class_unregister(&aml_stb_class);
for (i = 0; i < ASYNCFIFO_COUNT; i++) {
for (i = 0; i < advb->async_fifo_total_count; i++) {
if (advb->asyncfifo[i].id != -1)
aml_dvb_asyncfifo_release(advb, &advb->asyncfifo[i]);
}
@@ -2240,7 +2319,7 @@ static int aml_dvb_remove(struct platform_device *pdev)
}
dvb_unregister_adapter(&advb->dvb_adapter);
for (i = 0; i < TS_IN_COUNT; i++) {
for (i = 0; i < advb->ts_in_total_count; i++) {
if (advb->ts[i].pinctrl && !IS_ERR_VALUE(advb->ts[i].pinctrl))
devm_pinctrl_put(advb->ts[i].pinctrl);
}
@@ -2265,6 +2344,10 @@ static int aml_dvb_remove(struct platform_device *pdev)
amports_switch_gate("demux", 0);
amports_switch_gate("ahbarb0", 0);
amports_switch_gate("parser_top", 0);
if (get_cpu_type() == MESON_CPU_MAJOR_ID_TL1) {
clk_disable_unprepare(aml_dvb_afifo_clk);
}
}
#endif
#endif

14
drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb.h
View File

@@ -54,8 +54,14 @@
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#define TS_IN_COUNT 4
#define S2P_COUNT 3
#define ASYNCFIFO_COUNT 3
#if 0
#define TS_IN_COUNT 3
#define S2P_COUNT 2
#define ASYNCFIFO_COUNT 2
#endif
#define DMX_DEV_COUNT 3
#define FE_DEV_COUNT 2
@@ -67,7 +73,6 @@
#define SEC_BUF_GRP_COUNT 4
#define SEC_BUF_BUSY_SIZE 4
#define SEC_BUF_COUNT (SEC_BUF_GRP_COUNT*8)
#define ASYNCFIFO_COUNT 2
enum aml_dmx_id_t {
AM_DMX_0 = 0,
@@ -80,9 +85,12 @@ enum aml_ts_source_t {
AM_TS_SRC_TS0,
AM_TS_SRC_TS1,
AM_TS_SRC_TS2,
AM_TS_SRC_TS3,
AM_TS_SRC_S_TS0,
AM_TS_SRC_S_TS1,
AM_TS_SRC_S_TS2,
AM_TS_SRC_HIU,
AM_TS_SRC_DMX0,
AM_TS_SRC_DMX1,
@@ -286,11 +294,13 @@ struct aml_swfilter {
struct aml_dvb {
struct dvb_device dvb_dev;
int ts_in_total_count;
struct aml_ts_input ts[TS_IN_COUNT];
int s2p_total_count;
struct aml_s2p s2p[S2P_COUNT];
struct aml_dmx dmx[DMX_DEV_COUNT];
struct aml_dsc dsc[DSC_DEV_COUNT];
int async_fifo_total_count;
struct aml_asyncfifo asyncfifo[ASYNCFIFO_COUNT];
struct dvb_adapter dvb_adapter;
struct device *dev;

8
drivers/amlogic/media_modules/stream_input/parser/hw_demux/aml_dvb_reg.h
View File

@@ -25,9 +25,10 @@
#define ID_STB_CBUS_BASE 0
#define ID_SMARTCARD_REG_BASE 1
#define ID_ASYNC_FIFO_REG_BASE 2
#define ID_ASYNC_FIFO2_REG_BASE 3
#define ID_RESET_BASE 4
#define ID_PARSER_SUB_START_PTR_BASE 5
#define ID_ASYNC_FIFO1_REG_BASE 3
#define ID_ASYNC_FIFO2_REG_BASE 4
#define ID_RESET_BASE 5
#define ID_PARSER_SUB_START_PTR_BASE 6
long aml_stb_get_base(int id);
#include "c_stb_define.h"
@@ -52,5 +53,6 @@ long aml_stb_get_base(int id);
#define INT_ASYNC_FIFO2_FILL AM_IRQ(24)
#define INT_ASYNC_FIFO2_FLUSH AM_IRQ(25)
#define INT_ASYNC_FIFO3_FLUSH AM_IRQ(17)
#endif

11
drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_define.h
View File

@@ -96,6 +96,17 @@
#define INVERT_S2P0_FEC_CLK 2
#define S2P0_FEC_SERIAL_SEL 0
//define STB_S2P2_CONFIG
#define S2P2_DISABLE 11
#define S2P2_CLK_DIV 7
#define INVERT_S2P2_FEC_ERROR 6
#define INVERT_S2P2_FEC_DATA 5
#define INVERT_S2P2_FEC_SYNC 4
#define INVERT_S2P2_FEC_VALID 3
#define INVERT_S2P2_FEC_CLK 2
#define S2P2_FEC_SERIAL_SEL 0
/* 31:28 - s2p1_clk_div*/
/* 27:24 - s2p0_clk_div*/
/* 23 - s2p1_disable*/

20
drivers/amlogic/media_modules/stream_input/parser/hw_demux/c_stb_regs_define.h
View File

@@ -34,6 +34,7 @@
#define STB_CBUS_BASE aml_stb_get_base(ID_STB_CBUS_BASE)
#define SMARTCARD_REG_BASE aml_stb_get_base(ID_SMARTCARD_REG_BASE)
#define ASYNC_FIFO_REG_BASE aml_stb_get_base(ID_ASYNC_FIFO_REG_BASE)
#define ASYNC_FIFO1_REG_BASE aml_stb_get_base(ID_ASYNC_FIFO1_REG_BASE)
#define ASYNC_FIFO2_REG_BASE aml_stb_get_base(ID_ASYNC_FIFO2_REG_BASE)
#define RESET_BASE aml_stb_get_base(ID_RESET_BASE)
#define PARSER_SUB_START_PTR_BASE \
@@ -46,6 +47,12 @@
#define DEMUX_3_OFFSET 0xa0
#define STB_S2P2_CONFIG (STB_CBUS_BASE + 0xef)
#define P_STB_S2P2_CONFIG CBUS_REG_ADDR(STB_S2P2_CONFIG)
#define STB_RECORDER2_CNTL (STB_CBUS_BASE + 0xee)
#define P_STB_RECORDER2_CNTL CBUS_REG_ADDR(STB_RECORDER2_CNTL)
#define STB_TOP_CONFIG (STB_CBUS_BASE + 0xf0)
#define P_STB_TOP_CONFIG CBUS_REG_ADDR(STB_TOP_CONFIG)
#define TS_TOP_CONFIG (STB_CBUS_BASE + 0xf1)
@@ -109,6 +116,19 @@
#define ASYNC_FIFO_REG5 (ASYNC_FIFO_REG_BASE + 0x5)
#define P_ASYNC_FIFO_REG5 CBUS_REG_ADDR(ASYNC_FIFO_REG5)
#define ASYNC_FIFO1_REG0 (ASYNC_FIFO1_REG_BASE + 0x0)
#define P_ASYNC_FIFO1_REG0 CBUS_REG_ADDR(ASYNC_FIFO1_REG0)
#define ASYNC_FIFO1_REG1 (ASYNC_FIFO1_REG_BASE + 0x1)
#define P_ASYNC_FIFO1_REG1 CBUS_REG_ADDR(ASYNC_FIFO1_REG1)
#define ASYNC_FIFO1_REG2 (ASYNC_FIFO1_REG_BASE + 0x2)
#define P_ASYNC_FIFO1_REG2 CBUS_REG_ADDR(ASYNC_FIFO1_REG2)
#define ASYNC_FIFO1_REG3 (ASYNC_FIFO1_REG_BASE + 0x3)
#define P_ASYNC_FIFO1_REG3 CBUS_REG_ADDR(ASYNC_FIFO1_REG3)
#define ASYNC_FIFO1_REG4 (ASYNC_FIFO1_REG_BASE + 0x4)
#define P_ASYNC_FIFO1_REG4 CBUS_REG_ADDR(ASYNC_FIFO1_REG4)
#define ASYNC_FIFO1_REG5 (ASYNC_FIFO1_REG_BASE + 0x5)
#define P_ASYNC_FIFO1_REG5 CBUS_REG_ADDR(ASYNC_FIFO1_REG5)
#define ASYNC_FIFO2_REG0 (ASYNC_FIFO2_REG_BASE + 0x0)
#define P_ASYNC_FIFO2_REG0 CBUS_REG_ADDR(ASYNC_FIFO2_REG0)