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Merge commit 'adf004e7c8f9c2e75799b47da1e59c45d27bc302'

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* commit 'adf004e7c8f9c2e75799b47da1e59c45d27bc302':
  media: rockchip: vicap fixes issue of hdr raw capture
  media: i2c: sc1346: fix fps error
  ARM: configs: add rk3308-aarch32-ia.config for intelligent home appliances in RK3308 soc
  arm64: dts: rockchip: add RK3567 evaluation board devicetree
  Revert "arm64: dts: rockchip: rk3568-evb: add can nodes"

Change-Id: Id580877c8d4cf492652e261a08918fb339d410c5
This commit is contained in:
Tao Huang
2023-09-27 10:36:13 +08:00
parent ef8deca09b adf004e7c8
commit e71825db2b
9 changed files with 1034 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files

325
arch/arm/configs/rk3308-aarch32-ia.config Normal file
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@@ -0,0 +1,325 @@
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_CMA=y
CONFIG_DRM=y
# CONFIG_ETHERNET is not set
# CONFIG_ETHTOOL_NETLINK is not set
CONFIG_FB=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MISC is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_KCMP=y
# CONFIG_MDIO_DEVICE is not set
# CONFIG_MEDIA_CEC_SUPPORT is not set
# CONFIG_MEDIA_SUPPORT is not set
CONFIG_MFD_RK618=y
# CONFIG_NEW_LEDS is not set
# CONFIG_PHYLIB is not set
# CONFIG_PWRSEQ_EMMC is not set
# CONFIG_RK_NANDC_NAND is not set
# CONFIG_SND_SOC_ROCKCHIP_SPDIF is not set
CONFIG_SYNC_FILE=y
# CONFIG_USB_SUPPORT is not set
# CONFIG_VHOST_MENU is not set
# CONFIG_VIRTIO_MENU is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_GPIO is not set
# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BACKLIGHT_QCOM_WLED is not set
CONFIG_CLK_RK618=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_INACTIVE is not set
CONFIG_CMA_SIZE_MBYTES=16
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_COMMON_CLK_ROCKCHIP_REGMAP=y
CONFIG_CONTIG_ALLOC=y
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
CONFIG_DMA_CMA=y
# CONFIG_DMA_FENCE_TRACE is not set
# CONFIG_DMA_PERNUMA_CMA is not set
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_ARMADA is not set
CONFIG_DRM_BRIDGE=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
# CONFIG_DRM_DP is not set
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_EDID=y
# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_EXYNOS is not set
CONFIG_DRM_FBDEV_EMULATION=y
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FSL_DCU is not set
CONFIG_DRM_GEM_CMA_HELPER=y
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_SIL164 is not set
CONFIG_DRM_IGNORE_IOTCL_PERMIT=y
# CONFIG_DRM_ITE_IT6161 is not set
CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_KOMEDA is not set
# CONFIG_DRM_LEGACY is not set
# CONFIG_DRM_LIMA is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_MCDE is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_OMAP is not set
CONFIG_DRM_PANEL=y
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
CONFIG_DRM_PANEL_BRIDGE=y
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
# CONFIG_DRM_PANEL_MAXIM_MAX96752F is not set
# CONFIG_DRM_PANEL_MAXIM_MAX96772 is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
CONFIG_DRM_PANEL_SIMPLE=y
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# CONFIG_DRM_PANFROST is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_PL111 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
# CONFIG_DRM_RK1000_TVE is not set
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_ROCKCHIP_RK618=y
# CONFIG_DRM_ROCKCHIP_VVOP is not set
# CONFIG_DRM_ROHM_BU18XL82 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_STI is not set
# CONFIG_DRM_STM is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_TILCDC is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TVE200 is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MODE_HELPERS is not set
CONFIG_FB_NOTIFY=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SSD1307 is not set
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_TFT is not set
# CONFIG_FB_TILEBLITTING is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FIRMWARE_EDID is not set
CONFIG_HDMI=y
CONFIG_I2C_ALGOBIT=y
# CONFIG_LOGO is not set
# CONFIG_LT7911D_FB_NOTIFIER is not set
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_CORE=y
CONFIG_MIGRATION=y
CONFIG_REGMAP_IRQ=y
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
# CONFIG_RK_CMA_PROCFS is not set
# CONFIG_RK_DMABUF_PROCFS is not set
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
# CONFIG_ROCKCHIP_CDN_DP is not set
# CONFIG_ROCKCHIP_DRM_DEBUG is not set
# CONFIG_ROCKCHIP_DRM_DIRECT_SHOW is not set
# CONFIG_ROCKCHIP_DRM_TVE is not set
# CONFIG_ROCKCHIP_DW_DP is not set
# CONFIG_ROCKCHIP_DW_HDCP2 is not set
# CONFIG_ROCKCHIP_DW_HDMI is not set
# CONFIG_ROCKCHIP_DW_MIPI_DSI is not set
# CONFIG_ROCKCHIP_INNO_HDMI is not set
# CONFIG_ROCKCHIP_LVDS is not set
CONFIG_ROCKCHIP_RGB=y
# CONFIG_ROCKCHIP_RK3066_HDMI is not set
# CONFIG_ROCKCHIP_RKNPU is not set
# CONFIG_ROCKCHIP_SERDES_DRM_PANEL is not set
# CONFIG_ROCKCHIP_VCONN is not set
CONFIG_ROCKCHIP_VOP=y
# CONFIG_ROCKCHIP_VOP2 is not set
# CONFIG_SW_SYNC is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ADC is not set
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX is not set
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_ELAN5515 is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
# CONFIG_TOUCHSCREEN_FTS is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GOODIX is not set
# CONFIG_TOUCHSCREEN_GSL3673 is not set
# CONFIG_TOUCHSCREEN_GSL3673_800X1280 is not set
# CONFIG_TOUCHSCREEN_GSLX680_PAD is not set
CONFIG_TOUCHSCREEN_GT1X=y
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_IQS5XX is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
CONFIG_TOUCHSCREEN_PROPERTIES=y
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
# CONFIG_TOUCHSCREEN_ZFORCE is not set
# CONFIG_TOUCHSCREEN_ZINITIX is not set
# CONFIG_UDMABUF is not set
CONFIG_VIDEOMODE_HELPERS=y

1
arch/arm64/boot/dts/rockchip/Makefile
View File

@@ -144,6 +144,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-dual-camera.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux.dtb

8
arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10.dts Normal file
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@@ -0,0 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3567-evb2-lp4x-v10.dtsi"
#include "rk3568-android.dtsi"

648
arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10.dtsi Normal file
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@@ -0,0 +1,648 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/display/media-bus-format.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3567.dtsi"
#include "rk3568-evb.dtsi"
/ {
model = "Rockchip RK3567 EVB2 LP4X V10 Board";
compatible = "rockchip,rk3567-evb2-lp4x-v10", "rockchip,rk3567";
vcc_camera: vcc-camera-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&camera_pwr>;
regulator-name = "vcc_camera";
enable-active-high;
regulator-always-on;
regulator-boot-on;
};
vcc3v3_pcie: gpio-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_pcie";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
startup-delay-us = <5000>;
vin-supply = <&dc_12v>;
};
};
&bt_sound {
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&i2s2_2ch>;
};
};
&cpu0 {
cpu-supply = <&vdd_cpu_rk860>;
};
&bus_npu {
pvtm-supply = <&vdd_cpu_rk860>;
};
&combphy0_us {
status = "okay";
};
&combphy1_usq {
status = "okay";
};
&combphy2_psq {
status = "okay";
};
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
/*
* dphy0 only used for full mode,
* full mode and split mode are mutually exclusive
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dphy0_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&gc8034_out>;
data-lanes = <1 2 3 4>;
};
mipi_in_ucam1: endpoint@2 {
reg = <2>;
remote-endpoint = <&ov5695_out>;
data-lanes = <1 2>;
};
mipi_in_ucam2: endpoint@3 {
reg = <3>;
remote-endpoint = <&gc5025_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy0_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp0_in_dphy0>;
};
};
};
};
&csi2_dphy1 {
status = "disabled";
/*
* dphy1 only used for split mode,
* can be used concurrently with dphy2
* full mode and split mode are mutually exclusive
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dphy1_in: endpoint@1 {
reg = <1>;
//remote-endpoint = <&ov5695_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy1_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&isp0_in>;
};
};
};
};
&csi2_dphy2 {
status = "disabled";
/*
* dphy2 only used for split mode,
* can be used concurrently with dphy1
* full mode and split mode are mutually exclusive
*/
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
dphy2_in: endpoint@1 {
reg = <1>;
//remote-endpoint = <&gc5025_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
dphy2_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
/*
* video_phy0 needs to be enabled
* when dsi0 is enabled
*/
&dsi0 {
status = "okay";
};
&dsi0_in_vp0 {
status = "disabled";
};
&dsi0_in_vp1 {
status = "okay";
};
&dsi0_panel {
power-supply = <&vcc3v3_lcd0_n>;
reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&lcd0_rst_gpio>;
};
/*
* video_phy1 needs to be enabled
* when dsi1 is enabled
*/
&dsi1 {
status = "disabled";
};
&dsi1_in_vp0 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&dsi1_panel {
power-supply = <&vcc3v3_lcd1_n>;
reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&lcd1_rst_gpio>;
};
&gmac1 {
phy-mode = "rgmii";
clock_in_out = "output";
snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
tx_delay = <0x4f>;
rx_delay = <0x25>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&i2c0 {
vdd_cpu_rk860: rk8600@40{
compatible = "rockchip,rk8600";
reg = <0x40>;
vin-supply = <&vcc5v0_sys>;
regulator-compatible = "rk860x-reg";
regulator-name = "vdd_cpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <2300>;
rockchip,suspend-voltage-selector = <1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&i2c2 {
status = "okay";
pinctrl-0 = <&i2c2m1_xfer>;
/* split mode: lane0/1 */
ov5695: ov5695@36 {
status = "okay";
compatible = "ovti,ov5695";
reg = <0x36>;
clocks = <&cru CLK_CIF_OUT>;
clock-names = "xvclk";
power-domains = <&power RK3568_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cif_clk>;
reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
/*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "TongJu";
rockchip,camera-module-lens-name = "CHT842-MD";
port {
ov5695_out: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2>;
};
};
};
/* split mode: lane:2/3 */
gc5025: gc5025@37 {
status = "okay";
compatible = "galaxycore,gc5025";
reg = <0x37>;
clocks = <&pmucru CLK_WIFI>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&refclk_pins>;
reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
power-domains = <&power RK3568_PD_VI>;
/*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "TongJu";
rockchip,camera-module-lens-name = "CHT842-MD";
port {
gc5025_out: endpoint {
remote-endpoint = <&mipi_in_ucam2>;
data-lanes = <1 2>;
};
};
};
/* full mode: lane0-3 */
gc8034: gc8034@37 {
compatible = "galaxycore,gc8034";
status = "okay";
reg = <0x37>;
clocks = <&cru CLK_CIF_OUT>;
clock-names = "xvclk";
power-domains = <&power RK3568_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&cif_clk>;
reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "RK-CMK-8M-2-v1";
rockchip,camera-module-lens-name = "CK8401";
port {
gc8034_out: endpoint {
remote-endpoint = <&dphy0_in>;
data-lanes = <1 2 3 4>;
};
};
};
};
&i2c4 {
/* i2c4 sda conflict with camera pwdn */
status = "disabled";
/*
* gc2145 needs to be disabled,
* when gmac1 is enabled;
* pinctrl conflicts;
*/
gc2145: gc2145@3c {
status = "disabled";
compatible = "galaxycore,gc2145";
reg = <0x3c>;
clocks = <&cru CLK_CIF_OUT>;
clock-names = "xvclk";
power-domains = <&power RK3568_PD_VI>;
pinctrl-names = "default";
/* conflict with gmac1m1_rgmii_pins & cif_clk*/
pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus16>;
/*avdd-supply = <&vcc2v8_dvp>;*/
/*dovdd-supply = <&vcc1v8_dvp>;*/
/*dvdd-supply = <&vcc1v8_dvp>;*/
/*reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;*/
pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CameraKing";
rockchip,camera-module-lens-name = "Largan";
port {
gc2145_out: endpoint {
remote-endpoint = <&dvp_in_bcam>;
};
};
};
};
&i2s2_2ch {
pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>;
rockchip,bclk-fs = <32>;
status = "disabled";
};
&mdio1 {
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
/*
* power-supply should switche to vcc3v3_lcd1_n
* when mipi panel is connected to dsi1.
*/
&gt1x {
power-supply = <&vcc3v3_lcd0_n>;
};
&mipi_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&dphy2_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
data-lanes = <1 2>;
};
};
};
};
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "disabled";
};
&pcie2x1 {
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};
&pinctrl {
cam {
camera_pwr: camera-pwr {
rockchip,pins =
/* camera power en */
<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
wireless-bluetooth {
uart1_gpios: uart1-gpios {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd0 {
lcd0_rst_gpio: lcd0-rst-gpio {
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd1 {
lcd1_rst_gpio: lcd1-rst-gpio {
rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&rkcif {
status = "okay";
};
&rkcif_dvp {
status = "disabled";
port {
/* Parallel bus endpoint */
dvp_in_bcam: endpoint {
remote-endpoint = <&gc2145_out>;
bus-width = <8>;
vsync-active = <0>;
hsync-active = <1>;
};
};
};
&rkcif_mipi_lvds {
status = "okay";
port {
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
data-lanes = <1 2>;
};
};
};
&rkcif_mmu {
status = "okay";
};
&rkisp {
status = "okay";
};
&rkisp_mmu {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp0_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&dphy1_out>;
};
isp0_in_dphy0: endpoint@1 {
reg = <1>;
remote-endpoint = <&dphy0_out>;
};
};
};
&route_dsi0 {
status = "okay";
connect = <&vp1_out_dsi0>;
};
&sdmmc2 {
status = "disabled";
};
&sdmmc1 {
max-frequency = <150000000>;
no-sd;
no-mmc;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
mmc-pwrseq = <&sdio_pwrseq>;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
sd-uhs-sdr104;
status = "okay";
};
&sdio_pwrseq {
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
};
&spdif_8ch {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spdifm1_tx>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&vcc3v3_lcd1_n {
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&wireless_wlan {
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq>;
WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
};
&work_led {
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
};
&wireless_bluetooth {
compatible = "bluetooth-platdata";
clocks = <&rk809 1>;
clock-names = "ext_clock";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart1m0_rtsn>;
pinctrl-1 = <&uart1_gpios>;
BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
status = "okay";
};

24
arch/arm64/boot/dts/rockchip/rk3568-evb.dtsi
View File

@@ -377,30 +377,6 @@
status = "okay";
};
&can0 {
assigned-clocks = <&cru CLK_CAN0>;
assigned-clock-rates = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&can0m1_pins>;
status = "disabled";
};
&can1 {
assigned-clocks = <&cru CLK_CAN1>;
assigned-clock-rates = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&can1m1_pins>;
status = "disabled";
};
&can2 {
assigned-clocks = <&cru CLK_CAN2>;
assigned-clock-rates = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&can2m1_pins>;
status = "disabled";
};
&cpu0 {
cpu-supply = <&vdd_cpu>;
};

20
drivers/media/i2c/sc1346.c
View File

@@ -40,7 +40,7 @@
#define PIXEL_RATE_WITH_375M_10BIT (SC1346_LINK_FREQ_375 * 2 * \
SC1346_LANES / SC1346_BITS_PER_SAMPLE)
#define SC1346_XVCLK_FREQ 24000000
#define SC1346_XVCLK_FREQ 27000000
#define CHIP_ID 0xda4d
#define SC1346_REG_CHIP_ID 0x3107
@@ -160,26 +160,26 @@ struct sc1346 {
#define to_sc1346(sd) container_of(sd, struct sc1346, subdev)
/*
* Xclk 24Mhz
* Xclk 27Mhz
*/
static const struct regval sc1346_global_regs[] = {
{REG_NULL, 0x00},
};
/*
* Xclk 24Mhz
* Xclk 27Mhz
* max_framerate 30fps
* mipi_datarate per lane 630Mbps, 2lane
* mipi_datarate per lane 371.25Mbps, 1lane
*/
static const struct regval sc1346_linear_10_2560x1440_regs[] = {
static const struct regval sc1346_linear_10_1280x720_regs[] = {
{0x0103, 0x01},
{0x0100, 0x00},
{0x36e9, 0x80},
{0x37f9, 0x80},
{0x301f, 0x01},
{0x3106, 0x05},
{0x320e, 0x04},
{0x320f, 0x65},
{0x320e, 0x02},
{0x320f, 0xee},
{0x3301, 0x06},
{0x3306, 0x50},
{0x3308, 0x0a},
@@ -277,9 +277,9 @@ static const struct sc1346_mode supported_modes[] = {
},
.exp_def = 0x0080,
.hts_def = 0x0250 * 2,
.vts_def = 0x0708,
.vts_def = 0x02ee,
.bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
.reg_list = sc1346_linear_10_2560x1440_regs,
.reg_list = sc1346_linear_10_1280x720_regs,
.hdr_mode = NO_HDR,
.vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
}
@@ -913,7 +913,7 @@ static int __sc1346_power_on(struct sc1346 *sc1346)
}
ret = clk_set_rate(sc1346->xvclk, SC1346_XVCLK_FREQ);
if (ret < 0)
dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
dev_warn(dev, "Failed to set xvclk rate (27MHz)\n");
if (clk_get_rate(sc1346->xvclk) != SC1346_XVCLK_FREQ)
dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
ret = clk_prepare_enable(sc1346->xvclk);

58
drivers/media/platform/rockchip/cif/capture.c
View File

@@ -1603,7 +1603,7 @@ static void rkcif_rx_buffer_free(struct rkcif_stream *stream)
struct rkisp_rx_buf *dbufs;
struct rkcif_device *dev = stream->cifdev;
if (dev->sditf[0] && dev->sditf[0]->num_sensors != 0) {
if (dev->sditf[0] && dev->sditf[0]->sd.entity.num_links) {
if (dev->sditf[0]->is_combine_mode)
pad = media_pad_remote_pad_first(&dev->sditf[0]->pads[1]);
else
@@ -2313,6 +2313,8 @@ static void rkcif_assign_new_buffer_init(struct rkcif_stream *stream,
stream->curr_buf = list_first_entry(&stream->buf_head,
struct rkcif_buffer,
queue);
v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev, "%s %d, stream[%d] buf idx %d\n",
__func__, __LINE__, stream->id, stream->curr_buf->vb.vb2_buf.index);
list_del(&stream->curr_buf->queue);
}
}
@@ -2381,6 +2383,8 @@ static void rkcif_assign_new_buffer_init(struct rkcif_stream *stream,
if (!list_empty(&stream->buf_head)) {
stream->next_buf = list_first_entry(&stream->buf_head,
struct rkcif_buffer, queue);
v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev, "%s %d, stream[%d] buf idx %d\n",
__func__, __LINE__, stream->id, stream->next_buf->vb.vb2_buf.index);
list_del(&stream->next_buf->queue);
}
}
@@ -2488,16 +2492,15 @@ static int rkcif_assign_new_buffer_update(struct rkcif_stream *stream,
get_dvp_reg_index_of_frm1_uv_addr(channel_id);
}
if (dev->hdr.hdr_mode != NO_HDR && stream->id != 0 && (!dev->rdbk_buf[RDBK_L])) {
v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
return -EINVAL;
}
if (stream->to_stop_dma) {
if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
goto stop_dma;
} else {
if (stream->frame_phase == CIF_CSI_FRAME0_READY)
stream->curr_buf = NULL;
else
stream->next_buf = NULL;
v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
return -EINVAL;
}
@@ -2520,8 +2523,8 @@ static int rkcif_assign_new_buffer_update(struct rkcif_stream *stream,
list_del(&stream->curr_buf->queue);
buffer = stream->curr_buf;
v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
"stream[%d] update curr_buf 0x%x\n",
stream->id, buffer->buff_addr[0]);
"stream[%d] update curr_buf 0x%x, buf idx %d\n",
stream->id, buffer->buff_addr[0], stream->curr_buf->vb.vb2_buf.index);
}
} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
if (!stream->next_buf)
@@ -2541,8 +2544,8 @@ static int rkcif_assign_new_buffer_update(struct rkcif_stream *stream,
list_del(&stream->next_buf->queue);
buffer = stream->next_buf;
v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
"stream[%d] update next_buf 0x%x\n",
stream->id, buffer->buff_addr[0]);
"stream[%d] update next_buf 0x%x, buf idx %d\n",
stream->id, buffer->buff_addr[0], stream->next_buf->vb.vb2_buf.index);
}
}
}
@@ -2722,11 +2725,9 @@ stop_dma:
if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
stream->curr_buf) {
list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
stream->curr_buf = NULL;
} else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
stream->next_buf) {
list_add_tail(&stream->next_buf->queue, &stream->buf_head);
stream->next_buf = NULL;
}
stream->buf_replace_cnt--;
@@ -4365,11 +4366,17 @@ static void rkcif_check_buffer_update_pingpong(struct rkcif_stream *stream,
if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
stream->curr_buf = list_first_entry(&stream->buf_head,
struct rkcif_buffer, queue);
v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
"%s %d, stream[%d] buf idx %d\n",
__func__, __LINE__, stream->id, stream->curr_buf->vb.vb2_buf.index);
if (stream->curr_buf)
list_del(&stream->curr_buf->queue);
} else if (stream->frame_phase_cache == CIF_CSI_FRAME1_READY) {
stream->next_buf = list_first_entry(&stream->buf_head,
struct rkcif_buffer, queue);
v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev,
"%s %d, stream[%d] buf idx %d\n",
__func__, __LINE__, stream->id, stream->next_buf->vb.vb2_buf.index);
if (stream->next_buf)
list_del(&stream->next_buf->queue);
}
@@ -4398,6 +4405,7 @@ static void rkcif_check_buffer_update_pingpong(struct rkcif_stream *stream,
}
if (stream->lack_buf_cnt)
stream->lack_buf_cnt--;
} else {
v4l2_info(&dev->v4l2_dev, "%s %d, state %d, curr_buf %p, next_buf %p\n",
__func__, __LINE__, stream->state, stream->curr_buf, stream->next_buf);
@@ -4940,14 +4948,16 @@ void rkcif_do_stop_stream(struct rkcif_stream *stream,
} else if (mode == RKCIF_STREAM_MODE_CAPTURE && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
//only stop dma
stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
stream->is_wait_dma_stop = true;
wait_event_timeout(stream->wq_stopped,
stream->to_stop_dma != RKCIF_DMAEN_BY_VICAP,
!stream->is_wait_dma_stop,
msecs_to_jiffies(1000));
} else if (mode == RKCIF_STREAM_MODE_TOISP && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
//only stop dma
stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
stream->is_wait_dma_stop = true;
wait_event_timeout(stream->wq_stopped,
stream->to_stop_dma != RKCIF_DMAEN_BY_ISP,
!stream->is_wait_dma_stop,
msecs_to_jiffies(1000));
}
if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE) {
@@ -6521,6 +6531,7 @@ void rkcif_stream_init(struct rkcif_device *dev, u32 id)
stream->is_high_align = false;
stream->is_finish_stop_dma = false;
stream->is_wait_dma_stop = false;
if (dev->chip_id == CHIP_RV1126_CIF ||
dev->chip_id == CHIP_RV1126_CIF_LITE)
@@ -9820,6 +9831,11 @@ static int rkcif_stop_dma_capture(struct rkcif_stream *stream)
rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
}
stream->to_stop_dma = 0;
v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
"stream[%d] replace_cnt %d, y_addr 0x%x, 0x%x\n",
stream->id, stream->buf_replace_cnt,
rkcif_read_register(cif_dev, get_reg_index_of_frm0_y_addr(stream->id)),
rkcif_read_register(cif_dev, get_reg_index_of_frm1_y_addr(stream->id)));
return 0;
}
@@ -10357,7 +10373,12 @@ void rkcif_irq_pingpong_v1(struct rkcif_device *cif_dev)
stream->frame_idx - 1,
stream->frame_phase,
ktime_get_ns());
if (stream->is_finish_stop_dma && stream->is_wait_dma_stop) {
stream->is_wait_dma_stop = false;
wake_up(&stream->wq_stopped);
stream->is_finish_stop_dma = false;
continue;
}
if (stream->crop_dyn_en)
rkcif_dynamic_crop(stream);
@@ -10396,11 +10417,10 @@ void rkcif_irq_pingpong_v1(struct rkcif_device *cif_dev)
}
spin_lock_irqsave(&stream->vbq_lock, flags);
if (stream->is_finish_stop_dma) {
wake_up(&stream->wq_stopped);
stream->is_finish_stop_dma = false;
}
if (!(stream->dma_en & RKCIF_DMAEN_BY_ISP) && stream->lack_buf_cnt == 2) {
v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
"stream[%d] to stop dma, lack_buf_cnt %d\n",
stream->id, stream->lack_buf_cnt);
stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
rkcif_stop_dma_capture(stream);
}

1
drivers/media/platform/rockchip/cif/dev.h
View File

@@ -556,6 +556,7 @@ struct rkcif_stream {
bool is_in_vblank;
bool is_change_toisp;
bool is_stop_capture;
bool is_wait_dma_stop;
};
struct rkcif_lvds_subdev {

3
drivers/media/platform/rockchip/cif/subdev-itf.c
View File

@@ -801,7 +801,8 @@ static int sditf_s_rx_buffer(struct v4l2_subdev *sd,
return -EINVAL;
rx_buf = to_cif_rx_buf(dbufs);
v4l2_dbg(rkcif_debug, 3, &cif_dev->v4l2_dev, "buf back to vicap 0x%x\n",
(u32)rx_buf->dummy.dma_addr);
spin_lock_irqsave(&stream->vbq_lock, flags);
stream->last_rx_buf_idx = dbufs->sequence + 1;
atomic_inc(&stream->buf_cnt);