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UPSTREAM: clk: rockchip: fix clk_i2sout parent selection bits on rk3399

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Register, shift and mask were wrong according to datasheet.

Fixes: 115510053e ("clk: rockchip: add clock controller for the RK3399")
Cc: stable@vger.kernel.org
Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com>
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit a64ad00898)

Change-Id: I5d26dd7073cc14125a37cd02bdf964548248c60b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Alberto Panizzo
2018-07-06 15:18:51 +02:00
committed by Tao Huang
parent 3bbf75c4ed
commit e73ac0e248
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/rockchip/clk-rk3399.c
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@@ -715,7 +715,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
RK3399_CLKSEL_CON(30), 8, 2, MFLAGS,
RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
RK3399_CLKGATE_CON(8), 12, GFLAGS),
/* uart */