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clk: rockchip: rk3368: add CLK_SET_RATE_PARENT flag for dclk_vop

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dclk_vop only allowed on NPLL.

Change-Id: I5325a530d3052de1e8685c39b90357291f0f4fb3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2017-03-17 10:57:51 +08:00
committed by Tao Huang
parent a3ddb728c4
commit e7ebb13742
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/rockchip/clk-rk3368.c
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@@ -99,6 +99,7 @@ PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" };
PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
PNAME(mux_pll_src_dmycpll_dmygpll_npll_p) = { "dummy_cpll", "dummy_gpll", "npll" };
PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" };
PNAME(mux_pll_src_cpll_gpll_usb_usb_p) = { "cpll", "gpll", "usbphy_480m",
@@ -450,7 +451,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3368_CLKGATE_CON(4), 4, GFLAGS),
COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_cpll_gpll_npll_p, 0,
COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
RK3368_CLKGATE_CON(4), 1, GFLAGS),