mirror of
https://github.com/hardkernel/linux.git
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delete old driver of rt5621
This commit is contained in:
陈金泉
File diff suppressed because it is too large
Load Diff
@@ -1,516 +0,0 @@
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#ifndef _RT5621_H
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#define _RT5621_H
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#define RT5621_RESET 0X00 //RESET CODEC TO DEFAULT
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#define RT5621_SPK_OUT_VOL 0X02 //SPEAKER OUT VOLUME
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#define RT5621_HP_OUT_VOL 0X04 //HEADPHONE OUTPUT VOLUME
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#define RT5621_MONO_AUX_OUT_VOL 0X06 //MONO OUTPUT/AUXOUT VOLUME
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#define RT5621_AUXIN_VOL 0X08 //AUXIN VOLUME
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#define RT5621_LINE_IN_VOL 0X0A //LINE IN VOLUME
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#define RT5621_STEREO_DAC_VOL 0X0C //STEREO DAC VOLUME
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#define RT5621_MIC_VOL 0X0E //MICROPHONE VOLUME
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#define RT5621_MIC_ROUTING_CTRL 0X10 //MIC ROUTING CONTROL
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#define RT5621_ADC_REC_GAIN 0X12 //ADC RECORD GAIN
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#define RT5621_ADC_REC_MIXER 0X14 //ADC RECORD MIXER CONTROL
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#define RT5621_SOFT_VOL_CTRL_TIME 0X16 //SOFT VOLUME CONTROL TIME
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#define RT5621_OUTPUT_MIXER_CTRL 0X1C //OUTPUT MIXER CONTROL
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#define RT5621_MIC_CTRL 0X22 //MICROPHONE CONTROL
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#define RT5621_AUDIO_INTERFACE 0X34 //AUDIO INTERFACE
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#define RT5621_STEREO_AD_DA_CLK_CTRL 0X36 //STEREO AD/DA CLOCK CONTROL
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#define RT5621_COMPANDING_CTRL 0X38 //COMPANDING CONTROL
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#define RT5621_PWR_MANAG_ADD1 0X3A //POWER MANAGMENT ADDITION 1
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#define RT5621_PWR_MANAG_ADD2 0X3C //POWER MANAGMENT ADDITION 2
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#define RT5621_PWR_MANAG_ADD3 0X3E //POWER MANAGMENT ADDITION 3
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#define RT5621_ADD_CTRL_REG 0X40 //ADDITIONAL CONTROL REGISTER
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#define RT5621_GLOBAL_CLK_CTRL_REG 0X42 //GLOBAL CLOCK CONTROL REGISTER
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#define RT5621_PLL_CTRL 0X44 //PLL CONTROL
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#define RT5621_GPIO_OUTPUT_PIN_CTRL 0X4A //GPIO OUTPUT PIN CONTROL
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#define RT5621_GPIO_PIN_CONFIG 0X4C //GPIO PIN CONFIGURATION
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#define RT5621_GPIO_PIN_POLARITY 0X4E //GPIO PIN POLARITY/TYPE
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#define RT5621_GPIO_PIN_STICKY 0X50 //GPIO PIN STICKY
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#define RT5621_GPIO_PIN_WAKEUP 0X52 //GPIO PIN WAKE UP
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#define RT5621_GPIO_PIN_STATUS 0X54 //GPIO PIN STATUS
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#define RT5621_GPIO_PIN_SHARING 0X56 //GPIO PIN SHARING
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#define RT5621_OVER_TEMP_CURR_STATUS 0X58 //OVER TEMPERATURE AND CURRENT STATUS
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#define RT5621_JACK_DET_CTRL 0X5A //JACK DETECT CONTROL REGISTER
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#define RT5621_MISC_CTRL 0X5E //MISC CONTROL
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#define RT5621_PSEDUEO_SPATIAL_CTRL 0X60 //PSEDUEO STEREO & SPATIAL EFFECT BLOCK CONTROL
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#define RT5621_EQ_CTRL 0X62 //EQ CONTROL
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#define RT5621_EQ_MODE_ENABLE 0X66 //EQ MODE CHANGE ENABLE
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#define RT5621_AVC_CTRL 0X68 //AVC CONTROL
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#define RT5621_HID_CTRL_INDEX 0X6A //HIDDEN CONTROL INDEX PORT
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#define RT5621_HID_CTRL_DATA 0X6C //HIDDEN CONTROL DATA PORT
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#define RT5621_VENDOR_ID1 0x7C //VENDOR ID1
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#define RT5621_VENDOR_ID2 0x7E //VENDOR ID2
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//global definition
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#define RT_L_MUTE (0x1<<15) //MUTE LEFT CONTROL BIT
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#define RT_L_ZC (0x1<<14) //LEFT ZERO CROSS CONTROL BIT
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#define RT_L_SM (0x1<<13) //LEFT SOFTMUTE CONTROL BIT
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#define RT_R_MUTE (0x1<<7) //MUTE RIGHT CONTROL BIT
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#define RT_R_ZC (0x1<<6) //RIGHT ZERO CROSS CONTROL BIT
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#define RT_R_SM (0x1<<5) //RIGHT SOFTMUTE CONTROL BIT
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#define RT_M_HP_MIXER (0x1<<15) //Mute source to HP Mixer
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#define RT_M_SPK_MIXER (0x1<<14) //Mute source to Speaker Mixer
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#define RT_M_MONO_MIXER (0x1<<13) //Mute source to Mono Mixer
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#define SPK_CLASS_AB 0
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#define SPK_CLASS_D 1
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//Mic Routing Control(0x10)
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#define M_MIC1_TO_HP_MIXER (0x1<<15) //Mute MIC1 to HP mixer
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#define M_MIC1_TO_SPK_MIXER (0x1<<14) //Mute MiC1 to SPK mixer
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#define M_MIC1_TO_MONO_MIXER (0x1<<13) //Mute MIC1 to MONO mixer
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#define MIC1_DIFF_INPUT_CTRL (0x1<<12) //MIC1 different input control
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#define M_MIC2_TO_HP_MIXER (0x1<<7) //Mute MIC2 to HP mixer
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#define M_MIC2_TO_SPK_MIXER (0x1<<6) //Mute MiC2 to SPK mixer
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#define M_MIC2_TO_MONO_MIXER (0x1<<5) //Mute MIC2 to MONO mixer
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#define MIC2_DIFF_INPUT_CTRL (0x1<<4) //MIC2 different input control
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//ADC Record Gain(0x12)
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#define M_ADC_L_TO_HP_MIXER (0x1<<15) //Mute left of ADC to HP Mixer
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#define M_ADC_R_TO_HP_MIXER (0x1<<14) //Mute right of ADC to HP Mixer
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#define M_ADC_L_TO_MONO_MIXER (0x1<<13) //Mute left of ADC to MONO Mixer
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#define M_ADC_R_TO_MONO_MIXER (0x1<<12) //Mute right of ADC to MONO Mixer
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#define ADC_L_GAIN_MASK (0x1f<<7) //ADC Record Gain Left channel Mask
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#define ADC_L_ZC_DET (0x1<<6) //ADC Zero-Cross Detector Control
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#define ADC_R_ZC_DET (0x1<<5) //ADC Zero-Cross Detector Control
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#define ADC_R_GAIN_MASK (0x1f<<0) //ADC Record Gain Right channel Mask
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//ADC Input Mixer Control(0x14)
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#define M_MIC1_TO_ADC_L_MIXER (0x1<<14) //Mute mic1 to left channel of ADC mixer
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#define M_MIC2_TO_ADC_L_MIXER (0x1<<13) //Mute mic2 to left channel of ADC mixer
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#define M_LINEIN_L_TO_ADC_L_MIXER (0x1<<12) //Mute line In left channel to left channel of ADC mixer
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#define M_AUXIN_L_TO_ADC_L_MIXER (0x1<<11) //Mute aux In left channel to left channel of ADC mixer
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#define M_HPMIXER_L_TO_ADC_L_MIXER (0x1<<10) //Mute HP mixer left channel to left channel of ADC mixer
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#define M_SPKMIXER_L_TO_ADC_L_MIXER (0x1<<9) //Mute SPK mixer left channel to left channel of ADC mixer
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#define M_MONOMIXER_L_TO_ADC_L_MIXER (0x1<<8) //Mute MONO mixer left channel to left channel of ADC mixer
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#define M_MIC1_TO_ADC_R_MIXER (0x1<<6) //Mute mic1 to right channel of ADC mixer
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#define M_MIC2_TO_ADC_R_MIXER (0x1<<5) //Mute mic2 to right channel of ADC mixer
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#define M_LINEIN_R_TO_ADC_R_MIXER (0x1<<4) //Mute lineIn right channel to right channel of ADC mixer
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#define M_AUXIN_R_TO_ADC_R_MIXER (0x1<<3) //Mute aux In right channel to right channel of ADC mixer
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#define M_HPMIXER_R_TO_ADC_R_MIXER (0x1<<2) //Mute HP mixer right channel to right channel of ADC mixer
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#define M_SPKMIXER_R_TO_ADC_R_MIXER (0x1<<1) //Mute SPK mixer right channel to right channel of ADC mixer
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#define M_MONOMIXER_R_TO_ADC_R_MIXER (0x1<<0) //Mute MONO mixer right channel to right channel of ADC mixer
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//Output Mixer Control(0x1C)
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#define SPKOUT_N_SOUR_MASK (0x3<<14)
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#define SPKOUT_N_SOUR_LN (0x2<<14)
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#define SPKOUT_N_SOUR_RP (0x1<<14)
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#define SPKOUT_N_SOUR_RN (0x0<<14)
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#define SPK_OUTPUT_CLASS_AB (0x0<<13)
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#define SPK_OUTPUT_CLASS_D (0x1<<13)
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#define SPK_CLASS_AB_S_AMP (0x0<<12)
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#define SPK_CALSS_AB_W_AMP (0x1<<12)
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#define SPKOUT_INPUT_SEL_MASK (0x3<<10)
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#define SPKOUT_INPUT_SEL_MONOMIXER (0x3<<10)
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#define SPKOUT_INPUT_SEL_SPKMIXER (0x2<<10)
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#define SPKOUT_INPUT_SEL_HPMIXER (0x1<<10)
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#define SPKOUT_INPUT_SEL_VMID (0x0<<10)
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#define HPL_INPUT_SEL_HPLMIXER (0x1<<9)
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#define HPR_INPUT_SEL_HPRMIXER (0x1<<8)
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#define MONO_AUX_INPUT_SEL_MASK (0x3<<6)
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#define MONO_AUX_INPUT_SEL_MONO (0x3<<6)
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#define MONO_AUX_INPUT_SEL_SPK (0x2<<6)
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#define MONO_AUX_INPUT_SEL_HP (0x1<<6)
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#define MONO_AUX_INPUT_SEL_VMID (0x0<<6)
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//Micphone Control define(0x22)
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#define MIC1 1
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#define MIC2 2
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#define MIC_BIAS_90_PRECNET_AVDD 1
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#define MIC_BIAS_75_PRECNET_AVDD 2
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#define MIC1_BOOST_CTRL_MASK (0x3<<10)
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#define MIC1_BOOST_CTRL_BYPASS (0x0<<10)
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#define MIC1_BOOST_CTRL_20DB (0x1<<10)
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#define MIC1_BOOST_CTRL_30DB (0x2<<10)
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#define MIC1_BOOST_CTRL_40DB (0x3<<10)
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#define MIC2_BOOST_CTRL_MASK (0x3<<8)
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#define MIC2_BOOST_CTRL_BYPASS (0x0<<8)
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#define MIC2_BOOST_CTRL_20DB (0x1<<8)
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#define MIC2_BOOST_CTRL_30DB (0x2<<8)
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#define MIC2_BOOST_CTRL_40DB (0x3<<8)
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#define MICBIAS_VOLT_CTRL_MASK (0x1<<5)
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#define MICBIAS_VOLT_CTRL_90P (0x0<<5)
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#define MICBIAS_VOLT_CTRL_75P (0x1<<5)
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#define MICBIAS_SHORT_CURR_DET_MASK (0x3)
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#define MICBIAS_SHORT_CURR_DET_600UA (0x0)
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#define MICBIAS_SHORT_CURR_DET_1200UA (0x1)
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#define MICBIAS_SHORT_CURR_DET_1800UA (0x2)
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//Audio Interface(0x34)
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#define SDP_MASTER_MODE (0x0<<15) //Main I2S interface select Master mode
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#define SDP_SLAVE_MODE (0x1<<15) //Main I2S interface select Slave mode
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#define I2S_PCM_MODE (0x1<<14) //PCM 0:mode A ,1:mode B
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#define MAIN_I2S_BCLK_POL_CTRL (0x1<<7) //0:Normal 1:Invert
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#define ADC_DATA_L_R_SWAP (0x1<<5) //0:ADC data appear at left phase of LRCK
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//1:ADC data appear at right phase of LRCK
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#define DAC_DATA_L_R_SWAP (0x1<<4) //0:DAC data appear at left phase of LRCK
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//1:DAC data appear at right phase of LRCK
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//Data Length Slection
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#define I2S_DL_MASK (0x3<<2) //main i2s Data Length mask
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#define I2S_DL_16 (0x0<<2) //16 bits
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#define I2S_DL_20 (0x1<<2) //20 bits
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#define I2S_DL_24 (0x2<<2) //24 bits
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#define I2S_DL_32 (0x3<<2) //32 bits
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//PCM Data Format Selection
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#define I2S_DF_MASK (0x3) //main i2s Data Format mask
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#define I2S_DF_I2S (0x0) //I2S FORMAT
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#define I2S_DF_RIGHT (0x1) //RIGHT JUSTIFIED format
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#define I2S_DF_LEFT (0x2) //LEFT JUSTIFIED format
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#define I2S_DF_PCM (0x3) //PCM format
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//Stereo AD/DA Clock Control(0x36h)
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#define I2S_PRE_DIV_MASK (0x7<<12)
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#define I2S_PRE_DIV_1 (0x0<<12) //DIV 1
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#define I2S_PRE_DIV_2 (0x1<<12) //DIV 2
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#define I2S_PRE_DIV_4 (0x2<<12) //DIV 4
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#define I2S_PRE_DIV_8 (0x3<<12) //DIV 8
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#define I2S_PRE_DIV_16 (0x4<<12) //DIV 16
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#define I2S_PRE_DIV_32 (0x5<<12) //DIV 32
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#define I2S_SCLK_DIV_MASK (0x7<<9)
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#define I2S_SCLK_DIV_1 (0x0<<9) //DIV 1
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#define I2S_SCLK_DIV_2 (0x1<<9) //DIV 2
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#define I2S_SCLK_DIV_3 (0x2<<9) //DIV 3
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#define I2S_SCLK_DIV_4 (0x3<<9) //DIV 4
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#define I2S_SCLK_DIV_6 (0x4<<9) //DIV 6
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#define I2S_SCLK_DIV_8 (0x5<<9) //DIV 8
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#define I2S_SCLK_DIV_12 (0x6<<9) //DIV 12
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#define I2S_SCLK_DIV_16 (0x7<<9) //DIV 16
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#define I2S_WCLK_DIV_PRE_MASK (0xF<<5)
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#define I2S_WCLK_PRE_DIV_1 (0x0<<5) //DIV 1
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#define I2S_WCLK_PRE_DIV_2 (0x1<<5) //DIV 2
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#define I2S_WCLK_PRE_DIV_3 (0x2<<5) //DIV 3
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#define I2S_WCLK_PRE_DIV_4 (0x3<<5) //DIV 4
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#define I2S_WCLK_PRE_DIV_5 (0x4<<5) //DIV 5
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#define I2S_WCLK_PRE_DIV_6 (0x5<<5) //DIV 6
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#define I2S_WCLK_PRE_DIV_7 (0x6<<5) //DIV 7
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#define I2S_WCLK_PRE_DIV_8 (0x7<<5) //DIV 8
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//........................
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#define I2S_WCLK_DIV_MASK (0x7<<2)
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#define I2S_WCLK_DIV_2 (0x0<<2) //DIV 2
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#define I2S_WCLK_DIV_4 (0x1<<2) //DIV 4
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#define I2S_WCLK_DIV_8 (0x2<<2) //DIV 8
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#define I2S_WCLK_DIV_16 (0x3<<2) //DIV 16
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#define I2S_WCLK_DIV_32 (0x4<<2) //DIV 32
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#define ADDA_FILTER_CLK_SEL_256FS (0<<1) //256FS
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#define ADDA_FILTER_CLK_SEL_384FS (1<<1) //384FS
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#define ADDA_OSR_SEL_64FS (0) //64FS
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#define ADDA_OSR_SEL_128FS (1) //128FS
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//Power managment addition 1 (0x3A),0:Disable,1:Enable
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#define PWR_MAIN_I2S_EN (0x1<<15)
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#define PWR_ZC_DET_PD_EN (0x1<<14)
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#define PWR_MIC1_BIAS_EN (0x1<<11)
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#define PWR_SHORT_CURR_DET_EN (0x1<<10)
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#define PWR_SOFTGEN_EN (0x1<<8)
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#define PWR_DEPOP_BUF_HP (0x1<<6)
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#define PWR_HP_OUT_AMP (0x1<<5)
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#define PWR_HP_OUT_ENH_AMP (0x1<<4)
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#define PWR_DEPOP_BUF_AUX (0x1<<2)
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#define PWR_AUX_OUT_AMP (0x1<<1)
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#define PWR_AUX_OUT_ENH_AMP (0x1)
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//Power managment addition 2(0x3C),0:Disable,1:Enable
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#define PWR_CLASS_AB (0x1<<15)
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#define PWR_CLASS_D (0x1<<14)
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#define PWR_VREF (0x1<<13)
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#define PWR_PLL (0x1<<12)
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#define PWR_DAC_REF_CIR (0x1<<10)
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#define PWR_L_DAC_CLK (0x1<<9)
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#define PWR_R_DAC_CLK (0x1<<8)
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#define PWR_L_ADC_CLK_GAIN (0x1<<7)
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#define PWR_R_ADC_CLK_GAIN (0x1<<6)
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#define PWR_L_HP_MIXER (0x1<<5)
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#define PWR_R_HP_MIXER (0x1<<4)
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#define PWR_SPK_MIXER (0x1<<3)
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#define PWR_MONO_MIXER (0x1<<2)
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#define PWR_L_ADC_REC_MIXER (0x1<<1)
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#define PWR_R_ADC_REC_MIXER (0x1)
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//Power managment addition 3(0x3E),0:Disable,1:Enable
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#define PWR_MAIN_BIAS (0x1<<15)
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#define PWR_AUXOUT_L_VOL_AMP (0x1<<14)
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#define PWR_AUXOUT_R_VOL_AMP (0x1<<13)
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#define PWR_SPK_OUT (0x1<<12)
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#define PWR_HP_L_OUT_VOL (0x1<<10)
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#define PWR_HP_R_OUT_VOL (0x1<<9)
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#define PWR_LINEIN_L_VOL (0x1<<7)
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#define PWR_LINEIN_R_VOL (0x1<<6)
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#define PWR_AUXIN_L_VOL (0x1<<5)
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#define PWR_AUXIN_R_VOL (0x1<<4)
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#define PWR_MIC1_FUN_CTRL (0x1<<3)
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#define PWR_MIC2_FUN_CTRL (0x1<<2)
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#define PWR_MIC1_BOOST_MIXER (0x1<<1)
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#define PWR_MIC2_BOOST_MIXER (0x1)
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//Additional Control Register(0x40)
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#define AUXOUT_SEL_DIFF (0x1<<15) //Differential Mode
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#define AUXOUT_SEL_SE (0x1<<15) //Single-End Mode
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#define SPK_AB_AMP_CTRL_MASK (0x7<<12)
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#define SPK_AB_AMP_CTRL_RATIO_225 (0x0<<12) //2.25 Vdd
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#define SPK_AB_AMP_CTRL_RATIO_200 (0x1<<12) //2.00 Vdd
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#define SPK_AB_AMP_CTRL_RATIO_175 (0x2<<12) //1.75 Vdd
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#define SPK_AB_AMP_CTRL_RATIO_150 (0x3<<12) //1.50 Vdd
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#define SPK_AB_AMP_CTRL_RATIO_125 (0x4<<12) //1.25 Vdd
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#define SPK_AB_AMP_CTRL_RATIO_100 (0x5<<12) //1.00 Vdd
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#define SPK_D_AMP_CTRL_MASK (0x3<<10)
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#define SPK_D_AMP_CTRL_RATIO_175 (0x0<<10) //1.75 Vdd
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#define SPK_D_AMP_CTRL_RATIO_150 (0x1<<10) //1.50 Vdd
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#define SPK_D_AMP_CTRL_RATIO_125 (0x2<<10) //1.25 Vdd
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#define SPK_D_AMP_CTRL_RATIO_100 (0x3<<10) //1.00 Vdd
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#define STEREO_DAC_HI_PASS_FILTER_EN (0x1<<9) //Stereo DAC high pass filter enable
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#define STEREO_ADC_HI_PASS_FILTER_EN (0x1<<8) //Stereo ADC high pass filter enable
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#define DIG_VOL_BOOST_MASK (0x3<<4) //Digital volume Boost mask
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#define DIG_VOL_BOOST_0DB (0x0<<4) //Digital volume Boost 0DB
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#define DIG_VOL_BOOST_6DB (0x1<<4) //Digital volume Boost 6DB
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#define DIG_VOL_BOOST_12DB (0x2<<4) //Digital volume Boost 12DB
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#define DIG_VOL_BOOST_18DB (0x3<<4) //Digital volume Boost 18DB
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//Global Clock Control Register(0x42)
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#define SYSCLK_SOUR_SEL_MASK (0x1<<15)
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#define SYSCLK_SOUR_SEL_MCLK (0x0<<15) //system Clock source from MCLK
|
||||
#define SYSCLK_SOUR_SEL_PLL (0x1<<15) //system Clock source from PLL
|
||||
#define PLLCLK_SOUR_SEL_MCLK (0x0<<14) //PLL clock source from MCLK
|
||||
#define PLLCLK_SOUR_SEL_BITCLK (0x1<<14) //PLL clock source from BITCLK
|
||||
|
||||
#define PLLCLK_DIV_RATIO_MASK (0x3<<1)
|
||||
#define PLLCLK_DIV_RATIO_DIV1 (0x0<<1) //DIV 1
|
||||
#define PLLCLK_DIV_RATIO_DIV2 (0x1<<1) //DIV 2
|
||||
#define PLLCLK_DIV_RATIO_DIV4 (0x2<<1) //DIV 4
|
||||
#define PLLCLK_DIV_RATIO_DIV8 (0x3<<1) //DIV 8
|
||||
|
||||
#define PLLCLK_PRE_DIV1 (0x0) //DIV 1
|
||||
#define PLLCLK_PRE_DIV2 (0x1) //DIV 2
|
||||
|
||||
//PLL Control(0x44)
|
||||
|
||||
#define PLL_CTRL_M_VAL(m) ((m)&0xf)
|
||||
#define PLL_CTRL_K_VAL(k) (((k)&0x7)<<4)
|
||||
#define PLL_CTRL_N_VAL(n) (((n)&0xff)<<8)
|
||||
|
||||
//GPIO Pin Configuration(0x4C)
|
||||
#define GPIO_PIN_MASK (0x1<<1)
|
||||
#define GPIO_PIN_SET_INPUT (0x1<<1)
|
||||
#define GPIO_PIN_SET_OUTPUT (0x0<<1)
|
||||
|
||||
//Pin Sharing(0x56)
|
||||
#define LINEIN_L_PIN_SHARING (0x1<<15)
|
||||
#define LINEIN_L_PIN_AS_LINEIN_L (0x0<<15)
|
||||
#define LINEIN_L_PIN_AS_JD1 (0x1<<15)
|
||||
|
||||
#define LINEIN_R_PIN_SHARING (0x1<<14)
|
||||
#define LINEIN_R_PIN_AS_LINEIN_R (0x0<<14)
|
||||
#define LINEIN_R_PIN_AS_JD2 (0x1<<14)
|
||||
|
||||
#define GPIO_PIN_SHARING (0x3)
|
||||
#define GPIO_PIN_AS_GPIO (0x0)
|
||||
#define GPIO_PIN_AS_IRQOUT (0x1)
|
||||
#define GPIO_PIN_AS_PLLOUT (0x3)
|
||||
|
||||
//Jack Detect Control Register(0x5A)
|
||||
#define JACK_DETECT_MASK (0x3<<14)
|
||||
#define JACK_DETECT_USE_JD2 (0x3<<14)
|
||||
#define JACK_DETECT_USE_JD1 (0x2<<14)
|
||||
#define JACK_DETECT_USE_GPIO (0x1<<14)
|
||||
#define JACK_DETECT_OFF (0x0<<14)
|
||||
|
||||
#define SPK_EN_IN_HI (0x1<<11)
|
||||
#define AUX_R_EN_IN_HI (0x1<<10)
|
||||
#define AUX_L_EN_IN_HI (0x1<<9)
|
||||
#define HP_EN_IN_HI (0x1<<8)
|
||||
#define SPK_EN_IN_LO (0x1<<7)
|
||||
#define AUX_R_EN_IN_LO (0x1<<6)
|
||||
#define AUX_L_EN_IN_LO (0x1<<5)
|
||||
#define HP_EN_IN_LO (0x1<<4)
|
||||
|
||||
////MISC CONTROL(0x5E)
|
||||
#define DISABLE_FAST_VREG (0x1<<15)
|
||||
#define SPK_CLASS_AB_OC_PD (0x1<<13)
|
||||
#define SPK_CLASS_AB_OC_DET (0x1<<12)
|
||||
#define HP_DEPOP_MODE3_EN (0x1<<10)
|
||||
#define HP_DEPOP_MODE2_EN (0x1<<9)
|
||||
#define HP_DEPOP_MODE1_EN (0x1<<8)
|
||||
#define AUXOUT_DEPOP_MODE3_EN (0x1<<6)
|
||||
#define AUXOUT_DEPOP_MODE2_EN (0x1<<5)
|
||||
#define AUXOUT_DEPOP_MODE1_EN (0x1<<4)
|
||||
#define M_DAC_L_INPUT (0x1<<3)
|
||||
#define M_DAC_R_INPUT (0x1<<2)
|
||||
#define IRQOUT_INV_CTRL (0x1<<0)
|
||||
|
||||
//Psedueo Stereo & Spatial Effect Block Control(0x60)
|
||||
#define SPATIAL_CTRL_EN (0x1<<15)
|
||||
#define ALL_PASS_FILTER_EN (0x1<<14)
|
||||
#define PSEUDO_STEREO_EN (0x1<<13)
|
||||
#define STEREO_EXPENSION_EN (0x1<<12)
|
||||
|
||||
#define GAIN_3D_PARA_L_MASK (0x7<<9)
|
||||
#define GAIN_3D_PARA_L_1_00 (0x0<<9)
|
||||
#define GAIN_3D_PARA_L_1_25 (0x1<<9)
|
||||
#define GAIN_3D_PARA_L_1_50 (0x2<<9)
|
||||
#define GAIN_3D_PARA_L_1_75 (0x3<<9)
|
||||
#define GAIN_3D_PARA_L_2_00 (0x4<<9)
|
||||
|
||||
#define GAIN_3D_PARA_R_MASK (0x7<<6)
|
||||
#define GAIN_3D_PARA_R_1_00 (0x0<<6)
|
||||
#define GAIN_3D_PARA_R_1_25 (0x1<<6)
|
||||
#define GAIN_3D_PARA_R_1_50 (0x2<<6)
|
||||
#define GAIN_3D_PARA_R_1_75 (0x3<<6)
|
||||
#define GAIN_3D_PARA_R_2_00 (0x4<<6)
|
||||
|
||||
#define RATIO_3D_L_MASK (0x3<<4)
|
||||
#define RATIO_3D_L_0_0 (0x0<<4)
|
||||
#define RATIO_3D_L_0_66 (0x1<<4)
|
||||
#define RATIO_3D_L_1_0 (0x2<<4)
|
||||
|
||||
#define RATIO_3D_R_MASK (0x3<<2)
|
||||
#define RATIO_3D_R_0_0 (0x0<<2)
|
||||
#define RATIO_3D_R_0_66 (0x1<<2)
|
||||
#define RATIO_3D_R_1_0 (0x2<<2)
|
||||
|
||||
#define APF_MASK (0x3)
|
||||
#define APF_FOR_48K (0x3)
|
||||
#define APF_FOR_44_1K (0x2)
|
||||
#define APF_FOR_32K (0x1)
|
||||
|
||||
//EQ CONTROL(0x62)
|
||||
|
||||
#define EN_HW_EQ_BLK (0x1<<15) //HW EQ block control
|
||||
#define EN_HW_EQ_HPF_MODE (0x1<<14) //High Frequency shelving filter mode
|
||||
#define EN_HW_EQ_SOUR (0x1<<11) //0:DAC PATH,1:ADC PATH
|
||||
#define EN_HW_EQ_HPF (0x1<<4) //EQ High Pass Filter Control
|
||||
#define EN_HW_EQ_BP3 (0x1<<3) //EQ Band-3 Control
|
||||
#define EN_HW_EQ_BP2 (0x1<<2) //EQ Band-2 Control
|
||||
#define EN_HW_EQ_BP1 (0x1<<1) //EQ Band-1 Control
|
||||
#define EN_HW_EQ_LPF (0x1<<0) //EQ Low Pass Filter Control
|
||||
|
||||
//EQ Mode Change Enable(0x66)
|
||||
#define EQ_HPF_CHANGE_EN (0x1<<4) //EQ High Pass Filter Mode Change Enable
|
||||
#define EQ_BP3_CHANGE_EN (0x1<<3) //EQ Band-3 Pass Filter Mode Change Enable
|
||||
#define EQ_BP2_CHANGE_EN (0x1<<2) //EQ Band-2 Pass Filter Mode Change Enable
|
||||
#define EQ_BP1_CHANGE_EN (0x1<<1) //EQ Band-1 Pass Filter Mode Change Enable
|
||||
#define EQ_LPF_CHANGE_EN (0x1<<0) //EQ Low Pass Filter Mode Change Enable
|
||||
|
||||
|
||||
//AVC Control(0x68)
|
||||
#define AVC_ENABLE (0x1<<15)
|
||||
#define AVC_TARTGET_SEL_MASK (0x1<<14)
|
||||
#define AVC_TARTGET_SEL_R (0x1<<14)
|
||||
#define AVC_TARTGET_SEL_L (0x0<<14)
|
||||
|
||||
|
||||
struct rt5621_setup_data {
|
||||
unsigned short i2c_address;
|
||||
unsigned short i2c_bus;
|
||||
};
|
||||
|
||||
|
||||
|
||||
#define RT5621_PLL_FR_MCLK 0
|
||||
#define RT5621_PLL_FR_BCLK 1
|
||||
|
||||
|
||||
#define USE_DAPM_CONTROL 0
|
||||
#define REALTEK_HWDEP 0
|
||||
|
||||
//WaveOut channel for realtek codec
|
||||
enum
|
||||
{
|
||||
RT_WAVOUT_SPK =(0x1<<0),
|
||||
RT_WAVOUT_SPK_R =(0x1<<1),
|
||||
RT_WAVOUT_SPK_L =(0x1<<2),
|
||||
RT_WAVOUT_HP =(0x1<<3),
|
||||
RT_WAVOUT_HP_R =(0x1<<4),
|
||||
RT_WAVOUT_HP_L =(0x1<<5),
|
||||
RT_WAVOUT_MONO =(0x1<<6),
|
||||
RT_WAVOUT_AUXOUT =(0x1<<7),
|
||||
RT_WAVOUT_AUXOUT_R =(0x1<<8),
|
||||
RT_WAVOUT_AUXOUT_L =(0x1<<9),
|
||||
RT_WAVOUT_LINEOUT =(0x1<<10),
|
||||
RT_WAVOUT_LINEOUT_R =(0x1<<11),
|
||||
RT_WAVOUT_LINEOUT_L =(0x1<<12),
|
||||
RT_WAVOUT_DAC =(0x1<<13),
|
||||
RT_WAVOUT_ALL_ON =(0x1<<14),
|
||||
};
|
||||
|
||||
//WaveIn channel for realtek codec
|
||||
enum
|
||||
{
|
||||
RT_WAVIN_R_MONO_MIXER =(0x1<<0),
|
||||
RT_WAVIN_R_SPK_MIXER =(0x1<<1),
|
||||
RT_WAVIN_R_HP_MIXER =(0x1<<2),
|
||||
RT_WAVIN_R_PHONE =(0x1<<3),
|
||||
RT_WAVIN_R_AUXIN =(0x1<<3),
|
||||
RT_WAVIN_R_LINE_IN =(0x1<<4),
|
||||
RT_WAVIN_R_MIC2 =(0x1<<5),
|
||||
RT_WAVIN_R_MIC1 =(0x1<<6),
|
||||
|
||||
RT_WAVIN_L_MONO_MIXER =(0x1<<8),
|
||||
RT_WAVIN_L_SPK_MIXER =(0x1<<9),
|
||||
RT_WAVIN_L_HP_MIXER =(0x1<<10),
|
||||
RT_WAVIN_L_PHONE =(0x1<<11),
|
||||
RT_WAVIN_L_AUXIN =(0x1<<11),
|
||||
RT_WAVIN_L_LINE_IN =(0x1<<12),
|
||||
RT_WAVIN_L_MIC2 =(0x1<<13),
|
||||
RT_WAVIN_L_MIC1 =(0x1<<14),
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
POWER_STATE_D0=0,
|
||||
POWER_STATE_D1,
|
||||
POWER_STATE_D1_PLAYBACK,
|
||||
POWER_STATE_D1_RECORD,
|
||||
POWER_STATE_D2,
|
||||
POWER_STATE_D2_PLAYBACK,
|
||||
POWER_STATE_D2_RECORD,
|
||||
POWER_STATE_D3,
|
||||
POWER_STATE_D4
|
||||
|
||||
};
|
||||
|
||||
#if REALTEK_HWDEP
|
||||
|
||||
struct rt56xx_reg_state
|
||||
{
|
||||
unsigned int reg_index;
|
||||
unsigned int reg_value;
|
||||
};
|
||||
|
||||
struct rt56xx_cmd
|
||||
{
|
||||
size_t number;
|
||||
struct rt56xx_reg_state __user *buf;
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
RT_READ_CODEC_REG_IOCTL = _IOR('R', 0x01, struct rt56xx_cmd),
|
||||
RT_READ_ALL_CODEC_REG_IOCTL = _IOR('R', 0x02, struct rt56xx_cmd),
|
||||
RT_WRITE_CODEC_REG_IOCTL = _IOW('R', 0x03, struct rt56xx_cmd),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
extern struct snd_soc_dai rt5621_dai;
|
||||
extern struct snd_soc_codec_device soc_codec_dev_rt5621;
|
||||
|
||||
#endif
|
||||
@@ -1,229 +0,0 @@
|
||||
/*
|
||||
* rk29_rt5621.c -- SoC audio for rockchip
|
||||
*
|
||||
* Driver for rockchip rt5621 audio
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/device.h>
|
||||
#include <sound/core.h>
|
||||
#include <sound/pcm.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/soc-dapm.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/rk29_iomap.h>
|
||||
#include "../codecs/rt5621.h"
|
||||
#include "rk29_pcm.h"
|
||||
#include "rk29_i2s.h"
|
||||
|
||||
#if 0
|
||||
#define DBG(x...) printk(KERN_INFO x)
|
||||
#else
|
||||
#define DBG(x...)
|
||||
#endif
|
||||
|
||||
static int rk29_hw_params(struct snd_pcm_substream *substream,
|
||||
struct snd_pcm_hw_params *params)
|
||||
{
|
||||
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
||||
struct snd_soc_dai *codec_dai = rtd->codec_dai;
|
||||
struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
|
||||
unsigned int pll_out = 0;
|
||||
unsigned int lrclk = 0;
|
||||
int ret;
|
||||
|
||||
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
|
||||
|
||||
/*by Vincent Hsiung for EQ Vol Change*/
|
||||
#define HW_PARAMS_FLAG_EQVOL_ON 0x21
|
||||
#define HW_PARAMS_FLAG_EQVOL_OFF 0x22
|
||||
if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF))
|
||||
{
|
||||
ret = codec_dai->driver->ops->hw_params(substream, params, codec_dai); //by Vincent
|
||||
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
|
||||
} else {
|
||||
/* set codec DAI configuration */
|
||||
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
|
||||
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
|
||||
SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
|
||||
#endif
|
||||
#if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
|
||||
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
|
||||
SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM );
|
||||
#endif
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
/* set cpu DAI configuration */
|
||||
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
|
||||
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
|
||||
SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM);
|
||||
#endif
|
||||
#if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
|
||||
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
|
||||
SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
|
||||
#endif
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
switch(params_rate(params)) {
|
||||
case 8000:
|
||||
case 16000:
|
||||
case 24000:
|
||||
case 32000:
|
||||
case 48000:
|
||||
pll_out = 12288000;
|
||||
break;
|
||||
case 11025:
|
||||
case 22050:
|
||||
case 44100:
|
||||
pll_out = 11289600;
|
||||
break;
|
||||
default:
|
||||
DBG("Enter:%s, %d, Error rate=%d\n",__FUNCTION__,__LINE__,params_rate(params));
|
||||
return -EINVAL;
|
||||
break;
|
||||
}
|
||||
DBG("Enter:%s, %d, rate=%d\n",__FUNCTION__,__LINE__,params_rate(params));
|
||||
|
||||
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
|
||||
#if 0 //use pll from blck
|
||||
/*Set the pll of rt5621,the Pll source from BITCLK on CPU is master mode*/
|
||||
//bitclk is 64fs
|
||||
ret=snd_soc_dai_set_pll(codec_dai,RT5621_PLL_FR_BCLK,params_rate(params)*64,pll_out);
|
||||
if (ret < 0) {
|
||||
DBG("rk29_hw_params_rt5621:failed to set the pll for codec side\n");
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
/*Set the system clk for codec*/
|
||||
ret=snd_soc_dai_set_sysclk(codec_dai, 0,pll_out,SND_SOC_CLOCK_IN);
|
||||
if (ret < 0) {
|
||||
DBG("rk29_hw_params_rt5621:failed to set the sysclk for codec side\n");
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER)
|
||||
|
||||
if((24576000%params_rate(params))==0) //for 8k,16k,32k,48k
|
||||
{
|
||||
snd_soc_dai_set_pll(codec_dai,RT5621_PLL_FR_MCLK,pll_out, 24576000);
|
||||
snd_soc_dai_set_sysclk(codec_dai,0, 24576000, SND_SOC_CLOCK_IN);
|
||||
}
|
||||
else if((22579200%params_rate(params))==0) //for 11k,22k,44k
|
||||
{
|
||||
snd_soc_dai_set_pll(codec_dai,RT5621_PLL_FR_MCLK,pll_out, 22579200);
|
||||
snd_soc_dai_set_sysclk(codec_dai,0, 22579200, SND_SOC_CLOCK_IN);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
|
||||
snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0);
|
||||
snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK, (pll_out/4)/params_rate(params)-1);
|
||||
snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 3);
|
||||
#endif
|
||||
|
||||
DBG("Enter:%s, %d, LRCK=%d\n",__FUNCTION__,__LINE__,(pll_out/4)/params_rate(params));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct snd_soc_dapm_widget rt5621_dapm_widgets[] = {
|
||||
|
||||
SND_SOC_DAPM_MIC("Mic Jack", NULL),
|
||||
SND_SOC_DAPM_SPK("Ext Spk", NULL),
|
||||
SND_SOC_DAPM_HP("Headphone Jack", NULL),
|
||||
|
||||
};
|
||||
|
||||
static const struct snd_soc_dapm_route audio_map[]={
|
||||
|
||||
/* Mic Jack --> MIC_IN*/
|
||||
{"Mic Bias1", NULL, "Mic Jack"},
|
||||
{"MIC1", NULL, "Mic Bias1"},
|
||||
/* HP_OUT --> Headphone Jack */
|
||||
{"Headphone Jack", NULL, "HPOL"},
|
||||
{"Headphone Jack", NULL, "HPOR"},
|
||||
/* LINE_OUT --> Ext Speaker */
|
||||
{"Ext Spk", NULL, "SPOL"},
|
||||
{"Ext Spk", NULL, "SPOR"},
|
||||
|
||||
} ;
|
||||
|
||||
/*
|
||||
* Logic for a rt5621 as connected on a rockchip board.
|
||||
*/
|
||||
static int rk29_wm8988_init(struct snd_soc_pcm_runtime *rtd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct snd_soc_ops rk29_ops = {
|
||||
.hw_params = rk29_hw_params,
|
||||
};
|
||||
|
||||
static struct snd_soc_dai_link rk29_dai = {
|
||||
.name = "RT5621",
|
||||
.stream_name = "RT5621 PCM",
|
||||
.codec_name = "RT5621.0-001a",
|
||||
.platform_name = "rockchip-audio",
|
||||
.cpu_dai_name = "rk29_i2s.0",
|
||||
.codec_dai_name = "RT5621 HiFi",
|
||||
.init = rk29_wm8988_init,
|
||||
.ops = &rk29_ops,
|
||||
};
|
||||
|
||||
static struct snd_soc_card snd_soc_card_rk29 = {
|
||||
.name = "RK29_RT5621",
|
||||
.dai_link = &rk29_dai,
|
||||
.num_links = 1,
|
||||
};
|
||||
|
||||
static struct platform_device *rk29_snd_device;
|
||||
|
||||
static int __init audio_card_init(void)
|
||||
{
|
||||
int ret =0;
|
||||
|
||||
//rk29_speaker = rk29_speaker_init(RK29_PIN6_PB6, GPIO_HIGH, 2, (200*1000*1000));
|
||||
|
||||
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
|
||||
rk29_snd_device = platform_device_alloc("soc-audio", -1);
|
||||
if (!rk29_snd_device) {
|
||||
DBG("platform device allocation failed\n");
|
||||
ret = -ENOMEM;
|
||||
return ret;
|
||||
}
|
||||
platform_set_drvdata(rk29_snd_device, &snd_soc_card_rk29);
|
||||
ret = platform_device_add(rk29_snd_device);
|
||||
if (ret) {
|
||||
DBG("platform device add failed\n");
|
||||
platform_device_put(rk29_snd_device);
|
||||
return ret;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit audio_card_exit(void)
|
||||
{
|
||||
platform_device_unregister(rk29_snd_device);
|
||||
}
|
||||
|
||||
module_init(audio_card_init);
|
||||
module_exit(audio_card_exit);
|
||||
/* Module information */
|
||||
MODULE_AUTHOR("rockchip");
|
||||
MODULE_DESCRIPTION("ROCKCHIP i2s ASoC Interface");
|
||||
MODULE_LICENSE("GPL");
|
||||
Reference in New Issue
Block a user