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hdmitx: optimize hpll suspend

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PD#165090: hdmitx: optimize hpll suspend

The BIT definition of RESET / ENABLE in G12A is different from
earlier chips.
HPLL suspend workflow:
1. set RESET as 1
2. delay 50us
3. set ENABLE as 0
Resume workflow is inverse, but no need anymore, it will be set
in set_disp_mode_auto().

Change-Id: Iefc7f7f026562f566c8a40325c74a53f46465b02
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>
This commit is contained in:
Zongdong Jiao
2018-06-12 10:34:38 +08:00
committed by Yixun Lan
parent 1efcf84db4
commit e8768cd52e
1 changed files with 1 additions and 0 deletions
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1
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
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@@ -2483,6 +2483,7 @@ static int hdmitx_cntl(struct hdmitx_dev *hdev, unsigned int cmd,
/* G12A reset/enable bit position is different */
switch (hdev->chip_type) {
case MESON_CPU_ID_G12A:
case MESON_CPU_ID_G12B:
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 1, 29, 1);
udelay(50);
hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL, 0, 28, 1);