shinys000114/linux
1
0
Fork 0
mirror of https://github.com/hardkernel/linux.git synced 2026-06-10 21:07:02 +09:00
Code Issues Packages Projects Releases Wiki Activity

update DPLL rate after change DDR frequency

Browse Source
This commit is contained in:
hcy
2012-09-28 16:41:23 +08:00
parent 1a7ce41ef4
commit e8ca677ea2
1 changed files with 1 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-rk2928/ddr.c
View File

@@ -2242,6 +2242,7 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
(ddr_get_cap()>>20));
ddr_adjust_config(mem_type);
value=ddr_change_freq(freq);
clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
ddr_print("init success!!! freq=%dMHz\n", value);
calStatusLeft = pPHY_Reg->PHY_REG60;