PD#161616: VC1: 1. support vc1 decoder for G12A

2. Revert the commition of using 8 buffers for all chips
When we fix bug 128904(commit id:d723223bc) by using 8 buffers, but afterward, we
found it caused mosaic for some videos, So i revert it. I also revert the associated
ucode commition for it. This change is fit for all chips, not only G12A.

Change-Id: Idc5d2f96ca9f38208039e23da54e39f3c852e74e
Signed-off-by: Rong Zhang <rong.zhang@amlogic.com>

drivers/amlogic/media_modules/common/firmware/firmware_type.c

@@ -11,6 +11,7 @@ static const struct type_name_s type_name[] = {
 	{VIDEO_DEC_REAL_V8, "real_v8"},
 	{VIDEO_DEC_REAL_V9, "real_v9"},
 	{VIDEO_DEC_VC1, "vc1"},
+	{VIDEO_DEC_VC1_G12A, "vc1_g12a"},
 	{VIDEO_DEC_AVS, "avs"},
 	{VIDEO_DEC_AVS_GXM, "avs_gxm"},
 	{VIDEO_DEC_AVS_NOCABAC, "avs_no_cabac"},

drivers/amlogic/media_modules/common/firmware/firmware_type.h

@@ -36,6 +36,7 @@ enum firmware_type_e {
 	VIDEO_DEC_AVS_NOCABAC,
 	VIDEO_DEC_H264_MULTI_GXM,
 	VIDEO_DEC_H264_MVC_GXM,
+	VIDEO_DEC_VC1_G12A,
 	FIRMWARE_MAX
 };
 

drivers/amlogic/media_modules/frame_provider/decoder/vc1/vvc1.c

@@ -70,12 +70,12 @@
 #define VC1_OFFSET_REG      AV_SCRATCH_C
 #define MEM_OFFSET_REG      AV_SCRATCH_F
 
-#define VF_POOL_SIZE		32
-#define DECODE_BUFFER_NUM_MAX	8
+#define VF_POOL_SIZE		16
+#define DECODE_BUFFER_NUM_MAX	4
 #define WORKSPACE_SIZE		(2 * SZ_1M)
 #define MAX_BMMU_BUFFER_NUM	(DECODE_BUFFER_NUM_MAX + 1)
 #define VF_BUFFER_IDX(n)	(1 + n)
-#define DCAC_BUFF_START_ADDR	0x02e00000
+#define DCAC_BUFF_START_ADDR	0x01f00000
 
 
 #define PUT_INTERVAL        (HZ/100)
@@ -186,8 +186,8 @@ static inline u32 index2canvas(u32 index)
 {
 	const u32 canvas_tab[DECODE_BUFFER_NUM_MAX] = {
 #if 1	/* ALWASY.MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6 */
-		0x010100, 0x030302, 0x050504, 0x070706,
-		0x090908, 0x0b0b0a, 0x0d0d0c, 0x0f0f0e
+	0x010100, 0x030302, 0x050504, 0x070706/*,
+	0x090908, 0x0b0b0a, 0x0d0d0c, 0x0f0f0e*/
 #else
 		0x020100, 0x050403, 0x080706, 0x0b0a09
 #endif
@@ -314,7 +314,7 @@ static irqreturn_t vvc1_isr(int irq, void *dev_id)
 		}
 
 		repeat_count = READ_VREG(VC1_REPEAT_COUNT);
-		buffer_index = reg & 0x7;
+		buffer_index = ((reg & 0x7) - 1) & 3;
 		picture_type = (reg >> 3) & 7;
 
 		if (buffer_index >= DECODE_BUFFER_NUM_MAX) {
@@ -868,10 +868,10 @@ static int vvc1_prot_init(void)
 	WRITE_VREG(AV_SCRATCH_1, 0x030302);
 	WRITE_VREG(AV_SCRATCH_2, 0x050504);
 	WRITE_VREG(AV_SCRATCH_3, 0x070706);
-	WRITE_VREG(AV_SCRATCH_G, 0x090908);
+/*	WRITE_VREG(AV_SCRATCH_G, 0x090908);
 	WRITE_VREG(AV_SCRATCH_H, 0x0b0b0a);
 	WRITE_VREG(AV_SCRATCH_I, 0x0d0d0c);
-	WRITE_VREG(AV_SCRATCH_J, 0x0f0f0e);
+	WRITE_VREG(AV_SCRATCH_J, 0x0f0f0e);*/
 #else
 	WRITE_VREG(AV_SCRATCH_0, 0x020100);
 	WRITE_VREG(AV_SCRATCH_1, 0x050403);
@@ -1029,6 +1029,7 @@ static s32 vvc1_init(void)
 {
 	int ret = -1, size = -1;
 	char *buf = vmalloc(0x1000 * 16);
+	int fw_type = VIDEO_DEC_VC1;
 
 	if (IS_ERR_OR_NULL(buf))
 		return -ENOMEM;
@@ -1054,7 +1055,10 @@ static s32 vvc1_init(void)
 	} else
 		pr_info("not supported VC1 format\n");
 
-	size = get_firmware_data(VIDEO_DEC_VC1, buf);
+	if (get_cpu_type() >= MESON_CPU_MAJOR_ID_G12A)
+		fw_type = VIDEO_DEC_VC1_G12A;
+
+	size = get_firmware_data(fw_type, buf);
 	if (size < 0) {
 		amvdec_disable();
 		pr_err("get firmware fail.");