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phy: rockchip: naneng-combphy: Add config option for pcie1ln-sel

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Add dts decode to support the pcie2x1l0 and pcie2x1l1 setting, which is
in PHP_GRF_PCIESEL_CON.
pcie1l0_sel
Select the signal form PHY to PCIe1l0
1'b0: Select comb PHY
1'b1: Select PCIE3 PHY

Usage in dts:
rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I5fb177f37b23c5f3cdaadf8c103f8e6487ea6a76
This commit is contained in:
Kever Yang
2021-11-14 21:25:34 +08:00
committed by Tao Huang
parent 7a6e007af7
commit e984bc2a96
1 changed files with 6 additions and 0 deletions
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6
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -289,6 +289,7 @@ static int rockchip_combphy_parse_dt(struct device *dev,
{
const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
int ret, mac_id;
u32 vals[4];
ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
if (ret == -EPROBE_DEFER)
@@ -322,6 +323,11 @@ static int rockchip_combphy_parse_dt(struct device *dev,
param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel,
true);
if (!device_property_read_u32_array(dev, "rockchip,pcie1ln-sel-bits",
vals, ARRAY_SIZE(vals)))
regmap_write(priv->pipe_grf, vals[0],
(GENMASK(vals[2], vals[1]) << 16) | vals[3]);
priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb");
if (IS_ERR(priv->apb_rst)) {
ret = PTR_ERR(priv->apb_rst);