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lcd: fix special clk mistake for vbyone [2/2]
PD#SWPL-12609 Problem: clk calculation mistake when use some special clk for vbyone Solution: fix special clk mistake for vbyone Verify: x301 Change-Id: If639f02a6ad9d3adeb87f46e3bb0e454e1148075 Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
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@@ -1132,17 +1132,21 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf)
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if (lcd_debug_print_flag == 2) {
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LCDPR("clk_div_in=%d, fout=%d, xd=%d, clk_div_out=%d\n",
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clk_div_in, cConf->fout,
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clk_div_out, cConf->xd);
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cConf->xd, clk_div_out);
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}
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if (clk_div_out > cConf->data->div_out_fmax)
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goto generate_clk_done_txl;
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clk_div_sel = clk_vid_pll_div_get(
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clk_div_in * 100 / clk_div_out);
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cConf->div_sel = clk_div_sel;
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if (clk_div_sel == CLK_DIV_SEL_MAX) {
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clk_div_sel = CLK_DIV_SEL_1;
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cConf->xd *= clk_div_in / clk_div_out;
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} else
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cConf->div_sel = clk_div_sel;
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if (lcd_debug_print_flag == 2) {
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LCDPR("clk_div_sel=%s(index %d)\n",
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LCDPR("clk_div_sel=%s(index %d), xd=%d\n",
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lcd_clk_div_sel_table[clk_div_sel],
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cConf->div_sel);
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cConf->div_sel, cConf->xd);
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}
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done = check_pll_txl(cConf, pll_fout);
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if (done == 0)
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@@ -718,8 +718,8 @@ static void lcd_vbyone_config_set(struct lcd_config_s *pconf)
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LCDPR("change to min lane_num %d\n", minlane);
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}
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bit_rate = band_width / minlane;
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phy_div = lane_count / minlane;
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bit_rate = band_width / lane_count;
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phy_div = lane_count / lane_count;
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if (phy_div == 8) {
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phy_div /= 2;
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bit_rate /= 2;
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@@ -1342,8 +1342,8 @@ static void lcd_vbyone_config_set(struct lcd_config_s *pconf)
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LCDPR("change to min lane_num %d\n", minlane);
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}
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bit_rate = band_width / minlane;
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phy_div = lane_count / minlane;
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bit_rate = band_width / lane_count;
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phy_div = lane_count / lane_count;
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if (phy_div == 8) {
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phy_div /= 2;
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bit_rate /= 2;
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