lcd: fix special clk mistake for vbyone [2/2]

PD#SWPL-12609

Problem:
clk calculation mistake when use some special clk for vbyone

Solution:
fix special clk mistake for vbyone

Verify:
x301

Change-Id: If639f02a6ad9d3adeb87f46e3bb0e454e1148075
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2019-08-13 11:28:27 +08:00
committed by Tao Zeng
parent a15846b953
commit e99612d4bf
3 changed files with 12 additions and 8 deletions

View File

@@ -1132,17 +1132,21 @@ static void lcd_clk_generate_txl(struct lcd_config_s *pconf)
if (lcd_debug_print_flag == 2) {
LCDPR("clk_div_in=%d, fout=%d, xd=%d, clk_div_out=%d\n",
clk_div_in, cConf->fout,
clk_div_out, cConf->xd);
cConf->xd, clk_div_out);
}
if (clk_div_out > cConf->data->div_out_fmax)
goto generate_clk_done_txl;
clk_div_sel = clk_vid_pll_div_get(
clk_div_in * 100 / clk_div_out);
cConf->div_sel = clk_div_sel;
if (clk_div_sel == CLK_DIV_SEL_MAX) {
clk_div_sel = CLK_DIV_SEL_1;
cConf->xd *= clk_div_in / clk_div_out;
} else
cConf->div_sel = clk_div_sel;
if (lcd_debug_print_flag == 2) {
LCDPR("clk_div_sel=%s(index %d)\n",
LCDPR("clk_div_sel=%s(index %d), xd=%d\n",
lcd_clk_div_sel_table[clk_div_sel],
cConf->div_sel);
cConf->div_sel, cConf->xd);
}
done = check_pll_txl(cConf, pll_fout);
if (done == 0)

View File

@@ -718,8 +718,8 @@ static void lcd_vbyone_config_set(struct lcd_config_s *pconf)
LCDPR("change to min lane_num %d\n", minlane);
}
bit_rate = band_width / minlane;
phy_div = lane_count / minlane;
bit_rate = band_width / lane_count;
phy_div = lane_count / lane_count;
if (phy_div == 8) {
phy_div /= 2;
bit_rate /= 2;

View File

@@ -1342,8 +1342,8 @@ static void lcd_vbyone_config_set(struct lcd_config_s *pconf)
LCDPR("change to min lane_num %d\n", minlane);
}
bit_rate = band_width / minlane;
phy_div = lane_count / minlane;
bit_rate = band_width / lane_count;
phy_div = lane_count / lane_count;
if (phy_div == 8) {
phy_div /= 2;
bit_rate /= 2;