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clk: rockchip: rk3288: fix up the clk register for hclk_vio

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Change-Id: If07e27b1f88974fa0dcb2c8f719df6ba3c35dbcd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2017-04-11 11:11:56 +08:00
committed by Tao Huang
parent fb12dc10dc
commit ea0b81279a
2 changed files with 22 additions and 5 deletions
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22
drivers/clk/rockchip/clk-rk3288.c
View File

@@ -410,12 +410,10 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
RK3288_CLKGATE_CON(9), 1, GFLAGS),
COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 0, GFLAGS),
DIV(0, "hclk_vio", "aclk_vio0", 0,
RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK3288_CLKGATE_CON(3), 2, GFLAGS),
@@ -922,6 +920,22 @@ static void __init rk3288_clk_init(struct device_node *np)
RK3288_GRF_SOC_STATUS1);
rockchip_clk_register_branches(ctx, rk3288_clk_branches,
ARRAY_SIZE(rk3288_clk_branches));
if (of_machine_is_compatible("rockchip,rk3288w")) {
clk = clk_register_divider(NULL, "hclk_vio", "aclk_vio1", 0,
ctx->reg_base + RK3288_CLKSEL_CON(28), 8, 5,
DFLAGS, &ctx->lock);
} else {
clk = clk_register_divider(NULL, "hclk_vio", "aclk_vio0", 0,
ctx->reg_base + RK3288_CLKSEL_CON(28), 8, 5,
DFLAGS, &ctx->lock);
}
if (IS_ERR(clk))
pr_warn("%s: could not register clock hclk_vio: %ld\n",
__func__, PTR_ERR(clk));
else
rockchip_clk_add_lookup(ctx, clk, HCLK_VIO);
rockchip_clk_protect_critical(rk3288_critical_clocks,
ARRAY_SIZE(rk3288_critical_clocks));

5
include/dt-bindings/clock/rk3288-cru.h
View File

@@ -116,6 +116,8 @@
#define ACLK_VCODEC 208
#define ACLK_CPU 209
#define ACLK_PERI 210
#define ACLK_VIO0 211
#define ACLK_VIO1 212
/* pclk gates */
#define PCLK_GPIO0 320
@@ -204,8 +206,9 @@
#define HCLK_CPU 477
#define HCLK_PERI 478
#define HCLK_USB_PERI 479
#define HCLK_VIO 480
#define CLK_NR_CLKS (HCLK_PERI + 1)
#define CLK_NR_CLKS (HCLK_VIO + 1)
/* soft-reset indices */
#define SRST_CORE0 0