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[ARM] tegra: remove inner-writeback memory type from SMP startup

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the memory remapping (NMRR) registers were configured differently
by the SMP and LP2 startup code from the standard kernel.

temporarily reverting the inner-writeback change for now.

Change-Id: Ib9c4fc75580d1cc705a5dd83377c0703669bcabc
Signed-off-by: Gary King <gking@nvidia.com>
This commit is contained in:
Gary King
2010-09-15 09:24:35 -07:00
committed by Rebecca Schultz Zavin
parent 54d4145704
commit ea3f8f2347
1 changed files with 2 additions and 2 deletions
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4
arch/arm/mach-tegra/cortex-a9.S
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@@ -665,8 +665,8 @@ ENTRY(__return_to_virtual)
mov r0, #0x1f
mcr p15, 0, r0, c3, c0, 0 @ domain access register
mov32 r0, 0xff0a89a8
mov32 r1, 0x40e044e0
mov32 r0, 0xff0a81a8
mov32 r1, 0x40e040e0
mcr p15, 0, r0, c10, c2, 0 @ PRRR
mcr p15, 0, r1, c10, c2, 1 @ NMRR
mrc p15, 0, r0, c1, c0, 0