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FROMLIST: clk: rockchip: rk3399: add ddrc clock support

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Add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.

Change-Id: Ib743ffb642fe0c7c0a3b7db14389803595d868b3
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
This commit is contained in:
huang lin
2016-08-22 11:36:19 +08:00
committed by Jianqun Xu
parent 00fed37569
commit eaab9a9982
1 changed files with 19 additions and 0 deletions
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19
drivers/clk/rockchip/clk-rk3399.c
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@@ -139,6 +139,10 @@ PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
"clk_core_b_bpll_src",
"clk_core_b_dpll_src",
"clk_core_b_gpll_src" };
PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
"clk_ddrc_bpll_src",
"clk_ddrc_dpll_src",
"clk_ddrc_gpll_src" };
PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
"gpll_aclk_cci_src",
"npll_aclk_cci_src",
@@ -1405,6 +1409,18 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(58), 0, 5, DFLAGS,
RK3368_CLKGATE_CON(13), 11, GFLAGS),
/* ddrc */
GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3),
0, GFLAGS),
GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3),
1, GFLAGS),
GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3),
2, GFLAGS),
GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3),
3, GFLAGS),
COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrclk_p, 0,
RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
};
static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
@@ -1542,6 +1558,9 @@ static const char *const rk3399_cru_critical_clocks[] __initconst = {
"hclk_isp1_noc",
"aclk_gic_noc",
/* ddrc */
"sclk_ddrc",
/* other critical clocks */
"pclk_perilp0",
"pclk_perilp0",