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nvmem: rockchip-efuse: add support for rk3288 secure efuse

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This adds the necessary data for handling secure efuse on the rk3288.
Need to use secure interface to access efuse when kernel is in no-secure
mode.

Change-Id: I1979f23ed8f85c9eb248de276b32adcbb165bd79
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
This commit is contained in:
Finley Xiao
2017-04-05 18:01:48 +08:00
committed by Tao Huang
parent 6af4d023f1
commit eb0712d68f
2 changed files with 51 additions and 0 deletions
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1
Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt
View File

@@ -6,6 +6,7 @@ Required properties:
- "rockchip,rk3188-efuse" - for RK3188 SoCs.
- "rockchip,rk3228-efuse" - for RK3228 SoCs.
- "rockchip,rk3288-efuse" - for RK3288 SoCs.
- "rockchip,rk3288-secure-efuse" - for RK3288 SoCs.
- "rockchip,rk3328-efuse" - for RK3328 SoCs.
- "rockchip,rk3368-efuse" - for RK3368 SoCs.
- "rockchip,rk3399-efuse" - for RK3399 SoCs.

50
drivers/nvmem/rockchip-efuse.c
View File

@@ -102,6 +102,52 @@ static int rockchip_rk3288_efuse_read(void *context, unsigned int offset,
return 0;
}
static int rockchip_rk3288_efuse_secure_read(void *context,
unsigned int offset,
void *val, size_t bytes)
{
struct rockchip_efuse_chip *efuse = context;
u8 *buf = val;
u32 wr_val;
int ret;
ret = clk_prepare_enable(efuse->clk);
if (ret < 0) {
dev_err(efuse->dev, "failed to prepare/enable efuse clk\n");
return ret;
}
sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
RK3288_LOAD | RK3288_PGENB);
udelay(1);
while (bytes--) {
wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
(~(RK3288_A_MASK << RK3288_A_SHIFT));
sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
((offset++ & RK3288_A_MASK) << RK3288_A_SHIFT);
sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
udelay(1);
wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) |
RK3288_STROBE;
sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
udelay(1);
*buf++ = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_DOUT);
wr_val = sip_smc_secure_reg_read(efuse->phys + REG_EFUSE_CTRL) &
(~RK3288_STROBE);
sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL, wr_val);
udelay(1);
}
/* Switch to standby mode */
sip_smc_secure_reg_write(efuse->phys + REG_EFUSE_CTRL,
RK3288_PGENB | RK3288_CSB);
clk_disable_unprepare(efuse->clk);
return 0;
}
static int rockchip_rk3328_efuse_read(void *context, unsigned int offset,
void *val, size_t bytes)
{
@@ -287,6 +333,10 @@ static const struct of_device_id rockchip_efuse_match[] = {
.compatible = "rockchip,rk3288-efuse",
.data = (void *)&rockchip_rk3288_efuse_read,
},
{
.compatible = "rockchip,rk3288-secure-efuse",
.data = (void *)&rockchip_rk3288_efuse_secure_read,
},
{
.compatible = "rockchip,rk3328-efuse",
.data = (void *)&rockchip_rk3328_efuse_read,